JPS54112165A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPS54112165A JPS54112165A JP1944278A JP1944278A JPS54112165A JP S54112165 A JPS54112165 A JP S54112165A JP 1944278 A JP1944278 A JP 1944278A JP 1944278 A JP1944278 A JP 1944278A JP S54112165 A JPS54112165 A JP S54112165A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- junction
- conductive type
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE: To obtain a PN junction with no shift in position by forming the pattern of a doped oxide film on a Si substrate, etc., and by forming a PN junction in the substrate by injecting impurity ions, of the reverse conductive type to impurities in the film, from the entire surface including the film.
CONSTITUTION: Onto substrate 1 of wiring poly-crystal Si or Si substrate, doped oxide film 5 is adhered and patterning is done, but a PSG film for the diffusing formation of a N-type layer and a BSG film for the formation of a P-type layer are used. From the entire surface including film 5, impurity ions of the reverse conductive type as impurities contained in the substrate are injected and regions 7 and 8 different in conductive type are formed in the substrate through a heat treatment to make a PN junction. As a result, the position of the PN junction can be determined by self-alignment and variance in characteristics due to a shift in position does not occur. Further, only single photoetching process is required, so that the process of manufacture will be shortened.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1944278A JPS54112165A (en) | 1978-02-22 | 1978-02-22 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1944278A JPS54112165A (en) | 1978-02-22 | 1978-02-22 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54112165A true JPS54112165A (en) | 1979-09-01 |
Family
ID=11999407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1944278A Pending JPS54112165A (en) | 1978-02-22 | 1978-02-22 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54112165A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58123723A (en) * | 1982-01-19 | 1983-07-23 | Sumitomo Electric Ind Ltd | Impurity doping method onto semiconductor crystal |
| US5219768A (en) * | 1989-05-10 | 1993-06-15 | Oki Electric Industry Co., Ltd. | Method for fabricating a semiconductor device |
| US5661067A (en) * | 1995-07-26 | 1997-08-26 | Lg Semicon Co., Ltd. | Method for forming twin well |
-
1978
- 1978-02-22 JP JP1944278A patent/JPS54112165A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58123723A (en) * | 1982-01-19 | 1983-07-23 | Sumitomo Electric Ind Ltd | Impurity doping method onto semiconductor crystal |
| US5219768A (en) * | 1989-05-10 | 1993-06-15 | Oki Electric Industry Co., Ltd. | Method for fabricating a semiconductor device |
| US5661067A (en) * | 1995-07-26 | 1997-08-26 | Lg Semicon Co., Ltd. | Method for forming twin well |
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