JPS54109772A - Resist coating method - Google Patents

Resist coating method

Info

Publication number
JPS54109772A
JPS54109772A JP1660778A JP1660778A JPS54109772A JP S54109772 A JPS54109772 A JP S54109772A JP 1660778 A JP1660778 A JP 1660778A JP 1660778 A JP1660778 A JP 1660778A JP S54109772 A JPS54109772 A JP S54109772A
Authority
JP
Japan
Prior art keywords
resist
substrate
linear
baking
inter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1660778A
Other languages
Japanese (ja)
Inventor
Shuji Endo
Shuzo Oshio
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1660778A priority Critical patent/JPS54109772A/en
Publication of JPS54109772A publication Critical patent/JPS54109772A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE: To prevent the second dispersion of the linear resist onto the substrate from the periphery of the substrate and thus to obtain the flat pattern by giving the spin-coating of the resist onto the substrate while spraying the inactive gas to the surface to be coated.
CONSTITUTION: The Si substrae is rotated at 4000rpm, and the positive resist of 35cp viscosity is dropped down to the center. At the same time, the N2 gas is sprayed toward the center and vertically to the substrate. Thus, no linear protrusion is caused to the coated resist. Also, the exposure is given via the electron beam to secure the 1μm inter-line space after the pre-baking, and then the development is given with the methyl isobutyl ketone solution. After this, no linear resist is left at the inter-line space even though the after-baking may be applied. As a result, a high-accuracy pattern can be obtained when the Al film pattern is formed on the resist.
COPYRIGHT: (C)1979,JPO&Japio
JP1660778A 1978-02-17 1978-02-17 Resist coating method Pending JPS54109772A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1660778A JPS54109772A (en) 1978-02-17 1978-02-17 Resist coating method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1660778A JPS54109772A (en) 1978-02-17 1978-02-17 Resist coating method

Publications (1)

Publication Number Publication Date
JPS54109772A true JPS54109772A (en) 1979-08-28

Family

ID=11920982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1660778A Pending JPS54109772A (en) 1978-02-17 1978-02-17 Resist coating method

Country Status (1)

Country Link
JP (1) JPS54109772A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60171115A (en) * 1984-02-17 1985-09-04 Toray Ind Inc Preparation of thin film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60171115A (en) * 1984-02-17 1985-09-04 Toray Ind Inc Preparation of thin film
JPH0416429B2 (en) * 1984-02-17 1992-03-24 Toray Industries

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