JPS54104744A - Signal input circuit to computer - Google Patents

Signal input circuit to computer

Info

Publication number
JPS54104744A
JPS54104744A JP1172278A JP1172278A JPS54104744A JP S54104744 A JPS54104744 A JP S54104744A JP 1172278 A JP1172278 A JP 1172278A JP 1172278 A JP1172278 A JP 1172278A JP S54104744 A JPS54104744 A JP S54104744A
Authority
JP
Japan
Prior art keywords
data
computer
sampling
input signal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1172278A
Other languages
Japanese (ja)
Inventor
Kuniharu Murata
Naotake Takatsukasa
Toyoaki Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1172278A priority Critical patent/JPS54104744A/en
Publication of JPS54104744A publication Critical patent/JPS54104744A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable the input of a number of asynchronous serial digital signals, by utilizing the programmable peripheral interface having the latch circuit and the interrupt function to computer and increasing the number of the latch circuits in the permissible range of the processing speed of computer.
CONSTITUTION: The circuit is provided with the programmable peripheral interface 17 latching the input signal from the asynchronous serial digital signal lines 1 to 16, and the latched timing signal is fed from the demultiplier 18 demultiplying the reference signal of the microcomputer 19. Further, the input signal is sampled with the timing of 1/(2n+1) (where: n is an integer more than 1) of the nominal delivery speed, and the sampling and the sampling data immediately before it are compared. If there is a change between the logical value of the both data, the n-th data from the sampling time point is judged as true data, if no change, the data at 2n+1-th data from the sampling time point judging immediately before the true data is judged as the data of continuous input signal.
COPYRIGHT: (C)1979,JPO&Japio
JP1172278A 1978-02-03 1978-02-03 Signal input circuit to computer Pending JPS54104744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1172278A JPS54104744A (en) 1978-02-03 1978-02-03 Signal input circuit to computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1172278A JPS54104744A (en) 1978-02-03 1978-02-03 Signal input circuit to computer

Publications (1)

Publication Number Publication Date
JPS54104744A true JPS54104744A (en) 1979-08-17

Family

ID=11785924

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1172278A Pending JPS54104744A (en) 1978-02-03 1978-02-03 Signal input circuit to computer

Country Status (1)

Country Link
JP (1) JPS54104744A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58172742A (en) * 1982-04-05 1983-10-11 Oki Electric Ind Co Ltd Reading system for analog-to-digital conversion data
JPH0495478U (en) * 1991-01-16 1992-08-19

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58172742A (en) * 1982-04-05 1983-10-11 Oki Electric Ind Co Ltd Reading system for analog-to-digital conversion data
JPS6318212B2 (en) * 1982-04-05 1988-04-18 Oki Electric Ind Co Ltd
JPH0495478U (en) * 1991-01-16 1992-08-19

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