JPS54101262A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS54101262A
JPS54101262A JP727378A JP727378A JPS54101262A JP S54101262 A JPS54101262 A JP S54101262A JP 727378 A JP727378 A JP 727378A JP 727378 A JP727378 A JP 727378A JP S54101262 A JPS54101262 A JP S54101262A
Authority
JP
Japan
Prior art keywords
bump
layer
bonding
sio
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP727378A
Other languages
Japanese (ja)
Other versions
JPS617743B2 (en
Inventor
Toru Kawanobe
Keiji Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP727378A priority Critical patent/JPS54101262A/en
Publication of JPS54101262A publication Critical patent/JPS54101262A/en
Publication of JPS617743B2 publication Critical patent/JPS617743B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To establish the bonding method between bump and leads, which can effectively prevent the side etching lower the Au bump and can easily perform Au- Au press bonding.
CONSTITUTION: The Au bump 1 is formed on the specified wiring layer 4 via the back ground metal film 3 formed on the insulation film covering the surface of the semiconductor pellet 2 with selective Au plating through the use of the photo mask 5. The layer 6 is the first SiO2 layer formed with thermal oxidation and the layer 7 is the second SiO2 layer formed with CVD. Next, after providing Sn plating thinly on the surface of the Au bump 1, the photo mask is removed. Further, the unnecessary part of the back ground metal film 3 is removed with etching. Then, one end of the Cu lead 10 sticked on the carrier tape 9 made of polyimide resin is pressed on the Au bump 1 via the Sn film 8 of the Au bump 1, and the bonding of the bump 1 and the lead 10 is finished.
COPYRIGHT: (C)1979,JPO&Japio
JP727378A 1978-01-27 1978-01-27 Manufacture for semiconductor device Granted JPS54101262A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP727378A JPS54101262A (en) 1978-01-27 1978-01-27 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP727378A JPS54101262A (en) 1978-01-27 1978-01-27 Manufacture for semiconductor device

Publications (2)

Publication Number Publication Date
JPS54101262A true JPS54101262A (en) 1979-08-09
JPS617743B2 JPS617743B2 (en) 1986-03-08

Family

ID=11661413

Family Applications (1)

Application Number Title Priority Date Filing Date
JP727378A Granted JPS54101262A (en) 1978-01-27 1978-01-27 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS54101262A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5428889A (en) * 1991-09-09 1995-07-04 Hitachi Cable, Ltd. Method for manufacturing composite lead frame

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5428889A (en) * 1991-09-09 1995-07-04 Hitachi Cable, Ltd. Method for manufacturing composite lead frame

Also Published As

Publication number Publication date
JPS617743B2 (en) 1986-03-08

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