JPS54100674A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS54100674A
JPS54100674A JP769778A JP769778A JPS54100674A JP S54100674 A JPS54100674 A JP S54100674A JP 769778 A JP769778 A JP 769778A JP 769778 A JP769778 A JP 769778A JP S54100674 A JPS54100674 A JP S54100674A
Authority
JP
Japan
Prior art keywords
film
polycrystal
sio
regions
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP769778A
Other languages
Japanese (ja)
Inventor
Nobuo Kawamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP769778A priority Critical patent/JPS54100674A/en
Publication of JPS54100674A publication Critical patent/JPS54100674A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To obtain a IGFET of large mutual conductance with the distance between regions shortened, by oxidizing both flanks of a polycrystal Si gate electrode provided onto a semiconductor substrate and by diffusion-forming source and drain regions right under the boundary between the oxidized film and gate electrode.
CONSTITUTION: On the surface of P-type Si substrate 21, SiO2 film 22 and Si3N4 film 23 are stacked and adhered and on it, polycrystal Si film 24 and Si3N4 film 25 are formed. Next, a striped gate pattern is provided to film 25 by photoetching and used as a mask to oxidize polycrystal film 24 for partial conversion into SiO2 film 26, which is etched and removed. By using films 25 and 23 as masks, the flank of exposed gate polycrystal film 24 is oxidized to form SiO2 film 26, and N-type source and drain regions 27 and 28 are diffusion-formed that a PN junction surface will by produced right under the boundary between this film 26 and polycrystal film 24. As a result, the distance between regions 27 and 28 can be made below 0.1μm and the parasitic capacity becomes extremely small.
COPYRIGHT: (C)1979,JPO&Japio
JP769778A 1978-01-25 1978-01-25 Semiconductor device and its manufacture Pending JPS54100674A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP769778A JPS54100674A (en) 1978-01-25 1978-01-25 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP769778A JPS54100674A (en) 1978-01-25 1978-01-25 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPS54100674A true JPS54100674A (en) 1979-08-08

Family

ID=11672952

Family Applications (1)

Application Number Title Priority Date Filing Date
JP769778A Pending JPS54100674A (en) 1978-01-25 1978-01-25 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS54100674A (en)

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