JPS54100274A - Complementary mos integrated circuit device - Google Patents

Complementary mos integrated circuit device

Info

Publication number
JPS54100274A
JPS54100274A JP641178A JP641178A JPS54100274A JP S54100274 A JPS54100274 A JP S54100274A JP 641178 A JP641178 A JP 641178A JP 641178 A JP641178 A JP 641178A JP S54100274 A JPS54100274 A JP S54100274A
Authority
JP
Japan
Prior art keywords
region
groove
substrate
type
channels
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP641178A
Other languages
Japanese (ja)
Inventor
Matsuo Ichinose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP641178A priority Critical patent/JPS54100274A/en
Publication of JPS54100274A publication Critical patent/JPS54100274A/en
Pending legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE: To reduce the border region between two channels and thus to increase the density by forming a groove of 2∼10μm depth and 1∼20μm width through etching between the P and N channels on the Si single-crystal substrate.
CONSTITUTION: Groove 8 is formed through etching on Si substrate 7 with the depth of 2∼10μm and the width of 1∼20μm, and P--type region 9 is formed on substrate 7 of one side to hold groove 8 between. In such way, region 9 never extends owing to existence of groove 8 when the drive-in is given at the formation of region 9. Then P+-type stopper region 10 is formed at the bottom of groove 8, and N+-type stopper region 11 is formed on substrate 7 of the other side holding groove 8 between. P+-type layer 13 is formed through diffusion near region 11, and at the same time N+-type region 12 is formed within region 9. As a result, the two channels can be put close to each other, and region 11 can be omitted if groove 8 is filled with insulator material 14.
COPYRIGHT: (C)1979,JPO&Japio
JP641178A 1978-01-24 1978-01-24 Complementary mos integrated circuit device Pending JPS54100274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP641178A JPS54100274A (en) 1978-01-24 1978-01-24 Complementary mos integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP641178A JPS54100274A (en) 1978-01-24 1978-01-24 Complementary mos integrated circuit device

Publications (1)

Publication Number Publication Date
JPS54100274A true JPS54100274A (en) 1979-08-07

Family

ID=11637618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP641178A Pending JPS54100274A (en) 1978-01-24 1978-01-24 Complementary mos integrated circuit device

Country Status (1)

Country Link
JP (1) JPS54100274A (en)

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