JPS5342557A - Securing method of flip chips - Google Patents
Securing method of flip chipsInfo
- Publication number
- JPS5342557A JPS5342557A JP11832876A JP11832876A JPS5342557A JP S5342557 A JPS5342557 A JP S5342557A JP 11832876 A JP11832876 A JP 11832876A JP 11832876 A JP11832876 A JP 11832876A JP S5342557 A JPS5342557 A JP S5342557A
- Authority
- JP
- Japan
- Prior art keywords
- flip chips
- chips
- securing method
- substrate
- flip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
PURPOSE: To secure a multiplicity of chips on a substrate simply through one position aligning and enhance workability by providing guide holes of the same shape and size as those of flip chips in a substrate securing the flip chips and further beforehand mounting a guide sheet whose one surface is tackiness or adhesive property.
COPYRIGHT: (C)1978,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11832876A JPS5342557A (en) | 1976-09-29 | 1976-09-29 | Securing method of flip chips |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11832876A JPS5342557A (en) | 1976-09-29 | 1976-09-29 | Securing method of flip chips |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5342557A true JPS5342557A (en) | 1978-04-18 |
Family
ID=14733936
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11832876A Pending JPS5342557A (en) | 1976-09-29 | 1976-09-29 | Securing method of flip chips |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5342557A (en) |
-
1976
- 1976-09-29 JP JP11832876A patent/JPS5342557A/en active Pending
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