JPS5419357A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5419357A
JPS5419357A JP8484677A JP8484677A JPS5419357A JP S5419357 A JPS5419357 A JP S5419357A JP 8484677 A JP8484677 A JP 8484677A JP 8484677 A JP8484677 A JP 8484677A JP S5419357 A JPS5419357 A JP S5419357A
Authority
JP
Japan
Prior art keywords
production
semiconductor device
chips
mounting
remaining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8484677A
Other languages
Japanese (ja)
Inventor
Tetsuo Nakamura
Tetsuro Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8484677A priority Critical patent/JPS5419357A/en
Publication of JPS5419357A publication Critical patent/JPS5419357A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Dicing (AREA)

Abstract

PURPOSE: To use perforated pressure-sensitive adhesive tapes in order to prevent dislocation of chips in pre-mounting process and to considerably reduce the remaining of chips at the mounting.
COPYRIGHT: (C)1979,JPO&Japio
JP8484677A 1977-07-14 1977-07-14 Production of semiconductor device Pending JPS5419357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8484677A JPS5419357A (en) 1977-07-14 1977-07-14 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8484677A JPS5419357A (en) 1977-07-14 1977-07-14 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5419357A true JPS5419357A (en) 1979-02-14

Family

ID=13842154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8484677A Pending JPS5419357A (en) 1977-07-14 1977-07-14 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5419357A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63236944A (en) * 1987-03-25 1988-10-03 Shimadzu Corp Atomic absorption analysis instrument
JP2002025947A (en) * 2000-07-10 2002-01-25 Dowa Mining Co Ltd Manufacturing method for semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63236944A (en) * 1987-03-25 1988-10-03 Shimadzu Corp Atomic absorption analysis instrument
JP2002025947A (en) * 2000-07-10 2002-01-25 Dowa Mining Co Ltd Manufacturing method for semiconductor device

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