JPS52109871A - Lsi chip mounting system - Google Patents

Lsi chip mounting system

Info

Publication number
JPS52109871A
JPS52109871A JP2638576A JP2638576A JPS52109871A JP S52109871 A JPS52109871 A JP S52109871A JP 2638576 A JP2638576 A JP 2638576A JP 2638576 A JP2638576 A JP 2638576A JP S52109871 A JPS52109871 A JP S52109871A
Authority
JP
Japan
Prior art keywords
lsi chip
mounting system
chip mounting
make
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2638576A
Other languages
Japanese (ja)
Inventor
Katsuyuki Hamada
Seijiro Ueno
Makoto Mukai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2638576A priority Critical patent/JPS52109871A/en
Publication of JPS52109871A publication Critical patent/JPS52109871A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Abstract

PURPOSE: To make good for heat dissipation and to make higher the mounting density, by making a hole on multiple layer printed circuit board, and by inserting, fixing, and connecting the rod shape stud under the ceramic base on which LSI chip is die-bonded to this.
COPYRIGHT: (C)1977,JPO&Japio
JP2638576A 1976-03-11 1976-03-11 Lsi chip mounting system Pending JPS52109871A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2638576A JPS52109871A (en) 1976-03-11 1976-03-11 Lsi chip mounting system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2638576A JPS52109871A (en) 1976-03-11 1976-03-11 Lsi chip mounting system

Publications (1)

Publication Number Publication Date
JPS52109871A true JPS52109871A (en) 1977-09-14

Family

ID=12192053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2638576A Pending JPS52109871A (en) 1976-03-11 1976-03-11 Lsi chip mounting system

Country Status (1)

Country Link
JP (1) JPS52109871A (en)

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