JPS51137387A - Manufacturing method for a semiconductor - Google Patents
Manufacturing method for a semiconductorInfo
- Publication number
- JPS51137387A JPS51137387A JP6096775A JP6096775A JPS51137387A JP S51137387 A JPS51137387 A JP S51137387A JP 6096775 A JP6096775 A JP 6096775A JP 6096775 A JP6096775 A JP 6096775A JP S51137387 A JPS51137387 A JP S51137387A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- junction
- manufacturing
- layor
- covering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 230000000903 blocking effect Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
- H01L29/66393—Lateral or planar thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thyristors (AREA)
- Weting (AREA)
Abstract
PURPOSE:A method of forming simply the groove with a good shape arranging passive state layor covering PN junction on a semiconductor wafer where the voltage blocking PN junction is exposed to one main surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6096775A JPS51137387A (en) | 1975-05-23 | 1975-05-23 | Manufacturing method for a semiconductor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6096775A JPS51137387A (en) | 1975-05-23 | 1975-05-23 | Manufacturing method for a semiconductor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS51137387A true JPS51137387A (en) | 1976-11-27 |
Family
ID=13157682
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6096775A Pending JPS51137387A (en) | 1975-05-23 | 1975-05-23 | Manufacturing method for a semiconductor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS51137387A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5257236U (en) * | 1976-10-13 | 1977-04-25 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS498181A (en) * | 1972-05-10 | 1974-01-24 |
-
1975
- 1975-05-23 JP JP6096775A patent/JPS51137387A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS498181A (en) * | 1972-05-10 | 1974-01-24 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5257236U (en) * | 1976-10-13 | 1977-04-25 |
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