JPS4919023B1 - - Google Patents

Info

Publication number
JPS4919023B1
JPS4919023B1 JP12459170A JP12459170A JPS4919023B1 JP S4919023 B1 JPS4919023 B1 JP S4919023B1 JP 12459170 A JP12459170 A JP 12459170A JP 12459170 A JP12459170 A JP 12459170A JP S4919023 B1 JPS4919023 B1 JP S4919023B1
Authority
JP
Japan
Prior art keywords
areas
pad
mounting
substrate
folded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12459170A
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4919023B1 publication Critical patent/JPS4919023B1/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
JP12459170A 1970-01-02 1970-12-29 Pending JPS4919023B1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US35970A 1970-01-02 1970-01-02

Publications (1)

Publication Number Publication Date
JPS4919023B1 true JPS4919023B1 (it) 1974-05-14

Family

ID=21691183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12459170A Pending JPS4919023B1 (it) 1970-01-02 1970-12-29

Country Status (4)

Country Link
JP (1) JPS4919023B1 (it)
CH (1) CH540567A (it)
DE (1) DE2064856A1 (it)
GB (1) GB1337791A (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2521350B1 (fr) * 1982-02-05 1986-01-24 Hitachi Ltd Boitier porteur de puce semi-conductrice
EP0115514B1 (en) * 1982-08-10 1986-11-12 BROWN, David, Frank Chip carrier
DE102005044001B3 (de) 2005-09-14 2007-04-12 W.C. Heraeus Gmbh Laminiertes Substrat für die Montage von elektronischen Bauteilen

Also Published As

Publication number Publication date
CH540567A (de) 1973-08-15
DE2064856A1 (de) 1971-07-08
GB1337791A (en) 1973-11-21

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