GB1361400A - Method of electrically connecting a semi-conductor chip to a substrate - Google Patents

Method of electrically connecting a semi-conductor chip to a substrate

Info

Publication number
GB1361400A
GB1361400A GB6174570A GB6174570A GB1361400A GB 1361400 A GB1361400 A GB 1361400A GB 6174570 A GB6174570 A GB 6174570A GB 6174570 A GB6174570 A GB 6174570A GB 1361400 A GB1361400 A GB 1361400A
Authority
GB
United Kingdom
Prior art keywords
substrate
template
chip
semi
conductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB6174570A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ZF International UK Ltd
Original Assignee
Lucas Industries Ltd
Joseph Lucas Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lucas Industries Ltd, Joseph Lucas Industries Ltd filed Critical Lucas Industries Ltd
Priority to GB6174570A priority Critical patent/GB1361400A/en
Priority to AU37163/71A priority patent/AU449322B2/en
Priority to NL7117917A priority patent/NL7117917A/xx
Priority to DE19712165246 priority patent/DE2165246A1/en
Priority to FR7147599A priority patent/FR2121168A5/fr
Publication of GB1361400A publication Critical patent/GB1361400A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/099—Coating over pads, e.g. solder resist partly over pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

1361400 Soldering JOSEPH LUCAS (INDUSTRIES) Ltd 7 Dec 1971 [30 Dec 1970] 61745/70 Heading B3R [Also in Division H1] A semi-conductor chip 11 containing one or more circuit components is soldered at several places to a substrate 10, such as a printed circuit board, the areas at which soldering occurs being defined by apertures in a template 14 adhering to the substrate 10. The template 14 is not wettable by solder and may comprise an insulating glass layer formed on the substrate 10 by thick film printing. Prior to joining the chip and substrate together solder may be applied to the chip 11 as a flat land or a projecting pad and/or may be applied to the conductive strips 12 on the substrate 10 within the apertures in the template 14 so as to protrude above the template surface or so as not to so protrude.
GB6174570A 1970-12-13 1970-12-30 Method of electrically connecting a semi-conductor chip to a substrate Expired GB1361400A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
GB6174570A GB1361400A (en) 1970-12-30 1970-12-30 Method of electrically connecting a semi-conductor chip to a substrate
AU37163/71A AU449322B2 (en) 1970-12-13 1971-12-21 A method of electrically connecting a semiconductor chip toa substrate
NL7117917A NL7117917A (en) 1970-12-30 1971-12-27
DE19712165246 DE2165246A1 (en) 1970-12-30 1971-12-29 Method for electrically connecting a semiconductor piece to a substrate
FR7147599A FR2121168A5 (en) 1970-12-30 1971-12-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB6174570A GB1361400A (en) 1970-12-30 1970-12-30 Method of electrically connecting a semi-conductor chip to a substrate

Publications (1)

Publication Number Publication Date
GB1361400A true GB1361400A (en) 1974-07-24

Family

ID=10487398

Family Applications (1)

Application Number Title Priority Date Filing Date
GB6174570A Expired GB1361400A (en) 1970-12-13 1970-12-30 Method of electrically connecting a semi-conductor chip to a substrate

Country Status (4)

Country Link
DE (1) DE2165246A1 (en)
FR (1) FR2121168A5 (en)
GB (1) GB1361400A (en)
NL (1) NL7117917A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4818728A (en) * 1986-12-03 1989-04-04 Sharp Kabushiki Kaisha Method of making a hybrid semiconductor device
US4874721A (en) * 1985-11-11 1989-10-17 Nec Corporation Method of manufacturing a multichip package with increased adhesive strength

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2541044A1 (en) * 1983-02-21 1984-08-17 Ebauchesfabrik Eta Ag Method for mounting a printed-circuit board on a substrate
FR2567709B1 (en) * 1984-07-11 1990-11-09 Nec Corp GLITTER ASSEMBLY INCLUDING A MULTI-LAYER WIRING SUBSTRATE
FR2569052B1 (en) * 1984-08-10 1987-05-22 Thomson Csf METHOD FOR INTERCONNECTING INTEGRATED CIRCUITS

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3429040A (en) * 1965-06-18 1969-02-25 Ibm Method of joining a component to a substrate

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4874721A (en) * 1985-11-11 1989-10-17 Nec Corporation Method of manufacturing a multichip package with increased adhesive strength
US4818728A (en) * 1986-12-03 1989-04-04 Sharp Kabushiki Kaisha Method of making a hybrid semiconductor device

Also Published As

Publication number Publication date
FR2121168A5 (en) 1972-08-18
DE2165246A1 (en) 1972-07-13
NL7117917A (en) 1972-07-04
AU3716371A (en) 1973-06-28

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee