KR880011914A - 전기 도전 캐리어 플레이트를 포함하는 집적회로 - Google Patents

전기 도전 캐리어 플레이트를 포함하는 집적회로 Download PDF

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KR880011914A
KR880011914A KR1019880002803A KR880002803A KR880011914A KR 880011914 A KR880011914 A KR 880011914A KR 1019880002803 A KR1019880002803 A KR 1019880002803A KR 880002803 A KR880002803 A KR 880002803A KR 880011914 A KR880011914 A KR 880011914A
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conductor
support plate
terminal
serving
chip
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KR1019880002803A
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슈어만 조셉
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엔. 라이스 머레트
텍사스 인스트루먼츠 도이취랜드 게엠베하
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Publication of KR880011914A publication Critical patent/KR880011914A/ko

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Abstract

내용 없음

Description

전기 도전 캐리어 플레이트를 포함하는 집적회로
제1도는 본 발명에 따른 집적 회로내의지지 플레이트 및 도전체 스트립의 배역을 도시한 평면도.
제2도는 본 발명의 다른 실시예의 제1도와 유사한 도면.
제3도는 고주파 회로에 사용하기에 특히 적합한 제1도 실시예의 다른 형태를도시한 도면.

Claims (8)

  1. 전자 회로를 포함하는 반도체 칩, 칩이 장착된 전기 도전성 물질의지지 플레이트, 지지 플레이트의 평면에 거의 배치되고 지지 플레이트를 향해 연장되고 지지 플레이트에서 떨어진 단부에서 외부 전자 회로와의 접속을 이루기 위한 단자 도전체로서 형성되는 도전체 스트립, 및 지지 플레이트, 칩 및 도전체 스트립을 봉입하고 외부로 단자 도전체가 외향 돌출하는 하우징으로 구성되고, 선택된 도전체 스트립이 칩내의 전자 회로의 선택된 지점에 접속되며, 최소한 한 도전체가 접지 인가용으로 작요하는 집적회로에 있어서, 지지 플레이트(12)가 접지 인가용으로 작용하는 최소한 한 단자 도전체(22)를 향한 방향으로 오프 셋트되는 것을 특징으로 하는 집적 회로.
  2. 전자 회로를 포함하는 반도체 칩, 칩이 위에 장착된 전기 도전성 물질의지지 플레이트, 지지 플레이트의 평면에 거의 배치되고 지지 플레이트를 향해 연장되고 지지 플레이트에서 떨어진 단부에서 외부 전자 회로와의 접속을 이루기 위한 단자 도전체로서 형성되는 도전체 스트립, 및 지지 플레이트, 칩 및 도전체 스트립을 봉입하고 외부로 단자 도전체가 외향 돌출하는 하우징으로 구성되고, 선택된 도전체 스트립이 칩내의 전자 회로의 선택된 지점에 접속되며, 최소한 한 도전체가 접지 인가용으로 작용하는 집적 회로에 있어서, 지지 플레이트(12)가 접지 인가용으로 작용하는 최소한 한 단자 도전체(22)에 완전히 접속되는 것을 특징으로 하는 집적 회로.
  3. 전자 회로를 포함하는 반도체 칩, 칩이 위에 장착된 전기도전성 물질의 지지 플레이트, 지지 플레이트의 평면에 거의 배치도고지지 플레이트를 향해 연장되고 지지 플레이트에서 떨어진 단부에서 외부 전자 회로와의 접속을 이루기 위한 단자 도전체로서 형성되는 도전체 스트립, 및 지지 플레이트 및 도전체 스트립을 봉입하고 외부로 단자 도전체가 외향 돌출하는 하우징으로 구성되고, 선택된 도전체 스트립이 칩내의 전자 회로의 선택된 지점에 접속되며, 최소한 한 도전체가 접지 인가용으로 작용하는 집적 회로에 있어서, 지지 플레이트(12)가 접지 인가용으로 작용하는 최소한 단자 도전체(22)를 향한 방향으로 오프셋트 되고 단자 도전체(22)에 완전히 접속되는 것을 특징으로 하는 집적회로.
  4. 상기 항들 중의 어느 한 항에 있어서, 하우징(20)이, 접지 인가용으로 작용하는 작용하는 단자 도전체(22)가 횡 대칭선(20b)의 영역에 배치되고, 입력 신호 인가용으로 작용하는 단자도전체(22)가 횡 대칭선(20b)의 한 측상에 배역되며, 출력 신호 방출용으로 작용하는 단자 도전체(22)가 횡 대칭선(20b)으 다른 측상에 배열되는, 종 대칭 평면(20b) 및 횡 대칭 평면(20b)를 갖고 있는 장방형 베이스 형태로 되어 있고, 지지 플레이트(12)가 출력 신호 방출용으로 작용하는 단자 도전체(22)를 향한 방향으로 오프셋트 되는 것을 특징으로 하는 집적회로.
  5. 제4항에 있어서, 출력 신호 방출용으로 작용하는 단자 도전체(22)로 안내되는 도전체 스트립(18)이 입력 신호 인가용으로 작용하는 단자 도전체(22)로 안내되는 도전체 스트립보다 넓은 것을 특징으로 하는 집적 회로.
  6. 제4항 또는 제5항에 있어서, 출력 신호 방출용으로 작용하는 단자 도전체(22)로 안내되는 도전체 스트립(18)들 사이의 중간 공간에, 지지 플레이트(12)에 완전히 접속되는 차폐 도전체 스트립(24)가 제공되는 것을 특징으로 하는 집적회로.
  7. 상기 항들중의 어느 한 항에 있어서, 지지 플레이트(12)상의 칩 (10)이 지지 플레이트(12)에 전기 도전식으로 접속된 저-저항 반도체 물질의 기판(26), 및 이기판(26)위에 배치되고 실제 전자 회로를 포함하는 에피택셜 고-저항 반도체 층(28)으로 구성되고, 지지 플레이트(12)와 에피택셜 층내의 전자 회로의 최소한 한 접지 접속점 사이에 결속 접속부(16)이 형성되며, 지지 플레이트(12)와 접속되어 있는 전자 회로의 최소한 한 접지 접속점이 기판(26)과 함께 에피텍셜 층(28)내의 접촉 윈도우(32)를 통해 에피텍셜 층(28)에 접속되는 것을 특징으로 하는 집적 회로.
  8. 상기 항들중의 어느 한 항에 있어서, 입력 신호 인가용으로 작용하는 최소한 한 도전체 스트립(18d)의 양측상에 배치된 도전체 스트립(18e,18f) 및 출력 신호 방출용으로 작용하는 최소한 한 도전체 스트립(18a)의 양측상에 배치된 도전체 스트립(18b,18c)가지지 플레이트(12)에 완전히 접속되는 것을 특징으로 하는 집적 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880002803A 1987-03-18 1988-03-17 전기 도전 캐리어 플레이트를 포함하는 집적회로 KR880011914A (ko)

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DE87103957.4 1987-03-18
EP87103957A EP0282617A1 (de) 1987-03-18 1987-03-18 Integrierte Schaltung mit einer elektrisch leitenden Trägerplatte

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Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2638896B1 (fr) * 1988-11-08 1990-12-21 Bull Sa Boitier de circuit integre de haute densite, support de circuit integre et carte d'interconnexion en resultant
DE3942843A1 (de) * 1989-12-23 1991-06-27 Itt Ind Gmbh Deutsche Verkapselte monolithisch integrierte schaltung
US5695569A (en) * 1991-02-28 1997-12-09 Texas Instruments Incorporated Removal of metal contamination
JPH0536756A (ja) * 1991-07-30 1993-02-12 Mitsubishi Electric Corp 半導体装置用テープキヤリア及びその製造方法
JPH05251621A (ja) * 1992-03-05 1993-09-28 Mitsubishi Electric Corp 半導体集積回路
US5376909A (en) * 1992-05-29 1994-12-27 Texas Instruments Incorporated Device packaging
KR100306988B1 (ko) * 1992-10-26 2001-12-15 윌리엄 비. 켐플러 장치패키지
EP0654866A3 (en) * 1993-11-23 1997-08-20 Motorola Inc Carrier for connecting a semiconductor cube and manufacturing method.
KR970010676B1 (ko) * 1994-03-29 1997-06-30 엘지반도체 주식회사 반도체 패키지 및 이에 사용되는 리드 프레임
US5432678A (en) * 1994-05-12 1995-07-11 Texas Instruments Incorporated High power dissipation vertical mounted package for surface mount application
EP0682366A3 (en) * 1994-05-12 1996-03-06 Texas Instruments Inc Assembly of integrated circuit components.
US5781682A (en) * 1996-02-01 1998-07-14 International Business Machines Corporation Low-cost packaging for parallel optical computer link
US20050133241A1 (en) * 2003-12-18 2005-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Chip orientation and attachment method
JP2007088378A (ja) * 2005-09-26 2007-04-05 Mitsubishi Electric Corp 半導体モールドパッケージ

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4023053A (en) * 1974-12-16 1977-05-10 Tokyo Shibaura Electric Co., Ltd. Variable capacity diode device
CA1246755A (en) * 1985-03-30 1988-12-13 Akira Miyauchi Semiconductor device

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