JPS4838036A - - Google Patents

Info

Publication number
JPS4838036A
JPS4838036A JP47051779A JP5177972A JPS4838036A JP S4838036 A JPS4838036 A JP S4838036A JP 47051779 A JP47051779 A JP 47051779A JP 5177972 A JP5177972 A JP 5177972A JP S4838036 A JPS4838036 A JP S4838036A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP47051779A
Other versions
JPS5149535B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4838036A publication Critical patent/JPS4838036A/ja
Publication of JPS5149535B2 publication Critical patent/JPS5149535B2/ja
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0831Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP47051779A 1971-09-10 1972-05-26 Expired JPS5149535B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US17937671A 1971-09-10 1971-09-10

Publications (2)

Publication Number Publication Date
JPS4838036A true JPS4838036A (ja) 1973-06-05
JPS5149535B2 JPS5149535B2 (ja) 1976-12-27

Family

ID=22656338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP47051779A Expired JPS5149535B2 (ja) 1971-09-10 1972-05-26

Country Status (8)

Country Link
US (1) US3771137A (ja)
JP (1) JPS5149535B2 (ja)
CA (1) CA954231A (ja)
DE (1) DE2226382C3 (ja)
FR (1) FR2155203A5 (ja)
GB (1) GB1387043A (ja)
IT (1) IT953791B (ja)
SE (1) SE426110B (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5057340A (ja) * 1973-09-19 1975-05-19
JPS50120233A (ja) * 1974-03-05 1975-09-20

Families Citing this family (119)

* Cited by examiner, † Cited by third party
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FR2344094A1 (fr) * 1976-03-10 1977-10-07 Cii Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires
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JPS5849945B2 (ja) * 1977-12-29 1983-11-08 富士通株式会社 バツフア合せ方式
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JPS5680872A (en) * 1979-12-06 1981-07-02 Fujitsu Ltd Buffer memory control system
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US4507781A (en) * 1980-03-14 1985-03-26 Ibm Corporation Time domain multiple access broadcasting, multipoint, and conferencing communication apparatus and method
DE3012205C2 (de) * 1980-03-28 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Multiprozessor-Datenverarbeitungsanlage mit mehreren jeweils einem Prozessor zugeordneten Pufferspeichern
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US4814979A (en) * 1981-04-01 1989-03-21 Teradata Corporation Network to transmit prioritized subtask pockets to dedicated processors
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JPS60138653A (ja) * 1983-12-27 1985-07-23 Hitachi Ltd 階層記憶制御方式
US4905145A (en) * 1984-05-17 1990-02-27 Texas Instruments Incorporated Multiprocessor
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JPS6170654A (ja) * 1984-09-14 1986-04-11 Hitachi Ltd 分散処理システムにおける資源管理方式
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JP2568017B2 (ja) * 1992-03-12 1996-12-25 株式会社東芝 マイクロプロセッサ及びそれを使用したデータ処理システム
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JP4704659B2 (ja) 2002-04-26 2011-06-15 株式会社日立製作所 記憶装置システムの制御方法および記憶制御装置
JP2004110367A (ja) 2002-09-18 2004-04-08 Hitachi Ltd 記憶装置システムの制御方法、記憶制御装置、および記憶装置システム
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JP4386694B2 (ja) 2003-09-16 2009-12-16 株式会社日立製作所 記憶システム及び記憶制御装置
JP4598387B2 (ja) 2003-09-17 2010-12-15 株式会社日立製作所 記憶システム
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JP4307202B2 (ja) 2003-09-29 2009-08-05 株式会社日立製作所 記憶システム及び記憶制御装置
JP4307964B2 (ja) 2003-11-26 2009-08-05 株式会社日立製作所 アクセス制限情報設定方法および装置
JP2005202893A (ja) 2004-01-19 2005-07-28 Hitachi Ltd 記憶デバイス制御装置、ストレージシステム、プログラムを記録した記録媒体、情報処理装置、及びストレージシステムの制御方法
JP4391265B2 (ja) 2004-02-26 2009-12-24 株式会社日立製作所 ストレージサブシステムおよび性能チューニング方法
JP4646574B2 (ja) 2004-08-30 2011-03-09 株式会社日立製作所 データ処理システム
JP2006127028A (ja) 2004-10-27 2006-05-18 Hitachi Ltd 記憶システム及び記憶制御装置
JP2006134049A (ja) * 2004-11-05 2006-05-25 Hitachi Ltd ホスト装置が接続される制御装置の接続部とその制御装置が備える記憶デバイスとの間の論理パスを生成する装置及び方法
US8621154B1 (en) 2008-04-18 2013-12-31 Netapp, Inc. Flow based reply cache
US8161236B1 (en) 2008-04-23 2012-04-17 Netapp, Inc. Persistent reply cache integrated with file system
US8171227B1 (en) 2009-03-11 2012-05-01 Netapp, Inc. System and method for managing a flow based reply cache

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5057340A (ja) * 1973-09-19 1975-05-19
JPS546171B2 (ja) * 1973-09-19 1979-03-26
JPS50120233A (ja) * 1974-03-05 1975-09-20
JPS5812608B2 (ja) * 1974-03-05 1983-03-09 日本電気株式会社 デンシケイサンキシステム

Also Published As

Publication number Publication date
DE2226382A1 (de) 1973-03-15
DE2226382C3 (de) 1980-08-28
FR2155203A5 (ja) 1973-05-18
US3771137A (en) 1973-11-06
JPS5149535B2 (ja) 1976-12-27
DE2226382B2 (de) 1979-12-13
GB1387043A (en) 1975-03-12
CA954231A (en) 1974-09-03
SE426110B (sv) 1982-12-06
IT953791B (it) 1973-08-10

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