JPH11514450A - オフスクリーン領域を有するフレームバッファのリフレッシュを制御する回路および方法 - Google Patents

オフスクリーン領域を有するフレームバッファのリフレッシュを制御する回路および方法

Info

Publication number
JPH11514450A
JPH11514450A JP9510625A JP51062597A JPH11514450A JP H11514450 A JPH11514450 A JP H11514450A JP 9510625 A JP9510625 A JP 9510625A JP 51062597 A JP51062597 A JP 51062597A JP H11514450 A JPH11514450 A JP H11514450A
Authority
JP
Japan
Prior art keywords
area
data
display
refresh
frame buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9510625A
Other languages
English (en)
Japanese (ja)
Inventor
シャルマ，スディール
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cirrus Logic Inc
Original Assignee
Cirrus Logic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cirrus Logic Inc filed Critical Cirrus Logic Inc
Publication of JPH11514450A publication Critical patent/JPH11514450A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/048—Interaction techniques based on graphical user interfaces [GUI]
    • G06F3/0481—Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/048—Interaction techniques based on graphical user interfaces [GUI]
    • G06F3/0481—Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
    • G06F3/04817—Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance using icons
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/08—Cursor circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
JP9510625A 1995-08-28 1996-08-28 オフスクリーン領域を有するフレームバッファのリフレッシュを制御する回路および方法 Pending JPH11514450A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US51999295A 1995-08-28 1995-08-28
US08/519,992 1995-08-28
PCT/US1996/014062 WO1997008676A1 (en) 1995-08-28 1996-08-28 Circuits and methods for controlling the refresh of a frame buffer comprising an off-screen area

Publications (1)

Publication Number Publication Date
JPH11514450A true JPH11514450A (ja) 1999-12-07

Family

ID=24070741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9510625A Pending JPH11514450A (ja) 1995-08-28 1996-08-28 オフスクリーン領域を有するフレームバッファのリフレッシュを制御する回路および方法

Country Status (4)

Country Link
EP (1) EP0847571A1 (ko)
JP (1) JPH11514450A (ko)
KR (1) KR19990044196A (ko)
WO (1) WO1997008676A1 (ko)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4482979A (en) * 1982-02-04 1984-11-13 May George A Video computing system with automatically refreshed memory
JPS60113395A (ja) * 1983-11-25 1985-06-19 Hitachi Ltd メモリ制御回路
EP0482678B1 (en) * 1984-07-23 1998-01-14 Texas Instruments Incorporated Video system
GB2203316B (en) * 1987-04-02 1991-04-03 Ibm Display system with symbol font memory
US5058041A (en) * 1988-06-13 1991-10-15 Rose Robert C Semaphore controlled video chip loading in a computer video graphics system

Also Published As

Publication number Publication date
EP0847571A1 (en) 1998-06-17
WO1997008676A1 (en) 1997-03-06
KR19990044196A (ko) 1999-06-25

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