JPH11509691A - 肉厚導体を有するモノリシックマイクロ波回路の製造方法 - Google Patents
肉厚導体を有するモノリシックマイクロ波回路の製造方法Info
- Publication number
- JPH11509691A JPH11509691A JP9539686A JP53968697A JPH11509691A JP H11509691 A JPH11509691 A JP H11509691A JP 9539686 A JP9539686 A JP 9539686A JP 53968697 A JP53968697 A JP 53968697A JP H11509691 A JPH11509691 A JP H11509691A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductive
- region
- depositing
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 title claims description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000000034 method Methods 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 239000012212 insulator Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000000463 material Substances 0.000 claims description 44
- 238000005530 etching Methods 0.000 claims description 26
- 238000000151 deposition Methods 0.000 claims description 22
- 239000003990 capacitor Substances 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 230000002265 prevention Effects 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 3
- 238000004804 winding Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 235000012431 wafers Nutrition 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- 229910017758 Cu-Si Inorganic materials 0.000 description 1
- 229910017931 Cu—Si Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000012421 spiking Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
- H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/97—Specified etch stop material
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.肉厚金属導体を含むモノリシックマイクロ波集積回路を製造する方法であっ て、該方法が: a.シリコン基板上に絶縁体上シリコンの層構体を形成する工程と; b.前記シリコン層の少なくとも1つの所定領域に導電材料の層を形成すべ く不純物を添加する工程と; c.少なくとも前記導電材料層の上に絶縁層を堆積する工程と; d.前記絶縁層上の所定パターンの領域に、絶縁体に変えることのできる導 電性のエッチング防止材料層を堆積する工程であって、前記パターンが導電性の ままとすべき少なくとも1つの領域と、絶縁体に変えるべき少なくとも1つの領 域とを含むようにする導電性のエッチング防止材料層堆積工程と; e.前記導電性のエッチング防止材料層の上及び前記絶縁層の露出している 領域の上に前記肉厚金属導体の厚さに相当する厚さを有しているLTO材料製の 第1層を堆積する工程と; f.前記LTO材料製の第1層を、前記導電性のエッチング防止材料層のう ちの、前記絶縁体に変えるべき少なくとも1つの領域に相当する第1サブパター ンにエッチングして、前記少なくとも1つの領域を露出させ、且つ前記少なくと も1つの領域に相当する少なくとも1つの凹所を前記LTO材料層に形成するエ ッチング工程と; g.前記導電性のエッチング防止材料層の前記露出させた少なくとも1つの 領域を絶縁体に変える工程と; h.前記LTO材料製の第1層を、前記導電性のエッチング防止材料層のう ちの、導電性のままとすべき少なくとも1つの領域の少なくとも一部分に相当す る第2サブパターンにエッチングして、前記少なくとも一部分を露出させ、且つ 前記少なくとも一部分に相当する少なくとも1つの凹所を前記LTO材料層に形 成するエッチング工程と; i.前記LTO材料層に形成した凹所を画成する壁部の上及び前記露出させ た少なくとも一部分の上に薄い付着層を堆積する工程と; j.前記少なくとも1つの領域と、前記少なくとも一部分に対応する凹所に 、前記薄い付着層に付着し、且つそれぞれの肉厚導体を形成する金属導体材料を 充填する工程と; を具えていることを特徴とするモノリシックマイクロ波集積回路の製造方法。 2.a.前記肉厚導体の露出部分の上に導電性の不活性層を選択的に堆積する工 程と; b.前記不活性層の上及び前記LTO材料製の第1層の露出領域の上にLT O材料製の第2層を堆積する工程と; c.前記LTO材料製の第2層を選択的にエッチングして、前記不活性層に 前記肉厚導体の各1つへの電気的接点を形成すべき少なくとも1つの領域を露出 させるエッチング工程と; d.前記不活性層の露出した少なくとも1つの領域の上に導電層を選択的に 堆積して前記電気接点を形成する工程; も具えていることを特徴とする請求の範囲1に記載の方法。 3.前記シリコン基板の固有抵抗を100Ω−cm以上とすることを特徴とする 請求の範囲1又は2に記載の方法。 4.前記導電性のエッチング防止材料を、不純物を添加した多結晶シリコンとす ることを特徴とする請求の範囲1又は2に記載の方法。 5.前記導電性のエッチング防止材料層を酸化処理により絶縁体に変えることを 特徴とする請求の範囲4に記載の方法。 6.前記エッチング防止材料層のうちの導電性のままとすべき少なくとも1つの 領域が電極を構成することを特徴とする請求の範囲1に記載の方法。 7.前記電極がコンデンサの1つの構成要素を成すことを特徴とする請求の範囲 6に記載の方法。 8.前記エッチング防止材料層のうちの導電性のままとすべき少なくとも1つの 領域が抵抗を構成することを特徴とする請求の範囲1に記載の方法。 9.前記肉厚導体の少なくとも1つがインダクタを構成することを特徴とする請 求の範囲1に記載の方法。 10.少なくとも1つの肉厚導体がインダクタの巻線を形成することを特徴とす る請求の範囲9に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/647,386 | 1996-05-09 | ||
US08/647,386 US5652173A (en) | 1996-05-09 | 1996-05-09 | Monolithic microwave circuit with thick conductors |
PCT/IB1997/000464 WO1997042654A2 (en) | 1996-05-09 | 1997-04-30 | A method of making a monolithic microwave circuit with thick conductors |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11509691A true JPH11509691A (ja) | 1999-08-24 |
JP4145354B2 JP4145354B2 (ja) | 2008-09-03 |
Family
ID=24596794
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53968697A Expired - Fee Related JP4145354B2 (ja) | 1996-05-09 | 1997-04-30 | 肉厚導体を有するモノリシックマイクロ波回路の製造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US5652173A (ja) |
EP (1) | EP0838090B1 (ja) |
JP (1) | JP4145354B2 (ja) |
KR (1) | KR100435137B1 (ja) |
DE (1) | DE69735919T2 (ja) |
WO (1) | WO1997042654A2 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6150197A (en) * | 1997-04-25 | 2000-11-21 | The Whitaker Corp. | Method of fabricating heterolithic microwave integrated circuits |
KR100331226B1 (ko) * | 2000-02-23 | 2002-04-26 | 이상헌 | 다공성 산화 실리콘 기둥을 이용하여 형성한 초고주파용 소자 |
US6309922B1 (en) * | 2000-07-28 | 2001-10-30 | Conexant Systems, Inc. | Method for fabrication of on-chip inductors and related structure |
TW531806B (en) * | 2000-10-04 | 2003-05-11 | Infineon Technologies Ag | Method for fabricating a micorelectronic circuit having at least one monolithically integrated coil and micorelectonic circuit having at least one monolithically integrated coil |
US6534374B2 (en) | 2001-06-07 | 2003-03-18 | Institute Of Microelectronics | Single damascene method for RF IC passive component integration in copper interconnect process |
US6444517B1 (en) | 2002-01-23 | 2002-09-03 | Taiwan Semiconductor Manufacturing Company | High Q inductor with Cu damascene via/trench etching simultaneous module |
US7535100B2 (en) * | 2002-07-12 | 2009-05-19 | The United States Of America As Represented By The Secretary Of The Navy | Wafer bonding of thinned electronic materials and circuits to high performance substrates |
FR2929758B1 (fr) * | 2008-04-07 | 2011-02-11 | Commissariat Energie Atomique | Procede de transfert a l'aide d'un substrat ferroelectrique |
US10269702B2 (en) | 2016-01-29 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Info coil structure and methods of manufacturing same |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4418470A (en) * | 1981-10-21 | 1983-12-06 | General Electric Company | Method for fabricating silicon-on-sapphire monolithic microwave integrated circuits |
US4789648A (en) * | 1985-10-28 | 1988-12-06 | International Business Machines Corporation | Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias |
US4767724A (en) * | 1986-03-27 | 1988-08-30 | General Electric Company | Unframed via interconnection with dielectric etch stop |
US5162258A (en) * | 1988-10-17 | 1992-11-10 | Lemnios Zachary J | Three metal personalization of application specific monolithic microwave integrated circuit |
US5219787A (en) * | 1990-07-23 | 1993-06-15 | Microelectronics And Computer Technology Corporation | Trenching techniques for forming channels, vias and components in substrates |
NL9100094A (nl) * | 1991-01-21 | 1992-08-17 | Koninkl Philips Electronics Nv | Halfgeleiderinrichting en werkwijze ter vervaardiging van een dergelijke halfgeleiderinrichting. |
US5384281A (en) * | 1992-12-29 | 1995-01-24 | International Business Machines Corporation | Non-conformal and oxidizable etch stops for submicron features |
US5376574A (en) * | 1993-07-30 | 1994-12-27 | Texas Instruments Incorporated | Capped modular microwave integrated circuit and method of making same |
US5757077A (en) * | 1995-02-03 | 1998-05-26 | National Semiconductor Corporation | Integrated circuits with borderless vias |
-
1996
- 1996-05-09 US US08/647,386 patent/US5652173A/en not_active Expired - Lifetime
-
1997
- 1997-04-30 JP JP53968697A patent/JP4145354B2/ja not_active Expired - Fee Related
- 1997-04-30 EP EP97916615A patent/EP0838090B1/en not_active Expired - Lifetime
- 1997-04-30 DE DE69735919T patent/DE69735919T2/de not_active Expired - Fee Related
- 1997-04-30 WO PCT/IB1997/000464 patent/WO1997042654A2/en active IP Right Grant
- 1997-04-30 KR KR10-1998-0700151A patent/KR100435137B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
WO1997042654A2 (en) | 1997-11-13 |
DE69735919D1 (de) | 2006-06-29 |
US5652173A (en) | 1997-07-29 |
KR19990028850A (ko) | 1999-04-15 |
EP0838090B1 (en) | 2006-05-24 |
DE69735919T2 (de) | 2007-03-01 |
WO1997042654A3 (en) | 1998-02-05 |
KR100435137B1 (ko) | 2004-07-16 |
EP0838090A2 (en) | 1998-04-29 |
JP4145354B2 (ja) | 2008-09-03 |
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