JPH11330936A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce inductance induced noise at the time of inverting output while holding high speed of the inverting output operation of an output buffer. SOLUTION: Driving circuits 3 and 4 which drive control terminals of output transistors(TR) (MP1, MN1) constituting the output buffer 2 are decreased in driving capability to reduce the output current variation rate at the time of the output inverting operation of the output buffer, thereby reducing noise induced through an inductance in proportion to the current variation rate. At this time, delay of the output inverting operation accompanying the reduction of the driving capability of the driving circuits 3 and 4 is compensated through positive feedback operation by feedback control TRs MN3 and MP3. The feedback control TRs MN3 and MP3 perform positive feedback control over the conductances of the output TRs, having the control terminals coupled with external terminals, to the control terminals of the output TRs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for reducing noise generated when an output signal of an output buffer is switched in a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit for data processing or communication control requiring high speed operation with a large number of pins. The present invention relates to a technology effective when applied to a circuit.

[0002]

2. Description of the Related Art When an output signal of an output buffer is switched in a semiconductor integrated circuit, a current change occurs at an output terminal. A bonding wire or a lead frame connected to an external terminal of a semiconductor integrated circuit has a nonnegligible inductance component. Therefore, a current change with a large change rate induces noise through the inductance component.

In order to reduce such noise, the inductance component may be reduced and the rate of change of the output current may be reduced. That is, in a semiconductor integrated circuit,
The larger the number of output buffers that are simultaneously inverted, the faster the operation speed of the output inversion, and the larger the load capacitance component of the output, the larger the current change (di / dt) at the time of the output inversion by the output buffer. Become. Further, an undesirable inductance component is parasitic on the package and the socket of the semiconductor integrated circuit. With this in mind,
It is conceivable to reduce the inductance component by devising the shape of the package of the semiconductor integrated circuit and the arrangement of the power supply pins. For example, place power supply pins near the output circuit, and reduce the number of output pins of the package, reduce the output voltage amplitude, reduce the output capacitance component, and use inductive components such as sockets as much as possible. Can be considered.

[0004]

However, the reduction of the inductance component is contrary to the tendency to increase the number of pins of the semiconductor integrated circuit due to the improvement in the degree of integration of the semiconductor integrated circuit and the demand for the system LSI. Become. In addition, the power supply pins cannot always be arranged in the vicinity of the output buffer due to layout restrictions or the like.

An object of the present invention is to provide a semiconductor device which can reduce noise generated via an inductance component when an output signal of an output buffer is switched, even if it has a large number of pins or is to be operated at a high speed. It is to provide an integrated circuit.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, an output transistor (MP1) coupled to an external terminal (P), and a feedback terminal coupled to the external terminal for controlling the conductance of the output transistor in a positive feedback manner with respect to the control terminal of the output transistor. A configuration including a control transistor (MN3) is employed for the output buffer (2) of the semiconductor integrated circuit. During the output inversion operation of the output buffer, the feedback control transistor
It acts to expedite the determination of the output inversion operation. Therefore, even if the size or the driving ability of the driving transistor (Mp5, MP6) for driving the control terminal of the output transistor is reduced, the delay of the output inversion operation can be minimized. At this time, if the size or the driving ability of the driving transistor for driving the control terminal of the output transistor is small, the change in the current flowing through the output transistor during the output inversion operation can be relatively suppressed. If the current change rate is small, noise induced by the inductance component can be reduced in proportion to the current change rate.

As described above, the size or the driving ability of the drive transistor for driving the control terminal of the output transistor is reduced to reduce the output current change rate at the start of the output inversion operation, and the inductance is increased in proportion to the current change rate. The noise induced by the component is reduced, and at this time, the delay of the output inversion operation due to the reduction in the size or the driving ability of the driving transistor is compensated by the feedback control transistor. The transistor size of the driving transistor for achieving this can be, for example, 1/10 to 1/20 of the output transistor.

The output buffer according to a more specific mode comprises a first output transistor (MP1) and a second output transistor (MN) which are coupled to an external terminal and operated by a push-pull operation.
1) a first gate transistor (MN2) coupled to a control terminal of the first output transistor and turned on in synchronization with the on state of the first output transistor; and a series connection to the first gate transistor. A first feedback control transistor (MN3) having a control terminal coupled to the external terminal to enable positive feedback control of the conductance of the first output transistor with respect to the control terminal of the first output transistor; A first driving inverter (3) for driving the second output transistor; a second gate transistor (MP2) coupled to a control terminal of the second output transistor and turned on in synchronization with an on state of the second output transistor; The second output transistor is connected in series to a two-gate transistor and has a control terminal coupled to the external terminal; A second feedback control transistor (MP3) that enables positive feedback control of the conductance of the second output transistor with respect to a control terminal of the second output transistor, and a second feedback control transistor that enables the second output transistor to be driven complementarily with the first output transistor. And a two-drive inverter (4).

According to the invention of this aspect, the noise induced by the inductance component is reduced by reducing the change rate of the output current at the start of the output reversal operation by reducing the drive capability of the first and second drive inverters, At this time, the delay of the output inversion operation due to the reduction of the driving capability is compensated by the first feedback control transistor and the second feedback control transistor.

The specific functions of the semiconductor integrated circuit having the output buffer are not limited. For example, a central processing unit (14), a bus state controller (19) for starting bus access, and an input interface to the outside. The microcomputer may be provided with the output circuit (20) on one semiconductor substrate (1). In that case, the output buffer can be included in the input / output circuit.

[0013]

FIG. 1 shows an example of an output buffer included in a semiconductor integrated circuit according to the present invention. The output buffer 2 shown in FIG. 1 has a buffer circuit section 2A and a control circuit section 2B, and is formed on the semiconductor substrate 1. The buffer circuit section 2A has a final output stage CMOS inverter composed of a p-channel type first output MOS transistor MP1 and an n-channel type second output MOS transistor MN1 which are subjected to a push-pull operation. Is done. The operation power supply of the final output stage CMOS inverter is the power supply voltage Vdd and the ground voltage Vss.
In FIG. 1, the gate electrode of the p-channel MOS transistor is marked with a circle to distinguish it from the n-channel MOS transistor. MOS transistors MP7, MN
Reference numeral 7 is provided to protect the input gates of the MOS transistors MP1 and MN1.

The output terminal of the first drive inverter 3 is connected to the gate electrode of the first output MOS transistor MP1, and the output terminal of the second drive inverter 4 is connected to the gate electrode of the second output MOS transistor MP2. ing. The first drive inverter 3 is a MOS transistor MP
5, MP6, and the second drive inverter 4 is configured by a series circuit of MOS transistors MN5, MN6. The output MOS transistor M
In order to make P1 and MN1 perform a push-pull operation or to selectively bring them into a high output impedance state, the control circuit unit 2
B is a NOR gate 5, a NAND gate 6, and an inverter 7
Having. The push-pull operation of the first drive inverter 3 is controlled by the output signal of the NOR gate 5 and a signal obtained by inverting the output signal of the inverter 8. Controls the push-pull operation. The data signal 10 is data having a logical value to be output.
The control signal 11 indicates enable (activation) of the output buffer 2 by a logical value “0” (low level), and disables (deactivates) the output buffer 2 by a logical value “1” (high level). I do.

When the control signal 11 is set to a high level, M
The OS transistor MP5 is turned on to turn off the MOS transistor MP1, and the MOS transistor MN6 is turned on to turn on the MOS transistor MN1.
Is turned off, and the output buffer 2 is set to a high output impedance state. When the control signal 11 is at a low level and the data signal 10 is at a high level, the MOS transistor MP
5 is turned on to turn off the MOS transistor MP1, and the MOS transistor MN5 is turned on to turn on the MOS transistor MN1, and the output buffer 2 outputs a low level. When the control signal 11 is at a low level and the data signal 10 is at a low level, M
The OS transistor MP6 is turned on to turn on the MOS transistor MP1, and the MOS transistor MN6 is turned on to turn on the MOS transistor MN1.
Is turned off, and the output buffer 2 outputs a high level.

A series circuit of a first gate MOS transistor MN2 and a first feedback control MOS transistor MN3 is arranged between the gate electrode of the first output MOS transistor MP1 and the ground voltage Vss. A second gate MOS transistor MP is provided between the gate electrode of output MOS transistor MN1 and power supply voltage Vdd.
2 and a series circuit of the second feedback control MOS transistor MP3.

The gate electrode of the MOS transistor MN2 is connected to the output of the NOR gate 5, and the gate electrode of the MOS transistor MN3 is connected to the output terminal P in a feedback manner. Therefore, the MOS transistor MN2 is turned on in synchronization with the ON state of the MOS transistor MP1, and as a result, as the conductance of the MOS transistor MP1 increases, the level of the output terminal P approaches the power supply voltage Vdd. MOS transistor MN
3 is increased, and thereby the first
The conductance of the output MOS transistor MP1 is subjected to positive feedback control.

The gate electrode of the MOS transistor MP2 is coupled to the output of the NAND gate 6, and the gate electrode of the MOS transistor MP3 is connected to the output terminal P in a feedback manner. Therefore, the MOS transistor MP2 is turned on in synchronization with the ON state of the MOS transistor MN1,
Thereby, as the level of the output terminal P approaches the ground voltage Vss as the conductance of the MOS transistor MN1 increases, the conductance of the MOS transistor MP3 increases, thereby increasing the conductance of the second output MOS transistor MN1. Positive feedback control is performed. The positive feedback control acts to expedite the determination of the output inversion operation of the output buffer 2.

When the MOS transistor MP1 is turned on, the MOS transistor MN4 forces the gate electrode of the MOS transistor MP1 to the ground voltage Vss. When the MOS transistor MN1 is turned on, the MOS transistor MP4 forces the gate electrode of the MOS transistor MN1 to the power supply voltage Vdd.

Here, the MOS transistors MP5 and MP5
If the driving capability of the driving inverters 3 and 4 constituted by MP6 (MN5 and MN6) is large, the MOS transistor M
The inversion operation speed of the final output stage inverter constituted by P1 and MN1 is increased. On the other hand, the current change rate in the output reversal operation increases, and the noise induced via the inductance component increases. The size ratio of each of the MOS transistors MP5 and MP6 to the MOS transistor MP1 and the size ratio of each of the MOS transistors MN5 and MN6 to the MOS transistor MN1 are, for example, 1/10 to 1/20.
The size ratio is determined by the output buffer discussed earlier by the present inventors, ie, the MOS transistors MN2 and MN3 (MP
2, MP3), which is smaller than an output buffer (hereinafter also simply referred to as a comparative example circuit). In other words, the driving inverters 3 and 4 of FIG. 1 have smaller driving abilities than the driving inverters of the comparative example circuit. The current change rate in the output inversion operation is made smaller than that of the circuit of the comparative example, and the noise induced via the inductance component is also reduced by the smaller driving ability. On the other hand, it is expected that the determination of the inversion operation of the output buffer 2 will be delayed, but actually, the positive feedback control MOS transistors MN3, MPN
The positive feedback control by 3 makes the output inversion operation of the output buffer 2 more quickly determined. In short, the output MO
The transistor size or the driving capability of the drive inverters 3 and 4 for driving the control terminals of the S transistors MP1 and MN1 are reduced to reduce the output current change rate at the start of the output inversion operation, thereby being induced by the inductance component. The noise is reduced, and at this time, the delay of the output inversion operation due to the reduction in the transistor size or the driving capability of the driving inverters 3 and 4 is compensated by the feedback control MOS transistors MN3 and MP3.

Next, an example of the detailed operation of the output buffer 2 will be described with reference to FIGS. Here, an operation when the output terminal P is switched from a low level to a high level will be described as an example. FIG. 2 shows FIG.
The potential change of the node A is shown in comparison with the comparative example circuit. FIG. 3 shows how the drain current of the MOS transistor MP1 in FIG. 1 changes in comparison with the circuit of the comparative example. FIG. 4 shows the MOS transistor MP of FIG.
The change rate of the drain current of No. 1 is shown in comparison with the circuit of the comparative example. FIG. 5 shows a change in the potential of the output terminal P in comparison with the comparative example circuit. 2 to 4, when the transition response period from when the output of the output buffer changes from the low level to the high level is T, the first half is 0 to T1 and the second half is T1 to T.

As described above, as compared with the comparative example circuit, the output buffer 2 has the MOS transistor M constituting the final output stage.
The changes in the gate voltages of P1 and MN1 are moderated. This is because the driving capacity of the driving inverters 3 and 4 is smaller than that of the comparative example circuit. Therefore, as shown in the characteristics of the first half of FIG.
The change in the drain current of 1 is smaller in the output buffer 2. Therefore, the change rate of the drain current of the MOS transistor MP1 is smaller in the output buffer circuit 2 as illustrated in FIG. If the change rate of the drain current is reduced in this way, noise induced via the inductance component is also reduced.

On the other hand, as shown in the characteristics in the latter half of FIG.
In the case of the output buffer circuit 2, the positive feedback control MOS
By the positive feedback control by the transistor MN3, the node at the point A is sharply changed to the end in the latter half of the operation. In the case of the comparative example circuit, it becomes slow. The change of the drain current at this time is the same, and as illustrated in FIG.
In the case of the output buffer 2, the drain current gradually increases in the second half of the operation as in the first half. Therefore,
In the case of the output buffer 2, even if the change in the drain current in the first half of the output inversion operation is smaller than that in the comparative example circuit, the delay until the output inversion operation of the output buffer 2 is determined by the positive feedback control operation in the second half. Can compensate. As a result, as illustrated in FIG. 5, the determination of the output inversion operation of the output buffer 2 is maintained substantially equal to that of the comparative example circuit, while the current change rate is significantly reduced as illustrated in FIG. Noise induced by the inductance component can be reduced. Second in FIG.
The comparative example circuit assumes a circuit configuration that does not employ the positive feedback control configuration in the output buffer 2. Even though the generation of noise can be reduced, the determination of the output inversion operation is significantly delayed.

The same operation is performed when the output of the output buffer 2 is inverted from a high level to a low level. The only difference is the polarity of the signal change, and a detailed description of the operation is omitted.

FIG. 6 is a block diagram of a microcomputer to which the output buffer 2 is applied. The microcomputer 13 shown in FIG. 1 is formed on a semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique. Although not particularly limited, the microcomputer 13 includes a CPU (central processing unit) 14, a cache memory 15, a DMAC (direct memory access controller) 16, an INTC (interrupt controller) 17, an FPU (floating point arithmetic unit) 18,
It has a BSC (bus state controller) 19, an I / O (external input / output circuit) 20, and an internal bus 21. CP
U14 fetches an instruction, decodes the fetched instruction, performs an integer operation using an internal arithmetic circuit, or
The PU 18 performs floating point arithmetic operations, and performs an access operation for operands necessary for the arithmetic operations. The cache memory 15 temporarily stores instructions and data once accessed by the CPU 14 so that the memory access operation can be speeded up. When performing an external memory access in response to a cache miss or the like, the bus state controller 19 controls a bus cycle suitable for an access target area or the like. DMAC 16 responds to the DMA transfer request by C
Instead of the PU 14, a bus request is acquired and data transfer control is performed. The interrupt controller 17 performs priority control and mask control for the interrupt request signal. The external input / output circuit 20 forms an I / O port connected to an external bus or the like, and the output circuit or the input / output circuit includes the output buffer 2 described with reference to FIG.

The microcomputer 13 has a large number of bonding pads and metal bump electrodes on a semiconductor substrate, which are connected to bonding wires, beam leads and the like, and are connected to pins or leads of a package. In the microcomputer packaged in this manner, semiconductor integrated circuits tend to have more pins due to demands for higher integration, higher functionality, and system LSIs, and the number of pins reduces the inductance component. Has limitations. In addition, the power supply pins cannot always be arranged in the vicinity of the output buffer due to layout restrictions or the like. Whether to use inductive components such as sockets depends on the circumstances of the system set manufacturer. Considering these circumstances, the output buffer 2
Can reliably reduce inductive noise at the time of output inversion operation. In other words, a part of the power supply pins and ground pins arranged for the purpose of suppressing noise can be partially assigned to the signal pins, which can contribute to the elimination of the pin neck.

Although the invention made by the inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, the output buffer is not limited to a CMOS circuit. The push-pull circuit of the final output stage may be constituted by an N-channel MOS transistor.
It goes without saying that the output buffer according to the present invention can also be applied to an output buffer in an input / output buffer. The semiconductor integrated circuit according to the present invention is not limited to a microcomputer, but may be any other logic LSI such as a communication protocol processor, a memory LSI such as a static RAM or a flash memory, an analog LSI, or an analog / digital mixed LSI. It can be applied to circuits.

[0029]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the size or the driving ability of the driving transistor for driving the control terminal of the output transistor is reduced to reduce the output current change rate at the start of the output inversion operation, and the output current is induced in proportion to the current change rate. The noise is reduced, and at this time, the delay of the output inversion operation due to the reduction in the size or the driving capability of the driving transistor is
Since compensation is performed by the feedback control transistor, inductive noise generated due to a current change and an inductance component during the inversion output operation can be reduced without impeding the speeding up of the inversion output operation.

Since the inductive noise at the time of the output inversion operation can be reduced, a part of the power supply pins and the ground pins arranged for the purpose of suppressing the noise can be partially allocated to the signal pins, and the pin neck can be eliminated. Can contribute.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of an output buffer included in a semiconductor integrated circuit according to the present invention.

FIG. 2 is a characteristic diagram showing a potential change of a node A in FIG. 1 in comparison with a circuit of a comparative example.

FIG. 3 is a characteristic diagram showing a state of a change in a drain current of the MOS transistor MP1 of FIG. 1 in comparison with a circuit of a comparative example.

FIG. 4 is a characteristic diagram showing a change rate of a drain current of the MOS transistor MP1 of FIG. 1 in comparison with the comparative example circuit.

FIG. 5 is a characteristic diagram showing a potential change of an output terminal P in comparison with the circuit of the comparative example.

FIG. 6 is a block diagram illustrating an example of a microcomputer to which an output buffer is applied.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 output buffer MP1 first output MOS transistor MN1 second output MOS transistor 3 first drive inverter 4 second drive inverter P output terminal MN2 first gate MOS transistor MP2 second gate MOS transistor MN3 first feedback control MOS transistor MP3 second feedback control MOS transistor 13 microcomputer 14 CPU 19 bus state controller 20 external input / output circuit

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hiroshi Saito 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Cho-SII Systems Co., Ltd.

Claims (4)

[Claims] 1. A semiconductor integrated circuit having an output buffer, wherein the output buffer has an output transistor coupled to an external terminal, and a control terminal coupled to the external terminal. A feedback control transistor that performs positive feedback control on the conductance of the output transistor. 2. A driving transistor for driving a control terminal of the output transistor, wherein a size of the driving transistor is 1/10 to 1/20 of the output transistor.
3. The semiconductor integrated circuit according to claim 2, wherein 3. A semiconductor integrated circuit having an output buffer, wherein the output buffer is connected to an external terminal and has a first output transistor and a second output transistor that are operated by a push-pull operation, and controls the first output transistor. A first gate transistor coupled to a terminal and turned on in synchronization with an on state of the first output transistor; a first terminal connected in series to the first gate transistor and having a control terminal coupled to the external terminal; A first feedback control transistor that enables positive feedback control of the conductance of the first output transistor with respect to a control terminal of the transistor, a first drive inverter that drives the first output transistor, and a control terminal of the second output transistor And a second gate which is turned on in synchronization with the on state of the second output transistor. And a control terminal connected to the external terminal in series with the gate transistor and the second gate transistor so that the conductance of the second output transistor can be positively controlled with respect to the control terminal of the second output transistor. A second feedback control transistor;
A second drive inverter that enables the second output transistor to be driven complementarily with the first output transistor. 4. A microcomputer comprising a central processing unit, a bus state controller for activating a bus access, and an input / output circuit interfaced with the outside on a single semiconductor substrate. 4. The semiconductor integrated circuit according to claim 1, further comprising a buffer.