JPH043512A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent increase in power consumption by using an output buffer H bridge circuit and a buffer circuit driving the bridge circuit as output circuits so as to reduce a through-current. CONSTITUTION:A relative ratio of ON-resistance of P-channel and N-channel MOS transistors(TRs) in a CMOS inverter driving four N-channel MOS TRs 5-8 of an output buffer H bridge circuit is increased to obtain an output waveform with a slow leading and a fast trailing. That is, When an internal input terminal 1 goes to L and an internal input terminal 2 goes to H, the MOS TRs 5, 8 are turned off and the MOS TRs 6, 7 are turned on. A state of turning-on of both the TRs of power supply side and ground terminal side is caused in the transient state change and a through-current flows. Thus, the increase in the power consumption when the leading and trailing of the input signal are slow is prevented.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device that controls a motor, etc., and in particular, to an MO3 semiconductor integrated device that can prevent an increase in power consumption when the rise and fall of an input signal is slow. Regarding circuits.

[Conventional technology]

Figure 5 shows the MO8 that controls conventional motors, etc.
This is an example of a semiconductor integrated circuit. In Fig. 5, 1 is the input terminal, 2 is the power supply terminal 1, and the voltage is ■. . 23 is a ground terminal,
4 is the power supply terminal 2 whose voltage is VM, 5 is the first M03 transistor, 6 is the second M08 transistor, 7 is the third M03 transistor, and 8 is the fourth M08 transistor. It constitutes an output Zuffa H bridge circuit. 9 is an output terminal 1, and 10 is an output terminal 2, and a load such as a motor is connected between the terminals 9 and 10. 11 is internal input terminal 1, 12 is internal input terminal 2, 13 is internal input terminal 3, 1
4 is an internal input terminal 4, 15 is a CMOS inverter circuit l
, 16 is a CMOS inverter circuit 2, and 17 is a control circuit.

Next, the operation of the circuit configured as described above will be explained. When the level of internal input terminal 1 of 11 is "H", 5
Since the MOS transistors 8 and 8 are turned on, the output terminal 9 becomes 1-, and the output terminal 2 of 10 becomes =Ov. When the level of the internal input terminal 2 of 12 is rHJ, the MOS transistors 6 and 7 are turned on, so the output terminal 1 of 9 becomes =Ov, and the output terminal 2 of 10 becomes UvH. Here, internal input terminal 1. The levels of and 2 are controlled by 17 control circuits so that they do not become rHJ at the same time. However, when the output buffer H-bridge circuit is configured with four N-channel MO8 transistors as in the circuit shown in Figure 5, the MOS transistor on the power supply terminal 2 side of 4 has a higher switching ability than the MOS transistor on the ground terminal side. Due to slow speed, M of 5 and 6
There is a time when the OS transistor or the 7 and 80M0S transistors are on at the same time, and the power supply terminal 2 of 4
Therefore, a through current flows through the two MOS transistors toward the ground terminal 3, and that extra power is consumed.

[Problem to be solved by the invention]

As described above, when an output H-bridge circuit is constructed using N-channel MOS transistors, there is a problem in that a through current flows due to the difference in switching speed between the power supply side transistor and the ground side transistor, resulting in increased power consumption. In addition, this through current causes the power terminals 2 and 3 of 4 to
A large spike noise is generated at the ground terminal of the IC, which may cause the IC to malfunction.

[Means to solve the problem]

In the circuit of the present invention, the relative on-resistance ratio of the P-channel transistor and the N-channel transistor is increased to, for example, 40:1 with respect to the CMOS inverter that is the previous stage buffer that drives the output buffer H-bridge circuit.
The output waveform has a slow rise and a fast fall.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an embodiment of a circuit diagram related to the present invention. Fifth
The difference from the conventional circuit diagram shown in the figure is the output buffer H.
The point is that the relative on-resistance ratio of the P-channel MO3 transistor of the CMOS inverter that drives the four N-channel MO3 transistors of the bridge circuit and the N-channel MO3 transistor is set to be as large as 40:1, for example. Next, the operation of the circuit shown in FIG. 1 will be explained. 11 internal input terminal 1 is rHJ, 12 internal input terminal 2 is rLJ
In the state of , MOS transistors 5 and 8 are on and MOS transistors 6 and 7 are off, so the level of output terminal 1 of 9 is ≧■, , the level of output terminal 2 of 10 is = Ov. Next, from this state, 11
internal input terminal 1 of rLJ12 internal input terminal 2 of rH
When the voltage is changed to J, MOS transistors 5 and 8 are turned off, and MOS transistors 6 and 7 are turned on.

In this transient state change, since the switching speed of the MOS transistor on the power supply side is slower than that of the MOS transistor on the ground terminal side, a state appears in which both the transistor on the power supply side and the transistor on the ground terminal side are on. , a through current will flow. This difference in switching speed is due to the difference in gate-to-lase voltage in each transistor, resulting in a difference in gate charging/discharging time, resulting in a difference in gate voltage waveform.

In order to prevent the through current caused by the above causes, it is sufficient to shorten the discharge time relative to the gate charge time. For this purpose, the P-channel MO8 transistor and N-channel MOS of the drive buffer of the output 777781979 circuit
This increases the relative on-resistance ratio of the transistors, and since the on-resistance of the P-channel MO8 transistor is larger than that of the N-channel MOS transistor,
This has the effect that the time for charging the gate of the MOS transistor of the output H-bridge circuit becomes longer than the discharging time. The above will be explained using drawings. FIG. 6 shows the output 7777819 of the prior art circuit of FIG. 5 and the circuit of the present invention.
It shows the difference in gate waveforms of MOS transistors in 79 circuits. The circuit of the present invention has a faster fall time and a slower rise time than the conventional circuit, so the output 7777819
It can be seen that the time τ during which both the MOS transistor on the power supply side and the MOS transistor on the ground terminal side of the 79 circuit are on is shortened. (τ2 × τ1) As described above, the through current can be reduced. This effect is further improved by increasing the VT value of the MOS transistors forming the output 777781979 circuit.

Next, a comparison will be made of the through current between the circuit of the present invention and the circuit of the prior art. FIG. 3 shows the case of a conventional circuit, and when the level of the internal input terminal is changed, a through current as shown in the figure flows, and power shown by diagonal lines is consumed.

Figure 4 shows the through current in the circuit invented by Rikiki.As the gate rise time is longer than the fall time, the through current is reduced and the power consumption is also lower than in Figure 3. becomes very small.

FIG. 2 is a circuit diagram of a second embodiment of the present invention. The operation is similar to the circuit of Example 1, but in this case the output huffer H
The MOS) run transistor that makes up the bridge circuit is DMO8.
Consists of transistors. Even when DMO8 transistors are used, the through current can be sufficiently prevented and the effect is equivalent to that of a normal MOS transistor.

〔Effect of the invention〕

As explained above, the present invention improves the through-current of the output circuit by increasing the relative on-resistance ratio of the P-channel MO3 transistor and the N-channel MOS transistor of the preceding buffer, which drive the output buffer H-fridge circuit. This reduces the amount of time that the current flows, which prevents an increase in power consumption even for input signals with long rise and fall times.It also reduces spike noise that occurs at power supply terminals and ground terminals due to through current. It has the effect of reducing

4 is a diagram showing the through current of the conventional circuit, FIG. 4 is a diagram showing the through current of the circuit of the present invention, FIG. 5 is a circuit diagram of the conventional technology, and FIG. 6 is the gate voltage waveform of the MOS transistor of the output 777781979 circuit. It is a diagram.

1...Input terminal, 2...Power terminal l,
3... Ground terminal, 4... Power terminal 2.
5...1st MOS transistor, 6...
2nd M08) Runsistor, 7...3rd M03 transistor, 8...4th M0S transistor, 9...
...Output terminal 1.10 ...Output terminal 2.1
1...Internal input terminal 1.12...Internal input terminal 2.13...Internal input terminal 3.1496.
.

Internal input terminal 4.15...CMOS inverter 1.16...CMOS inverter 2, 17...
...Control circuit.

Agent Patent Attorney Susumu Uchihara

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, and FIG. 3 is a circuit diagram showing a second embodiment of the present invention. l#1tnsノ8tFIII(yb) 1st episode

Claims (1)

[Scope of Claims] 1) A semiconductor device characterized in that an output buffer H-bridge circuit and a buffer circuit that drives the circuit are used as output circuits to reduce through current. 2) Output buffer H bridge circuit is N channel MOS
Consisting of four transistors, the drain of the first MOS transistor is connected to the power supply terminal and the source is connected to the output terminal 1, the drain of the second MOS transistor is connected to the output terminal and the source is connected to the ground terminal, and the third The drain of the MOS transistor is connected to the power supply terminal, the source is connected to the output terminal 2, the drain of the fourth MOS transistor is connected to the output terminal 2, the source is connected to the ground terminal, and the gates of the first MOS transistor and the fourth MOS transistor are connected. An output circuit in which a terminal is a common input terminal 1, a gate terminal of the second MOS transistor and a third MOS transistor is a common input terminal 2, and a load is connected between the output terminal 1 and the output terminal 2, The buffer circuit that drives the output circuit is
One P-channel MOS transistor and one N-channel MOS
Two CMOS inverters consisting of one transistor
By connecting the respective output terminals to input terminals 1 and 2 of the output buffer H-bridge circuit, and increasing the on-resistance ratio of the P-channel MOS transistor and N-channel MOS transistor of the CMOS inverter, the through-current 2. The semiconductor device according to claim 1, wherein: 3) The N-channel MOS transistor that constitutes the output buffer H-bridge circuit is a double-diffused MOS (DMOS).
2. The semiconductor device according to claim 1, wherein the semiconductor device is a transistor, and the input voltages of input terminals 1 and 2 of the output buffer H-bridge circuit are boosted to a level higher than a power supply voltage of the output buffer H-bridge circuit.