JPH1132306A - Television video system converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the generation of noise due to beat components, to unnecessitate any PLL circuit, and to reduce costs by using a clock obtained by frequency-dividing a clock to be used for a video system before conversion for the driving of a video signal after conversion. SOLUTION: A writing address reset signal 6a and a writing clock 6b are generated from a vertical synchronizing signal 5a, horizontal synchronizing signal 3a, and clock 3e in a writing signal generating circuit 6. Also, an address reset signal 8f and a reading clock 8e are generated from the vertical synchronizing signal 5a and a clock 3d obtained by three frequency-dividing the clock 3e by a clock frequency-dividing circuit 5 in a reading signal generating circuit 7. Then, a vertically band-limited video signal 11b is written in a storage circuit 8 only by one scanning line per three scanning lines according to the writing address reset signal 6a and the writing clock 6b, and read according to the reading address reset signal 8f and the reading clock 8e, and a pseudo video signal 12a is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a television video system conversion circuit, and more particularly to a television video system conversion circuit using a digital conversion system using a memory.

[0002]

2. Description of the Related Art Format conversion of a television video signal is performed by a horizontal or vertical interpolation filter and a clock rate conversion circuit. In this clock rate conversion circuit, when it is not possible to generate a clock after conversion by dividing the clock output from the clock before conversion or the oscillator generating the clock before conversion, a phase locked loop circuit (hereinafter, referred to as It is necessary to generate a clock after conversion by an oscillator. Simulate 750p 525i while preserving the number of samples in the horizontal video period
Is equivalent to this. Here, the 750p video signal means a field frequency of 60 Hz, a total number of scanning lines of 750, of which 720 are vertical video periods and horizontal scanning line periods are 165.
0 samples, of which 1280 samples are progressive scanning video signals during the horizontal video period, and the clock is 74.25 MHz
It is. The pseudo 525i video signal is a frame frequency of 30 Hz, a field frequency of 60 Hz, a total of 525 scanning lines, of which 480 are vertical video periods, horizontal scanning periods are 1545 samples, and horizontal video periods are 1280 samples. An interlaced video signal with a clock of 24.33375 MHz
z. In addition, what is expressed as pseudo 525i is that of EIA
This is because there is a slight difference in the numerical values from the NTSC system standardized by RS170A or the like.

In the conventional process of converting a 750p video signal into a pseudo 525i video signal, in the vertical direction, 720 scanning lines in the vertical video period of the 750p video signal are thinned out to 240 scanning lines in the 525i vertical video period. I do. More specifically, the processing is performed by limiting the band in the vertical direction and thinning out one scanning line to three scanning lines. In the horizontal direction, 1 to 260 and 1541 to 1650 of the horizontal 1650 samples of the 750p signal are the horizontal blanking period, 261 to 1540 are the horizontal video periods, and the number of samples in the horizontal video period is 1280 for both 750p and 525i. It is. As for the sync signal, the horizontal sync signal is 1650 samples per cycle for a 750p video signal, and is a signal of period 1 of 1 to 33 samples, period 0 of 34 to 1650 samples, and a vertical sync signal of 1500 horizontal One cycle of the scanning line period,
The signal is 1 at the fifth scanning line and 0 at the 6th to 1500th scanning lines.

[0004] First, the vertical band limitation will be described. Since the position of the scanning line of the 525i signal differs between the odd field and the even field, the phase in the vertical direction is shifted by 180 degrees every other field. Therefore, band limitation in the vertical direction requires not only band limitation but also a signal whose phase is shifted by 180 degrees from a signal whose phase in the vertical direction is not shifted every other field. This can be realized by changing the transfer function of the vertical filter every other field. Mock 52
In order to correspond to 5i, signals that are band-limited in the vertical direction with respect to the 750p signal are set as one set of signals in two fields. In this case, out of 1500 scanning lines, 1 to 25, 746 to 77
5、1496 ~ 1500 scanning lines during vertical blanking period 26 ~ 7
The scanning lines 45, 776 to 1495 constitute the vertical image period. And vertical band limiting, halving the band, 26-745
The phase of the video signal of the scanning line 776 to 1495 is not changed, and the phase of the video signal of the scanning line 776 to 1495 is shifted 180 degrees in the vertical direction.

Next, a description will be given of a process of thinning out one scanning line to three scanning lines. This includes RAM with FIFO operation
This can be realized by clock rate conversion using. In other words, the video signal of 750p, which is vertically band-limited, is stored in RAM as 1
Write in percentage of books. The clock frequency when writing is
74.25 MHz. Then, the written signal is pseudo 525i
, The vertical video period can be thinned out.

[0006] 750p
A pseudo 525i video signal is obtained from the above signal. In the pseudo 525i video signal, scanning lines 1 to 21, 262 to 284, and 525 are vertical blanking, and 22 to 261 and 285 to 524 are vertical video periods.

Next, clock conversion will be described. Mock 52
Since the clock of the 5i video signal cannot be generated by dividing the frequency of the clock of 74.25 MHz used for the 750P video signal, it is generated using a PLL circuit. Because 74,250,0
This is because 00 is not divisible by 525 and cannot be generated by frequency division. If the horizontal scanning line period is set to 1545 samples in order to make the ratio of the horizontal video period and the blanking period almost the same as NTSC, the clock frequency of the pseudo 525i is 24.33375 MHz. The clock having a frequency of 24.33375 MHz is generally generated using a crystal oscillator that can be controlled in voltage.

[0008]

In the conventional video signal format conversion circuit, in clock rate conversion, the frequency of the clock before conversion and the frequency of the clock after conversion are not an integer multiple, so that a beat component is generated and noise is generated. Affects video signal. In addition, a PLL circuit is required to generate a converted video format clock.

A video signal format conversion circuit according to the present invention generates a clock used in a video signal after conversion by dividing a clock used in a video signal before conversion, and reads the converted video signal. An object of the present invention is to enable operation using a clock obtained by frequency division, thereby suppressing generation of noise due to beat components caused by clock frequencies before and after conversion, and reducing power and cost by eliminating the need for a PLL circuit. I do.

[0010]

According to the present invention, there is provided a television image format conversion circuit comprising: means for dividing a first clock to generate a second clock; Means for generating a write signal from a clock and a synchronizing signal; means for storing a video signal in a memory according to the write signal; and different horizontal scanning line periods within one field based on the second clock and the synchronizing signal. Means for generating a read signal, and means for reading a video signal from the memory in accordance with the read signal, and a horizontal scanning line in one field of the read signal so as to obtain a converted television video signal. The period is adjusted.

With this configuration, a clock obtained by dividing the clock used in the video system before conversion can be used for driving the video signal after conversion, and a PLL circuit is not required.

Further, the horizontal scanning line period of the read signal is set to have different lengths in the vertical blanking period and the vertical video period.

Further, the horizontal scanning line period of the read signal is gradually increased and decreased in the vertical blanking period.

With this configuration, the television image format can be converted without affecting the image displayed on the screen. Further, if the horizontal scanning line period gradually increases and decreases during the vertical blanking period, it is possible to reduce the disturbance of the image in the horizontal direction due to the unevenness of the horizontal scanning line period.

Next, the horizontal scanning line period of the read signal is set to the same length in the scanning lines near the end of the vertical blanking period and in the scanning lines in the vertical video period.

Further, the horizontal scanning line period of the readout signal has different lengths in the scanning lines near the end of the vertical video period, and the horizontal scanning line period of the scanning lines near the end of the vertical video period and the scanning line in the vertical blanking period And the same horizontal scanning line period.

[0017] With this configuration, it is possible to suppress the disturbance of the image generated at the upper part of the screen due to the difference in the horizontal synchronization.

Further, the horizontal scanning line period of the read signal has different lengths in the scanning lines near the start of the vertical video period, and the scanning lines in the horizontal scanning line period and the vertical blanking period of the scanning lines near the start of the vertical video period. And the same horizontal scanning line period.

With this configuration, it is possible to convert a television video system in correspondence with a monitor having a narrow horizontal synchronization range.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Embodiment 1 is a television video format conversion circuit that performs thinning-out processing and clock rate conversion when converting a 750p video signal into a pseudo 525i video signal while preserving the number of samples in a horizontal video period. . 750p and pseudo
The 525i video signal has been described in the related art, and a description thereof will be omitted. The horizontal synchronization signal and the vertical synchronization signal are the same as those described in the related art.

FIG. 1 is a configuration diagram of a television image format conversion circuit. In FIG. 1, reference numeral 1 denotes an input terminal to which a vertical synchronizing signal 5a is input, 2 denotes an input terminal to which a horizontal synchronizing signal 3a is input, and 3 denotes an input terminal to which a clock 3e of 74.25 MHz used in 750p is input. Is 750p band-limited in the vertical direction
5 is a clock divider circuit, 6 is a write signal generation circuit, 7 is a read signal generation circuit, 8 is a storage circuit for storing the video signal 11b, and 9 is a pseudo 525i video signal. An output terminal 12a is output.

First, the configurations and operations of the clock frequency dividing circuit 5, the write signal generating circuit 6, the read signal generating circuit 7, and the storage circuit 8 will be described, and finally, the operation of the television video format conversion circuit will be described.

The configuration and operation of the clock frequency dividing circuit 5 will be described. FIG. 2 is a configuration diagram of the clock frequency dividing circuit 5, and FIG. 3 is a timing chart of the clock frequency dividing circuit 5. FIG.
, 201 is an input terminal to which the horizontal synchronization signal 3a is input, 202 is an input terminal to which a clock 3e of 74.25 MHz is input, 203 is a reset signal extraction circuit, 204 is a ternary counter,
205 is an output terminal from which a 24.75 MHz clock is output.

A horizontal synchronizing signal 3a is input from an input terminal 201, and a 74.25 MHz clock 3e is input from an input signal 202. The reset signal extracting circuit 203 outputs a reset signal 3b which becomes 1 only for one clock when the horizontal synchronizing signal 3a rises. More specifically, a reset signal 3b is obtained by ANDing the horizontal synchronization signal 3a with the inverted signal of the horizontal synchronization signal 3a delayed by one clock by a D flip-flop clocked by a clock 3e of 74.25 MHz. . Then, the ternary counter 204 is synchronously reset to 0 at the next clock after the reset signal 3b becomes 1, and thereafter becomes 74.25 MHz.
Each time the clock 3e of z rises, the counter value increases by 1 and returns to 0 at the next clock which becomes 2, and 0, 1,.
The operation as a 2, 0, 1, 2 and ternary counter is repeated. The upper bits of the ternary counter 204 are 3d in FIG. 3, and the lower bits are 3c in FIG. 3c and 3d are both 7
The period is three times as long as the 4.25 MHz clock 3e. That is, it is a signal obtained by dividing the frequency of the 74.25 MHz clock by three.
Therefore, either signal may be used as the output signal of the clock frequency dividing circuit 5, but here, 3d is output from the output terminal 205 as a 24.75 MHz clock. Further, since the number of horizontal pixels is 1650 and 1650 is divisible by 3, the ternary counter 204 repeats counting to 0, 1, and 2 without any shift after the initial reset is performed once.

The horizontal synchronizing signal 3a is reset to the reset signal 3b.
However, the reset signal 3b may be extracted by detecting the rise of the power supply. Further, if the initial value of the flip-flop used for the counter is determined, the reset may be omitted.

Next, the configuration and operation of the write signal generation circuit 6 will be described. FIG. 4 is a configuration diagram of the write signal generation circuit 6, and FIGS. 5 and 6 are timing charts of the write signal generation circuit 6. In FIG. 4, reference numeral 401 denotes a vertical synchronization signal 5a.
Is an input terminal to which the horizontal synchronization signal 3a is input, 403 is an input terminal to which a clock of 74.25 MHz is input, 404 and 405 are reset signal extraction circuits, and 406 is an input terminal.
A decimal counter, 407 is a synthesis circuit, 408 is an output terminal for outputting a write address reset signal, and 409 is an output terminal for outputting a write clock. Reset signal extraction circuit 40
4 and 405 have the same configuration as the reset signal extraction circuit 203 in FIG. 2, and the ternary counter 406 has the same configuration as the ternary counter 204 in FIG.

The reset signal extraction circuit 404 has an input terminal 402
When the vertical synchronizing signal 5a input from the input terminal 401 rises, the reset signal 5b which becomes 1 for one clock is output using the horizontal synchronizing signal 3a input from the clock as a clock. At the next clock after the reset signal 5b becomes 1, the ternary counter 406 is synchronously reset to 0, and thereafter, the operation as a ternary counter is repeated, and the ternary count is repeated every horizontal cycle. The upper bit of the ternary counter 406 is 5d in FIG. 5 and the lower bit is 5c in FIG. 5, and the signal 5d is input to the reset extraction circuit 405 and the synthesis circuit 407. The reset signal extraction circuit 405 uses the clock 3e of 74.25 MHz input from the input terminal 403 as a clock, and the write address reset signal which becomes 1 only for one clock when the upper bit signal 5d of the ternary counter 406 rises.
Output 6a. In the synthesis circuit 407, the clock 3 of 74.25 MHz is used.
The logical product of the inversion of e and the higher-order bit signal 5d of the ternary counter 406 is taken and output from the output terminal 409 as a write clock 6b. The write clock 6b is a clock of 74.25 MHz only for one scan line out of three scan lines, and the remaining 2
The period of the scanning line remains at 0. That is, the write signal generation circuit 6 repeats the rise and fall of 1650 clocks at a clock rate of 74.25 MHz for a period of 1650 clocks corresponding to one scanning period after reset, and outputs a clock of 74.25 MHz. 33 corresponding to the scanning line period
During the period of 00 clocks, the output remains at 0, and an operation of not outputting a clock is performed.

Next, the configuration and operation of the read signal generation circuit 7 will be described. FIG. 7 is a configuration diagram of the read signal generation circuit 7,
8 and 9 are timing charts of the read signal generation circuit 7. 701 is an input terminal to which the vertical synchronizing signal 5a is input, and 702 is frequency-divided by the clock frequency dividing circuit 5.
An input terminal to which a 75 MHz clock 3d is input, 703 is a constant circuit that stores a constant of 1570, 704 is a constant circuit that stores a constant of 1575, 705 is a constant circuit that stores a constant of 256, and 706 is a constant circuit that stores a constant of 21. Constant circuit to store, 707 is 26
A constant circuit for storing a constant of 1; 708, a constant circuit for storing a constant of 284; 709, a constant circuit for storing a constant of 524; 710, a selection circuit for selecting one of two signals; A reset signal extracting circuit for extracting a reset signal from a signal, 712 is a horizontal counter, 713 is a vertical counter, 714 is an inverting circuit, 715 is a comparing circuit for comparing whether two signals are equal, 716 to 719 are two signals. Comparison circuit for comparing magnitude, 720 is a synthesis circuit that performs logical operation, 7
21 is an output terminal from which the read address reset signal 8e is output, and 722 is an output terminal from which the read clock 8f is output. Note that the reset signal extraction circuit 711 has the same configuration as the reset signal extraction circuit 204 in FIG. 2, and thus a detailed description of the operation is omitted.

The selection circuit 710 outputs a value of 1570 output from the constant circuit 703 when the vertical blanking signal 9e output from the synthesis circuit 720 is 0, and outputs a constant value when the vertical blanking signal 9e is 1 The value of 1575 output from the circuit 704 is output, and the horizontal counter 71 is output as the horizontal period signal 9f.
Enter 2 The reset signal extraction circuit 711 is connected to the input terminal 70
Using the 24.75 MHz clock 3d input from 2 as a clock, a vertical reset signal 8a that becomes 1 for one clock when the vertical synchronization signal 5a input from the input terminal 701 rises is output. At the next clock after the vertical reset signal 8a becomes 1, the horizontal counter 712 and the vertical counter 713 are reset to 0. The reset horizontal counter 712 is 2
It increases by 1 each time 4.75MHz clock 3d rises,
When it becomes equal to the value of the horizontal period signal 9f output from the selection circuit 710, it is reset by the next clock. The horizontal counter 712 sets the horizontal carry signal 8c to 1 only when the value of the counter becomes equal to the horizontal period signal 9f. The comparison circuit 715 compares the signal 8b of the horizontal counter with a constant of 256 output from the constant circuit 705, outputs a read address reset signal 8e which becomes 1 only when the values become equal, and outputs a read address reset signal 8e Are output from the output terminal 721. Although the value of the constant circuit 705 is 256,
It is sufficient that the read address of the RAM of the storage circuit 8 is a value that cannot be overtaken by the write address.
Since there are other than 6, there can be a value other than 256.

The horizontal counter 712 and the vertical counter 713 are 2
Operates using 4.75 MHz clock 3d as a clock. After the vertical counter 713 becomes 0 by the vertical reset signal 8a, the value is maintained at 0 until the horizontal carry signal 8c becomes 1, and when the horizontal carry signal 8c becomes 1, the counter is reset by the next clock. The value increases by 1 to become 1. Thereafter, similarly, when the horizontal carry signal 8c is input, the operation of increasing the counter value by 1 at the next clock is repeated, and the vertical reset signal 8a becomes 1 and the counter value increases until it is reset. to continue. Vertical counter signal 8d
Are input to the comparison circuits 716 to 719. The comparison circuit 716 compares the value with the value 21 obtained from the constant circuit 706, and outputs a comparison signal 9a that is 1 if the value is less than 21 and 0 if the value is 21 or more. The comparison circuit 717 compares the value 261 obtained from the constant circuit 707, and outputs a comparison signal 9b that is 0 when the value is less than 261 and 1 when the value is 261 or more. The comparison circuit 718 compares the value 284 output from the constant circuit 708 with 1 when the value is less than 284,
In the above case, the comparison signal 9c which becomes 0 is output. The comparison circuit 719 compares the value 524 output from the constant circuit 709, and outputs a comparison signal 9d that is 0 when the value is less than 524 and 1 when the value is 524 or more. The comparison signals 9a to 9d output from the comparison circuits 716 to 719 are input to the synthesis circuit 620. The synthesis circuit 620 calculates the logical product of the comparison signal 9b and the comparison signal 9c, and outputs a vertical blanking signal 9e obtained by calculating the logical sum of the logical product of the comparison signal 9a and the comparison signal 9d. Vertical blanking signal 9e
Is an output signal of the synthesizing circuit 720, and is a signal which becomes 1 when the value of the vertical counter is 0 to 20, 261 to 283, 524.
The vertical blanking signal 9e is used as a selection control signal of the selection circuit 710.

With the above operation, the read signal generation circuit 7
Is a vertical blanking period of 1 to 21, 262 to 284, and a total of 45 scan lines of number 525 for the 525 scan lines of the pseudo 525i video signal, the horizontal cycle is 1576 samples, Vertical video period 22-261, 285-524 No. total 480
The scanning line outputs a read address reset signal 8e having a horizontal cycle of 1571 samples. The 24.75 MHz clock input from the input terminal 702 is inverted by the inversion circuit 714.
And output from the output terminal 722 as a read clock.

Next, the configuration and operation of the storage circuit 8 will be described.
FIG. 10 is a configuration diagram of the storage circuit 8, FIG. 11 is a timing chart at the time of writing, and FIG. 12 is a timing chart at the time of reading. The storage circuit 8 basically operates as a FIFO RAM. In FIG. 10, 1001 is an input terminal to which a write address reset signal 6a is input, 1002 is an input terminal to which a write clock 6b is input, and 1003 is an input terminal to which a 750p video signal 11b whose band is vertically limited is input. , 100
4 is an input terminal to which a read clock 8f is input, 1005 is an input terminal to which a read address reset signal 8e is input, 1006 is a counter for generating a RAM write address, 1007 is a counter for generating a RAM read address, and 1008 is a counter for generating a RAM read address. Synchronous dual port RAM that can control writing and reading separately, 1009 is a pseudo 525i video signal
An output terminal 12b is output.

First, the writing operation will be described. At the same time as the write address reset signal 6a becomes 1, the write clock 6b, which has been 0 so far, is input as a signal having a frequency of 74.25 MHz. The write clock 6b is a signal having a value of 1 for 1650 clock periods after reset and a value of 0 for the next 3300 clock periods as described in the description of the operation of the write signal generation circuit 6. This reset signal is 1
Then, when the write clock 6b rises, the write address counter 1006 is reset to 0 at the next clock. Then, each time the write clock 6b rises, the value increases by one, and this counter value is output as the write address 11a. And dual port R
The AM 1008 writes the 750p video signal 11b to the address specified by the write address 11a. The write clock 6b is a clock of a frequency of 74.25 MHz for only 1650 clocks, and thereafter, 33 clocks at a clock rate of 74.25 MHz.
It remains at 0 during the 00 clock period. Therefore, if the address
Up to 1648, that is, 1649 signals are written, and the address stops at 1649. In FIG. 11, a value of 17 is written to address 0, a value of 16 is written to address 1, and thereafter, a value of the video signal 11b corresponding to the address is similarly written. Then, the value 11b of the write counter is 164
When it reaches 9, the write clock 6b becomes 0 for the next 3300 clock periods, and there is no clock input to the write address counter 1006, so that the write operation stops. When the signal rises for the first time after the next write address reset signal 6a becomes 1, a signal is written to the address 1649. However, when reading,
Since only the address up to the 1575th address is accessed, 16
The value written to the 49 address can be any value.

Next, the read operation will be described. Input terminal
From 1004, the read clock 8f is always input at a frequency of 24.75 MHz. The read address reset signal 8e becomes 1 and the next time the clock 8f rises next, the read address counter is reset and becomes 0, and the value increases by one every time the read clock 8f rises. Then, the value is reset when the read address reset signal 8e becomes 1 next, so that the value of the read address counter 1007 increases to 1570 in the vertical video period and to 1575 in the vertical blanking period, and becomes the read address counter 1007 as the read address 12a. Output from A signal is read from the dual port RAM 1009 according to the read address 12a. The read address reset signal 8e is
Since the period is 1571 samples during the vertical video period and 1576 samples during the vertical blanking period, dual port RAM
The video signal read from 1009 has 24.75 MHz, a frame frequency of 30 Hz, and 525 scanning lines per frame.
The vertical video period consisting of one horizontal scanning period has 1571 samples, and the vertical blanking period consisting of 45 horizontal scanning periods has 1576 samples and is a pseudo 525i signal.

The operation of the clock rate conversion circuit will be described based on the description of the configuration and operation of the clock frequency dividing circuit 5, write signal generation circuit 6, read signal generation circuit 7, and storage circuit 8 described above.

The write signal generation circuit 6 generates a write address reset signal 6a and a write clock 6b from the vertical synchronizing signal 5a, the horizontal synchronizing signal 3a, and the clock 3e of 74.25 MHz. In the read signal generation circuit 7, the vertical synchronization signal 5a
Then, the read address reset signal 8f and the read clock 8e are generated using the clock 3d of 24.75 MHz obtained by dividing the clock 3e of 74.25 MHz by 3 by the clock frequency dividing circuit 5. And the 750p video signal 11b whose band is limited in the vertical direction is
Write address reset signal 6a and write clock 6b
Thus, only one scanning line is written to the storage circuit 8 for every three scanning lines. Then, the read signal is read from the storage circuit 8 in accordance with the read address reset signal 8f and the read clock 8e, and a pseudo 525i video signal 12a is obtained and output from the output terminal 9. The pseudo 525i video signal 12a has a clock rate of 24.75 MHz, a horizontal period of 1576 samples in the vertical blanking period, and a horizontal period of 15
71 samples.

By the above operation, the 750p video signal (clock rate 74.25 MHz) whose band is limited in the vertical direction is
It can be converted to a 525i video signal (clock rate 24.75 MHz).

(Embodiment 2) Embodiment 2 is a television video format converter for performing thinning-out processing and clock rate conversion when converting a 750p video signal into a pseudo 525i video signal while preserving the number of samples in a horizontal video period. Circuit.

The overall circuit configuration and input signals of the television image format conversion circuit of the second embodiment are the same as those of the first embodiment shown in FIG. The configuration is different. The circuit configuration and signals other than the read signal generation circuit 7 are the same as those described in the first embodiment, and thus description thereof will be omitted, and the second embodiment will be described below focusing on the configuration and operation of the read signal generation circuit 7. Will be described.

FIG. 13 is a configuration diagram of the read signal generation circuit 7,
FIG. 14 is a diagram showing a relationship between signals of an address decoder 1301 and a constant storage circuit 1302 which is a RAM. The configuration of the read circuit 7 in the second embodiment uses an address decoder 1301 and a constant storage circuit 1302 instead of the constant circuit 703 of the read signal generation circuit 7 in the first embodiment shown in FIG. The rest of the circuit configuration and signals are the same as those of the read signal generation circuit 7 of the first embodiment shown in FIG. 7, and therefore description thereof is omitted here. The operation of the address decoder 1301 and the constant storage circuit 1302 will be mainly described.

In the vertical blanking period, the address decoder 1301 decodes the signal 8d of the vertical counter to obtain the signal 13a shown in FIG. 14, and the signal 13a is given to the RAM which is the constant storage circuit 1302, Signal 13b is output. In the vertical blanking period, that is, when the vertical blanking signal 9e output from the synthesizing circuit 720 is 1, the output signal 13b is selected by the selection circuit 710 and input to the horizontal counter 712 as a signal 9f indicating a horizontal cycle. . Accordingly, the horizontal counter 712 operates in the period of the signal 13b shown in FIG. 14 during the vertical blanking period. Therefore, the read address reset signal 8e output from the output terminal 721 is a signal composed of 1571 samples in the vertical video period and one sample larger than the counter setting value shown in FIG. 14 in the vertical blanking period.
Since the read operation in the storage circuit 8 is performed in accordance with the read address reset signal, the vertical video period consists of 1571 samples, and the vertical blanking period consists of one more sample than the counter set value shown in FIG. A pseudo 525i video signal 12a is obtained. This pseudo 5
When the 25i video signal 12a is D / A-converted and output to the monitor, the horizontal cycle gradually changes during the vertical blanking period, so that the synchronization disturbance when the response of the horizontal synchronization adjustment circuit in the monitor is fast is suppressed. It is possible to suppress the disturbance of the image on the upper part of the screen due to the influence of the disturbance of the synchronization during the vertical blanking period.

(Embodiment 3) Embodiment 3 is a television picture format conversion for thinning-out processing and clock rate conversion when converting a 750p picture signal into a pseudo 525i picture signal while preserving the number of samples in the horizontal picture period. In this circuit, the cycle of the last two scanning lines in vertical blanking is the same as the cycle of the scanning lines in the vertical video period. The overall circuit configuration and input signals are the same as those of the first and second embodiments shown in FIG. 1, but the configuration of the read signal generation circuit 7 is different. The circuit configuration and signals other than the read signal generation circuit 7 are the same as those described in the first embodiment, and a description thereof will not be repeated. The circuit configuration of the read signal generation circuit 7 is the same as that of the second embodiment shown in FIG.
01, the output of the constant storage circuit 1302 is as shown in FIG.

As shown in FIG. 15, the period of the last two scanning lines in the vertical blanking period is the same as the period of the vertical video period. Therefore, the horizontal counter 712 performs the counter operation in the period of the signal 13b shown in FIG. 15 during the vertical blanking period. Therefore, the read address reset signal 8e output from the output terminal 721 is a signal having 1571 samples in the vertical video period and one sample number larger than the counter setting value shown in FIG. 15 in the vertical blanking period. Since the read operation in the storage circuit 8 is performed according to the read address reset signal, the vertical video period includes 1571 samples, and the vertical blanking period includes one more than the counter set value shown in FIG. A pseudo 525i video signal 12a is obtained. When the pseudo 525i video signal 12a is DA-converted and output to the monitor, it occurs during the vertical blanking period because the cycle of the last two scanning lines in vertical blanking is the same as the scanning line cycle in the vertical video period. The disturbance of the synchronization of the horizontal synchronization adjustment circuit in the monitor is less likely to appear as the disturbance of the video at the top of the screen.

(Embodiment 4) In Embodiment 4, as in Embodiment 3, thinning-out processing and clock rate conversion when converting a 750p video signal into a pseudo 525i video signal while preserving the number of samples in the horizontal video period are performed. This is a circuit for converting the last two scanning lines of vertical blanking to be the same as the period of the scanning lines in the vertical video period.

The input signal and the overall circuit configuration are as shown in FIG. 1 and are the same as in the first embodiment, but the configuration of the read signal generation circuit 7 is different. The circuit configuration and signals other than the read signal generation circuit 7 are the same as those of the first embodiment.
The description here is omitted because it is the same as that described above. The circuit configuration of the read signal generation circuit 7 is the same as that of the first embodiment shown in FIG.
The values of the constants 6 to 709 are different from those of the first embodiment.

In FIG. 7, the constant circuit 706 has a constant of 19, the constant circuit 707 has a constant of 259, and the constant circuit 708 has a constant of 2
The constant circuit 709 stores the constant of 82 and the constant of 522. In this case, the phase of the vertical blanking signal 9e output from the synthesizing circuit 720 is two times greater than that described in the first embodiment.
Only the scanning lines become faster. Then 1-19, 260-282, 523
For the 525525th scanning line, the horizontal period is 1576 samples, and for the 20th to 259th and 283〜522th scanning lines, it is 1571 samples, which is similar to that of the third embodiment with a simple circuit configuration compared to the third embodiment. The effect of can be obtained. However, this is effective when the response of the automatic adjustment circuit of the horizontal synchronization of the monitor is slow, and even if the horizontal cycle of the last two scanning lines in the vertical video period is changed, the video is not affected.

(Embodiment 5) In Embodiment 5, as in Embodiment 1, thinning-out processing and clock rate conversion when converting a 750p video signal into a pseudo 525i video signal while preserving the number of samples in the horizontal video period are performed. This is a television video format conversion circuit to be performed.

The input signal and the overall circuit configuration are as shown in FIG. 1 and are the same as in the first embodiment, but the configuration of the read signal generation circuit 7 is different. The circuit configuration and signals other than the read signal generation circuit 7 are the same as those of the first embodiment.
The description here is omitted because it is the same as that described above. The circuit configuration of the read signal generation circuit 7 is the same as that of the first embodiment shown in FIG.
The values of the constants 6 to 709 are different from those of the first embodiment.

In FIG. 7, the constant circuit 704 has a constant of 1573, the constant circuit 706 has a constant of 31, and the constant circuit 707 has
The constant circuit 708 stores a constant of 294, and the constant circuit 709 stores a constant of 519. In this case, the read address reset signal 8 output from the comparison circuit 715
For e, the horizontal period is 1574 samples for the 1st to 31st, 258 to 294, and 520 to 525th scanning lines, and 1571 samples for the 32 to 257th and 295 to 519th scanning lines. The pseudo 525i video signal 12a by this conversion circuit can be used when the upper and lower images of the screen are reduced in the horizontal direction, so that distortion at the edge of the screen does not matter. However, 2 existing in one field
There is an advantage that the difference between the types of horizontal periods is small, and this is effective for a monitor in which the fluctuation range of the frequency of horizontal synchronization is narrow.

[0050]

According to the television video system conversion circuit of the present invention, a clock obtained by dividing a clock used in a video system before conversion can be used for driving a video signal after conversion, and a PLL circuit is not required. .

By limiting the horizontal scanning line period to two types, the circuit configuration for generating the converted synchronization signal is simplified. Furthermore, it is possible to suppress the disturbance of the image generated at the upper part of the screen, and it is possible to cope with a monitor having a narrow horizontal synchronization range.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a television video format conversion circuit of the present invention.

FIG. 2 is a diagram showing a configuration example of a clock frequency dividing circuit of FIG. 1;

FIG. 3 is a diagram showing signal waveforms of the clock divider circuit of FIG. 2;

FIG. 4 is a diagram illustrating a configuration example of a write signal generation circuit in FIG. 1;

FIG. 5 is a diagram showing signal waveforms of a counter operation of the write signal generation circuit of FIG. 4;

FIG. 6 is a diagram showing a waveform of an output signal of the write signal generation circuit of FIG. 4;

7 is a diagram illustrating a configuration example of a read signal generation circuit in FIG. 1;

FIG. 8 is a diagram showing signal waveforms in units of one sample of the read signal generation circuit of FIG. 7;

9 is a diagram showing signal waveforms in units of a horizontal scanning period of the readout signal generation circuit in FIG. 7;

10 illustrates a configuration example of a storage circuit in FIG.

11 is a diagram showing signal waveforms related to a write operation of the memory circuit in FIG.

12 is a diagram showing signal waveforms related to a read operation of the memory circuit in FIG.

13 is a diagram illustrating a configuration example of a read signal generation circuit in FIG. 1;

14 is a diagram showing the correspondence between the scanning lines near the vertical blanking period, the values of the address decoder, and the horizontal scanning line period in the read signal generation circuit in FIG. 13;

FIG. 15 is a diagram showing the correspondence between the scanning lines near the vertical blanking period, the values of the address decoder, and the horizontal scanning line period in the read signal generation circuit of FIG. 13;

[Description of Signs] 1,401,701 Vertical synchronization signal input terminal 2,201,402 Horizontal synchronization signal input terminal 3,202,403,702,1002,1004 Clock input terminal 4,1003 Video signal input terminal 5 Clock division Circuit 6 Write signal generation circuit 7 Read signal generation circuit 8 Storage circuit 9, 1009 Video signal output terminal 203, 404, 405, 711 Reset signal extraction circuit 204, 406 Binary counter 205, 409, 722 Clock output terminal 407, 720 Synthesis Circuit 408 Write address reset signal output terminal 703 to 709 Constant circuit 710 Selection circuit 712 Horizontal counter 713 Vertical counter 714 Inversion circuit 715 to 719 Comparison circuit 721 Read address reset signal output terminal 1001 Write address reset DOO signal input terminal 1005 read address reset signal input terminal 1006 RAM write address generating counter 1007 RAM read address generating counter 1008 dual port RAM

Claims (6)

[Claims] 1. A means for dividing a first clock to generate a second clock, a means for generating a write signal from the first clock and a synchronization signal, and a means for storing a video signal in a memory by the write signal. Means for storing, means for generating a read signal having a different horizontal scanning line period in one field based on the second clock and the synchronizing signal, and reading of a video signal from the memory according to the read signal Means for adjusting a horizontal scanning line period in one field of the readout signal so as to obtain a converted television image signal. 2. A horizontal scanning line period of the read signal,
2. The television video system conversion circuit according to claim 1, wherein the scanning lines in the vertical blanking period and the scanning lines in the vertical video period have different lengths. 3. A horizontal scanning line period of the read signal,
2. The television picture format conversion circuit according to claim 1, wherein the conversion is performed gradually during the vertical blanking period. 4. A horizontal scanning line period of the read signal,
2. The television video format conversion circuit according to claim 1, wherein the scanning line near the end of the vertical blanking period and the scanning line in the vertical video period have the same length. 5. A horizontal scanning line period of the read signal,
2. The television image format conversion circuit according to claim 1, wherein the number increases / decreases in a scanning line near the end of the vertical image period. 6. A horizontal scanning line period of the read signal,
2. The television image format conversion circuit according to claim 1, wherein the number increases / decreases in a scanning line near the start of the vertical image period.