JPH11312733A - Manufacturing method of integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce capacitance between wirings by interposing either an adequate gap or an insulating film of high conductivity between the wirings. SOLUTION: This manufacturing method of integrated circuit device is provided with the four steps mentioned comprising a first step of forming a plurality of wirings 3 separated from one another via the first insulating film 2 on a semiconductor substrate 1, a second step of forming a second insulating film 4 positioned between the wirings 3 at positions lower than the highest positions of the second insulating film 4 above the wirings 3 to form a semiconductor base substance, a third step for overlapping the flat-shaped member forming a third insulating film 5 on a supporting film made of an organic or inorganic materiel on the semiconductor base substance so as to make adherence to the second insulating film 4, as well as a fourth step of removing the supporting film of the flat-shaped member.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an integrated circuit device, and more particularly to a method for manufacturing an integrated circuit device in which a gap is formed between wirings in order to reduce the capacitance between the wirings.

[0002]

2. Description of the Related Art Conventionally, in an integrated circuit device, Si
By providing an insulating film containing O ₂ as a main component, a short circuit between wirings has been prevented. Meanwhile, in order to operate the integrated circuit devices at high speed, it is necessary to use the insulating material having a low dielectric constant film, but an insulating film composed mainly of SiO _2, a small film of sufficient dielectric constant I can't get it. For example, the non-dielectric constant of a film using SiOF is 3 to 4,
For a film formed by the OG (spin on glass) method, the thickness is 2.5 to 4. Depending on process conditions, a hollow gap may be formed by an insulating film formed between narrow wirings. In this case, the relative dielectric constant is almost 1, and an ideal relative dielectric constant must be used. Can be.

The air isolation, which has been conventionally used, is a method of forming a gap between wirings by adjusting the process conditions as described above, and is not sufficiently controlled. Only about 1/4 of the volume of the region formed between the wiring and the wiring is used as the air isolation portion.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and includes a plurality of wirings formed on a semiconductor substrate at a distance from each other via a first insulating film. Forming a second insulating film on the semiconductor substrate such that the highest portion of the second insulating film located between the wirings is located at a position lower than the second insulating film above the wirings; After a flat member in which a third insulating film is formed on a supporting film made of an organic material or an inorganic material is stacked on the semiconductor substrate so that the third insulating film is in close contact with the second insulating film, It is an object of the present invention to provide a method of manufacturing an integrated circuit device in which a sufficient gap is formed between wirings by removing a supporting film of a member, thereby reducing the capacitance between the wirings.

Further, according to the present invention, a plurality of wirings are formed on a semiconductor substrate at a distance from each other with a first insulating film interposed therebetween, and a second insulating film is formed on the semiconductor substrate including the wirings between the wirings. A semiconductor substrate is formed by forming the highest position of the second insulating film located at a position lower than the second insulating film above the wiring, and forming the third insulating film on the support film made of an inorganic material. After the formed flat member subjected to the annealing treatment is overlaid on the semiconductor substrate so that the third insulating film is in close contact with the second insulating film, the supporting film of the flat member is removed, whereby the distance between the wirings is reduced. It is an object of the present invention to provide a method of manufacturing an integrated circuit device in which a sufficient gap is formed, thereby reducing the capacitance between wirings.

Further, according to the present invention, a plurality of wirings are formed on a semiconductor substrate so as to be separated from each other via a first insulating film, and a second insulating film is formed on a support film made of an organic material or an inorganic material. After the flat member is overlaid on the semiconductor substrate such that the second insulating film is in close contact with the wiring, a sufficient gap is formed between the wirings by removing the support film of the flat member, thereby forming a gap between the wirings. It is an object of the present invention to provide a method of manufacturing an integrated circuit device capable of reducing capacitance.

[0007]

According to a first aspect of the present invention, a plurality of wirings are formed on a semiconductor substrate at a distance from each other via a first insulating film, and a plurality of wirings are formed on the semiconductor substrate including the wirings. Forming an insulating film such that the highest portion of the second insulating film located between the wirings is lower than the second insulating film above the wirings, thereby forming a semiconductor substrate; Or a step of stacking a flat member in which a third insulating film is formed on a supporting film made of an inorganic material on the semiconductor substrate such that the third insulating film is in close contact with the second insulating film; Removing the support film of the member.

According to a second aspect of the present invention, there is provided a step of forming a plurality of wirings on a semiconductor substrate at a distance from each other via a first insulating film, and forming a second insulating film on the semiconductor substrate including the wirings.
Forming a second insulating film located between the wirings such that the highest portion of the second insulating film is lower than the second insulating film above the wirings, forming a semiconductor substrate; Stacking a flat member, which has been subjected to an annealing treatment after forming the third insulating film, on the semiconductor substrate so that the third insulating film is in close contact with the third insulating film; And a step of removing the film.

According to a third aspect of the present invention, there is provided a process for forming a plurality of wirings on a semiconductor substrate so as to be separated from each other via a first insulating film, and forming a second insulating film on a supporting film made of an organic material or an inorganic material. Forming a flat member on the semiconductor substrate such that the second insulating film is in close contact with the wiring,
Removing the support film of the flat member.

In the present invention, the thickness of the support film is preferably 10
It is desirable that it is not more than μm. This is because if the thickness of the support film exceeds 10 μm, it takes time to remove the support film.

In the present invention, the inorganic material of the support film is preferably a metal. The reason for this is that, after the flat member is overlaid on the semiconductor substrate, a heat treatment can be performed to obtain an adhesion.

In the present invention, it is preferable that the wiring has an electric circuit arranged inside a ring of a closed dummy wiring which is held at a constant potential. At the end of the semiconductor substrate, it is desirable to form a hollow portion by providing a dummy wiring outside the wiring at the edge. Since the dummy wiring has a closed shape, the reliability of the semiconductor substrate can be improved.

[0013]

FIG. 1 is a sectional view of an integrated circuit device according to the present invention.

Reference numeral 1 in the figure denotes a semiconductor substrate, on which a plurality of metal wirings 3 are formed via a first interlayer insulating film 2 so as to be separated from each other. On the interlayer insulating film 2 including the wiring 3, a thin second interlayer insulating film 4 is formed. Here, the highest part of the interlayer insulating film 4 located between the wirings 3 is formed so as to be lower than the interlayer insulating film 4 above the wiring 3. The second interlayer insulating film 4
An insulating film 5 made of an inorganic material or an organic material is formed thereon. An air isolation (gap) 6 is formed between the wirings 3 by the second interlayer insulating film 4 and the insulating film 5.

As described above, in the present invention, the second interlayer insulating film 4 is provided on the first interlayer insulating film 2 including the wiring 3 as shown in FIG. is there. However, the second interlayer insulating film is not always necessary and can be omitted in some cases. For this reason, the ratio of the volume of the hollow portion in the region formed between the horizontally adjacent wiring can be reduced to about 1/2 to 1, which is larger than that of the conventional method.
The parasitic capacitance between wirings is greatly reduced.

In the present invention, it is desirable to arrange the wiring intervals evenly. However, it is not necessary to completely align the wiring intervals. The maximum value is set, and if it does not exceed the maximum value, the hollow portion can be maintained. Further, at the end of the semiconductor chip, it is desirable to form a hollow portion by providing a dummy wiring outside the wiring at the adjacent end.
Since the dummy wiring has a closed shape, the reliability of the semiconductor chip can be increased.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) Referring to FIG. 2 and FIG. First, the flat member 11 is formed. This flat member 11
A polyethylene film (or polystyrene film) 12 having a thickness of 5 μm as a support film and a SiO ₂ film as a third insulating film
A film (cap film) 13 is formed by sputtering or coating. On the other hand, a semiconductor substrate 15 was formed using a Si substrate (semiconductor substrate) 14. That is, a first interlayer insulating film (BP) as a first insulating film having a thickness of 1 μm is formed on the Si substrate 14.
After a plurality of metal wirings 17 are formed apart from each other via an SG film 16, a thin (10 μm or less) second insulating film as a second insulating film is formed on the interlayer insulating film 16 including the wirings 17. The semiconductor substrate 15 was formed by forming an interlayer insulating film (plasma TEOS film) 18 (see FIG. 2). In the case where a passivation film is further deposited, the interlayer insulating film 18 is not necessary. The size of the wiring 17 is 0.
The width is 6 μm, the width is 0.5 μm, and the wiring interval is 0.6 μm.
Further, the highest part of the interlayer insulating film 18 located between the wirings 17 is formed to be lower than the interlayer insulating film 18 above the wiring 17.

Subsequently, the flat member 11 was overlaid on the semiconductor substrate 15 so that the cap film 13 was in close contact with the second interlayer insulating film 18 of the semiconductor substrate 15 (see FIG. 3). At this time, the cap film 13 and the second interlayer insulating film 18 were brought into close contact in a reduced pressure atmosphere. The atmosphere for the close contact is preferably helium. This adhesion is due to intermolecular forces,
At this stage, the adhesion is not yet sufficient. Next, the support film 12 is removed by ashing in oxygen plasma,
By annealing in a nitrogen atmosphere at 30 ° C. for 30 minutes, an isolation (gap) 19 composed of the second interlayer insulating film 18 and the cap film 13 adhered to the second interlayer insulating film 18 was formed, and an integrated circuit device was manufactured (see FIG. 4). . After that, although not shown, a plasma TEOS film is formed, and a wiring layer is further formed thereon.

According to the above embodiment, the flat member 11 in which the cap film 13 is formed on the support film 12 is formed on the second interlayer insulating film 18 which is unevenly formed by the plurality of wirings 17.
Are overlapped in a He atmosphere so as to be in close contact with the second interlayer insulating film 18, the support film 12 is removed, and then annealing is performed, so that the second interlayer insulating film 18 and the cap film adhered thereto are adhered.
Since the gap 19 formed with the wiring 13 is formed, a sufficient gap 19 can be formed between the wirings 17, and the capacitance between the wirings 17 can be reduced. In fact, when the parasitic capacitance between the wirings was measured using the apparatus according to the example 1, it was confirmed that the parasitic capacitance could be reduced to approximately half as compared with the conventional apparatus, and the device could be speeded up by about 5%.

Embodiment 2 Referring to FIG. 4 and FIG. In the second embodiment, an aluminum thin film 21 having a thickness of 3 μm was used as a support film. First, this aluminum thin film 21
After forming the O ₂ film (cap film) 13, the flat member 22 was formed by annealing at 400 ° C. And
As in the first embodiment, after bonding to the semiconductor substrate 15 as shown in FIG. 4, the aluminum thin film 21 was removed by ordinary dry etching. At this time, since the selectivity with respect to the oxide film is sufficient, only the cap film 13 can be left as shown in FIG. Here, by using a tungsten thin film instead of the aluminum thin film, baking can be performed at a higher temperature, so that a dense interlayer film can be formed.

(Embodiment 3) Referring to FIG. 6 and FIG. Here, FIG. 6 is a cross-sectional view of the integrated circuit device according to the third embodiment, and FIG. 7 is a circuit diagram of wiring constituting one configuration of the device. The third embodiment is different from the first and second embodiments in that the cap film 13 is formed on the Si substrate 14 including the wiring 17 so as to directly contact the wiring 17 without using the second interlayer insulating film. different. As shown in FIG. 7, the wiring 17 has a configuration in which an electric circuit 42 is arranged inside a ring of a closed dummy wiring 41 which is held at a fixed potential.

In each of the above embodiments, a gap 19 is provided between the wirings.
However, the capacitance between the wirings can be reduced even if an insulating film having a low dielectric constant is interposed between the wirings instead of forming the air gap.

[0024]

As described above in detail, according to the present invention, a plurality of wirings are formed on a semiconductor substrate at a distance from each other via a first insulating film, and a second wiring is formed on the semiconductor substrate including the wirings. An insulating material is formed such that the highest part of the second insulating film located between the wirings is located at a position lower than the second insulating film above the wirings, thereby forming a semiconductor substrate. After a flat member in which a third insulating film is formed on a supporting film made of is laminated on the semiconductor substrate so that the third insulating film is in close contact with the second insulating film, the supporting film of the flat member is removed. Accordingly, it is an object of the present invention to provide a method of manufacturing an integrated circuit device in which a sufficient gap is formed between wirings, thereby reducing the capacitance between the wirings.

Further, according to the present invention, a plurality of wirings are formed on a semiconductor substrate so as to be separated from each other via a first insulating film, and a second insulating film is formed on the semiconductor substrate including the wirings between the wirings. A semiconductor substrate is formed by forming the highest position of the second insulating film located at a position lower than the second insulating film above the wiring, and forming the third insulating film on the support film made of an inorganic material. After the formed flat member subjected to the annealing treatment is overlaid on the semiconductor substrate so that the third insulating film is in close contact with the second insulating film, the supporting film of the flat member is removed, whereby the distance between the wirings is reduced. Thus, it is possible to provide a method of manufacturing an integrated circuit device in which a sufficient gap is formed so that the capacitance between wirings can be reduced.

Further, according to the present invention, a plurality of wirings are formed on a semiconductor substrate so as to be separated from each other via a first insulating film, and a second insulating film is formed on a support film made of an organic material or an inorganic material. After the flat member is overlaid on the semiconductor substrate such that the second insulating film is in close contact with the wiring, a sufficient gap is formed between the wirings by removing the support film of the flat member, thereby forming a gap between the wirings. A method for manufacturing an integrated circuit device capable of reducing the capacitance can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of an integrated circuit device according to the present invention.

FIG. 2 is a sectional view showing one step of the method for manufacturing the integrated circuit device according to the first embodiment of the present invention, before the semiconductor substrate and the flat member are bonded to each other.

FIG. 3 is a cross-sectional view illustrating one step of the method for manufacturing the integrated circuit device according to the first embodiment of the present invention, in which the semiconductor substrate and the flat member are bonded and the final step after annealing is performed.

FIG. 4 is a cross-sectional view showing a step in a manufacturing method of the integrated circuit device according to the second embodiment of the present invention, after a semiconductor substrate and a flat member are bonded.

FIG. 5 is a sectional view showing one step of the method for manufacturing the integrated circuit device according to the second embodiment of the present invention, and showing the final step after the support film is removed from the flat member.

FIG. 6 is a sectional view of an integrated circuit device according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram of wiring showing one configuration of the integrated circuit device of FIG. 6;

[Explanation of symbols]

 11, 22: flat member, 12, 21, supporting film, 13: second insulating film (cap film), 14: Si substrate, 15: semiconductor substrate, 16: first interlayer insulating film (first insulating film) 17) wiring, 18 ... second interlayer insulating film (second insulating film), 19 ... void.

Claims (6)

[Claims] A step of forming a plurality of wirings on a semiconductor substrate at a distance from each other via a first insulating film; and a step of positioning a second insulating film on the semiconductor substrate including the wirings between the wirings. The highest part of the second insulating film is the second part on the upper part of the wiring.
Forming a semiconductor substrate at a position lower than that of the insulating film, and forming a flat member having a third insulating film formed on a support film made of an organic material or an inorganic material by the third insulating film. A method of manufacturing an integrated circuit device, comprising: a step of stacking a film on the semiconductor substrate so that the film is in close contact with the second insulating film; and a step of removing a support film of the flat member. 2. A step of forming a plurality of wirings on a semiconductor substrate so as to be separated from each other via a first insulating film; and a step of positioning a second insulating film on the semiconductor substrate including the wirings between the wirings. The highest part of the second insulating film is the second part on the upper part of the wiring.
Forming a semiconductor substrate at a position lower than that of the insulating film, forming a third insulating film on a support film made of an inorganic material, and then annealing the flat member. 3. A method of manufacturing an integrated circuit device, comprising: a step of superposing the insulating film on the semiconductor substrate so that the insulating film is in close contact with the third insulating film; and a step of removing the supporting film of the flat member. . 3. A step of forming a plurality of wirings on a semiconductor substrate at a distance from each other with a first insulating film interposed therebetween, and a step of forming a second insulating film on a supporting film made of an organic material or an inorganic material. Manufacturing an integrated circuit device, comprising: a step of stacking a member on the semiconductor substrate so that the second insulating film is in close contact with the wiring; and a step of removing a support film of the flat member. Method. 4. The method according to claim 1, wherein the thickness of the supporting film is 10 μm or less. 5. The method for manufacturing an integrated circuit device according to claim 1, wherein the inorganic material of the support film is a metal. 6. The method of manufacturing an integrated circuit device according to claim 3, wherein said wiring has an electric circuit disposed inside a loop of a closed dummy wiring which is held at a constant potential.