JPH03262133A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent shortcircuit between a gate electrode and source.drain electrode from occurring by a method wherein a three layer structure holding an Si3N4 film as a stopper of wet etching process is formed between an SiO2 film and another SiO2 film. CONSTITUTION:A p-type Si substrate 1 is covered with an Si3N4 film 11 to pattern an element formation region. Next, an element isolating SiO2 film 12 is formed by thermal-oxidation process to form an SiO2 film by hydrochloric acid oxidation. Next, a gate SiO2 film 2 is formed using a gate electrode 3 formed by patterning as a mask. Next, phosphorus ions are implanted in the Si substrate 1 to form a source.drain diffused layer 4. Next, the SiO2 film 2 is covered by CVD process and then sidewall SiO2 films 5 are left by anisotropic dry-etching process. Successively, the other SiO2 film 6, another Si3N4 film 7 and the other SiO2 film 8 are successively laminated to form a three layer structure. Finally, the SiO2 film 8 is patterned using a resist and then the Si3N4 film 7 and the SiO2 film 6 are continuously etched away to make a contact hole thus forming electrodes 9, 10.

Description

[Detailed description of the invention] 〔overview〕 The present invention relates to a method for manufacturing a semiconductor device.

In a method for forming an interlayer insulating film that separates a gate electrode and a source/drain electrode of a semiconductor device for the purpose of preventing short circuit between electrodes, a first cover 5iOz film is formed on a Si substrate; Cover 5iJ4 film The step of sequentially laminating the second cover SiO□ film, and the second cover S
a step of patterning and removing the source/train contact formation region of the iO□ film;

Using the second cover 5iOz film as a mask, cover Si
3N am and the step of removing source/drain contact hole forming regions of the first SiO□ film by anisotropic dry etching.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device.

In recent years, as semiconductors have become more highly integrated and finer, advanced manufacturing techniques have been required for forming two-layer insulating films and multilayer wiring.

[Conventional technology]

FIG. 3 is an explanatory diagram of a conventional example.

In the figure, 13 is a Si substrate, 14 is a silicon substrate, 15 is a polycrystalline silicon (poly-Si) gate electrode 216 is a source/drain diffusion layer, 17 is a sidewall SiO
□ film, 18 is a cover SiO □ film, 19 is titanium nitride (T
iN) source/drain electrodes, 20mm aluminum (A
I) Source/drain extraction electrode.

In manufacturing a highly integrated Mis-type semiconductor device, it is necessary to form source/drain electrodes 9 between poly-Si gate electrodes 15 with very narrow intervals.

In order to improve the coverage of the source/drain electrodes 9, the cover SiO□ film 18, which serves as a three-layer insulating film, is tapered and etched.

[Problem to be solved by the invention]

However, at this time, as shown by the arrow in Fig. 3, the cover 5
The thickness of the in2 film 18 becomes thinner at a location facing the shoulder portion of the poly-Si gate electrode 15, and there is a risk of short-circuiting between the poly-Si gate electrode 15 and the TiN source/drain electrode 19.

The present invention is provided for the purpose of preventing a short circuit between a gate electrode and a source/drain electrode in forming a cover oxide film.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, 1 is a Si substrate, 2 is a gate 5, an iOz film 3 is a poly-Si gate electrode, 4 is a source/train diffusion layer, and 5 is a poly-Si gate electrode.
6 is the side wall SiO□ film, and 6 is the first cover SiO
□Membrane, 7 is cover 513N4 membrane, 8 is second cover Si
O□ film, 9 is TiN source/drain electrode, 10 is Aj
2 source/drain lead electrodes.

The purpose of the present invention is to remove Si without deteriorating the coverage of the source/drain electrodes and to prevent the shoulder portion of the gate electrode from being exposed during etching of the cover SiO□ film.
This is achieved by forming a three-layer structure in which a 5iJ4 film is sandwiched between the O□ film and the SiO□ film as a wet etching stopper.

That is, in a method for forming an interlayer insulating film separating a gate electrode and source/drain electrodes of a semiconductor device, a first cover SiO□ film 6. Cover Si3N4 film7.
a step of sequentially stacking a second cover SiO□ film 8; a step of removing the source/drain contact hole formation region of the second cover SiO□ film 8 by buttering;
Using the second cover SiO□ film 8 as a mask, cover S
i3N4 membrane7. and removing the source/drain contact hole formation regions of the first cover SiO□ film 6 by anisotropic dry etching.

[Effect]

By means of the present invention, when the cover SiO□ film is etched, the shoulder portion of the gate electrode is not exposed due to the 5i3Na film of the stopper, and short circuit between the source/drain electrode and the gate electrode can be prevented.

〔Example〕

FIG. 2 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps.

In the figure, ■ is a Si substrate, 2 is a gate 5, iOz film 3 is a poly-Si gate electrode, 4 is a source/toluin diffusion layer, and 5 is a gate electrode.
6 is the Zide wall SiO□ film, 6 is the first cover SiO
□Membrane, 7 is cover Si, N, membrane, 8 is second cover 5i
02 film, 9 is TiN source/drain electrode, 10 is AA
Source/drain extraction electrode, 11 is SiJ film, 12
is an element isolation 5iO7 film.

An embodiment of the present invention will be explained with reference to FIG.

As shown in FIG. 2(a), a CV
A 1,000-layer thick Si 3N s film 1 was prepared using the D method.
1 is coated, and the element formation region is patterned.

As shown in FIG. 2(b), an element isolation film 12 having a thickness of 6,000 g is formed in the element isolation region by thermal oxidation. Subsequently, a SiO□ film 2 for the SiOz film is formed to a thickness of 200 mm by hydrochloric acid oxidation.

As shown in FIG. 2(C), a poly-Si film is coated to a thickness of 3,000 nm at 600°C by CVD method, and is subjected to buttering to form a poly-Si gate electrode 3. 3 as a mask, a gate SiO□ film 2 is formed.

As shown in Figure 2(d), S
The phosphorus ions (p゛) are accelerated in the i-substrate 1 at a voltage of 40 keV.
It was implanted under the conditions of a dose of 2xLOIS, and nitrogen (N2
) The implanted ions are activated by annealing at 900° C. for 30 minutes in a gas atmosphere to form source/drain diffusion layers 4.

As shown in FIG. 2(e), by CVD method.

A 5in2 film was coated to a thickness of 2,000 mm using the CVD method.

Anisotropic dry etching is performed to leave the sidewall SiO2 film 5 only on the sides of the poly-Si electrode 1-electrode 3.

Subsequently, the first cover 5iOz film 6 is formed by CVD method.
2,000 people at 800°C, and cover S
300 i3N4 films 7 were grown, and a second cover S was added.
2,700 iO□ films 8 are stacked to form a three-layer structure of insulating films.

In order to open three source/drain contact holes as shown in FIG. 2(f), the upper second cover SiO□ film 8 is patterned by wet etching with hydrofluoric acid using a resist. At this time, the S1-3i3N4 film 7 and the first cover SiO□ film 6 are continuously etched on the surface of the cover Si3N4 film 7, and a contact hole is opened in the surface of the source/drain diffusion layer.

As shown in Figure 2())), TiN
Titanium to the thickness of 2,000 people, followed by 8! was continuously coated to a thickness of 1 μm and patterned.

TiN source/drain electrode9. Additionally, a ρ source train lead electrode 10 is formed.

〔Effect of the invention〕

As explained above, according to the present invention, the stopper 5
The gate shoulder portion is not exposed due to the i3Na film.

Short circuits between the gate electrode and the source/drain electrodes can be prevented, which greatly contributes to improving the reliability of the device.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the principle of the present invention. FIG. 2 is a schematic cross-sectional view of an embodiment of the present invention in the order of steps. FIG. 3 is an explanatory diagram of a conventional example. In the figure, 1 is a Si substrate, and 2 is a gate SiO□ film. 3 is a poly-Si gate electrode. 4 is the source train diffusion layer. 5 is a sidewall SiO2 film. 6 is the first cover SiO□ film. 7 is a cover Si3N4 film, and 8 is a second cover SiO□ film. 9 is a TiN source/drain electrode. IO is the AP source/drain extraction electrode.

Claims (1)

[Claims] In a method for forming an interlayer insulating film separating a gate electrode and source/drain electrodes of a semiconductor device, silicon (Si)
On the substrate (1), a first cover silicon dioxide (SiO
_2) Film (6), cover silicon nitride (Si_3N_4
a step of sequentially stacking a film (7) and a second cover SiO_2 film (8); a step of patterning and removing the source/drain contact hole formation region of the second cover SiO_2 film (8); Using the second cover SiO_2 film (8) as a mask, cover SiO_3N_4 film (7) and first cover Si
A method for manufacturing a semiconductor device, comprising the step of removing source/drain contact hole forming regions of the O_2 film (6) by anisotropic dry etching.