JPH11282820A5 - - Google Patents

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Publication number
JPH11282820A5
JPH11282820A5 JP1998340924A JP34092498A JPH11282820A5 JP H11282820 A5 JPH11282820 A5 JP H11282820A5 JP 1998340924 A JP1998340924 A JP 1998340924A JP 34092498 A JP34092498 A JP 34092498A JP H11282820 A5 JPH11282820 A5 JP H11282820A5
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JP
Japan
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address
computer system
reference information
multiprocessor
ordered
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Granted
Application number
JP1998340924A
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English (en)
Japanese (ja)
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JP4700773B2 (ja
JPH11282820A (ja
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Publication date
Priority claimed from US08/957,298 external-priority patent/US6122714A/en
Application filed filed Critical
Publication of JPH11282820A publication Critical patent/JPH11282820A/ja
Publication of JPH11282820A5 publication Critical patent/JPH11282820A5/ja
Application granted granted Critical
Publication of JP4700773B2 publication Critical patent/JP4700773B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP34092498A 1997-10-24 1998-10-26 スイッチをベースとするマルチプロセッサシステムに使用するための順序サポート機構 Expired - Fee Related JP4700773B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/957298 1997-10-24
US08/957,298 US6122714A (en) 1997-10-24 1997-10-24 Order supporting mechanisms for use in a switch-based multi-processor system

Publications (3)

Publication Number Publication Date
JPH11282820A JPH11282820A (ja) 1999-10-15
JPH11282820A5 true JPH11282820A5 (enExample) 2005-12-02
JP4700773B2 JP4700773B2 (ja) 2011-06-15

Family

ID=25499385

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34092498A Expired - Fee Related JP4700773B2 (ja) 1997-10-24 1998-10-26 スイッチをベースとするマルチプロセッサシステムに使用するための順序サポート機構

Country Status (4)

Country Link
US (1) US6122714A (enExample)
EP (1) EP0911731B1 (enExample)
JP (1) JP4700773B2 (enExample)
DE (1) DE69832943T2 (enExample)

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US6725307B1 (en) 1999-09-23 2004-04-20 International Business Machines Corporation Method and system for controlling data transfers with physical separation of data functionality from address and control functionality in a distributed multi-bus multiprocessor system
US6457085B1 (en) 1999-11-04 2002-09-24 International Business Machines Corporation Method and system for data bus latency reduction using transfer size prediction for split bus designs
US6529990B1 (en) 1999-11-08 2003-03-04 International Business Machines Corporation Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system
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US7529799B2 (en) 1999-11-08 2009-05-05 International Business Machines Corporation Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system
US6523076B1 (en) 1999-11-08 2003-02-18 International Business Machines Corporation Method and apparatus for synchronizing multiple bus arbiters on separate chips to give simultaneous grants for the purpose of breaking livelocks
US6542949B1 (en) 1999-11-08 2003-04-01 International Business Machines Corporation Method and apparatus for increased performance of a parked data bus in the non-parked direction
US6606676B1 (en) 1999-11-08 2003-08-12 International Business Machines Corporation Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor system
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US6842830B2 (en) * 2001-03-31 2005-01-11 Intel Corporation Mechanism for handling explicit writeback in a cache coherent multi-node architecture
US7237016B1 (en) * 2001-09-07 2007-06-26 Palau Acquisition Corporation (Delaware) Method and system to manage resource requests utilizing link-list queues within an arbiter associated with an interconnect device
US8189591B2 (en) * 2001-10-30 2012-05-29 Exar Corporation Methods, systems and computer program products for packet ordering for parallel packet transform processing
US6961827B2 (en) * 2001-11-13 2005-11-01 Sun Microsystems, Inc. Victim invalidation
US20030196081A1 (en) * 2002-04-11 2003-10-16 Raymond Savarda Methods, systems, and computer program products for processing a packet-object using multiple pipelined processing modules
US6892290B2 (en) * 2002-10-03 2005-05-10 Hewlett-Packard Development Company, L.P. Linked-list early race resolution mechanism
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
JP2004171209A (ja) * 2002-11-19 2004-06-17 Matsushita Electric Ind Co Ltd 共有メモリデータ転送装置
US7636815B1 (en) 2003-04-09 2009-12-22 Klaiber Alexander C System and method for handling direct memory accesses
US8751753B1 (en) * 2003-04-09 2014-06-10 Guillermo J. Rozas Coherence de-coupling buffer
US8117392B2 (en) * 2003-10-22 2012-02-14 Intel Corporation Method and apparatus for efficient ordered stores over an interconnection network
US7856534B2 (en) * 2004-01-15 2010-12-21 Hewlett-Packard Development Company, L.P. Transaction references for requests in a multi-processor network
US7971002B1 (en) 2005-04-07 2011-06-28 Guillermo Rozas Maintaining instruction coherency in a translation-based computer system architecture
US7519778B2 (en) * 2005-08-10 2009-04-14 Faraday Technology Corp. System and method for cache coherence
US7958513B2 (en) * 2005-11-17 2011-06-07 International Business Machines Corporation Method, system and program product for communicating among processes in a symmetric multi-processing cluster environment
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