DE69832943T2 - Sequenzsteuerungsmechanismus für ein switch-basiertes Mehrprozessorsystem - Google Patents

Sequenzsteuerungsmechanismus für ein switch-basiertes Mehrprozessorsystem Download PDF

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Publication number
DE69832943T2
DE69832943T2 DE69832943T DE69832943T DE69832943T2 DE 69832943 T2 DE69832943 T2 DE 69832943T2 DE 69832943 T DE69832943 T DE 69832943T DE 69832943 T DE69832943 T DE 69832943T DE 69832943 T2 DE69832943 T2 DE 69832943T2
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Prior art keywords
address
processor
node
data
multiprocessor
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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DE69832943T
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German (de)
English (en)
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DE69832943D1 (de
Inventor
Stephen R. Northborough Vandoren
Simon C. Hudson Steely
Madhumitra Shrewsbury Sharma
David M. Acton Fenwick
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Compaq Computer Corp
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Compaq Computer Corp
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
DE69832943T 1997-10-24 1998-10-12 Sequenzsteuerungsmechanismus für ein switch-basiertes Mehrprozessorsystem Expired - Lifetime DE69832943T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/957,298 US6122714A (en) 1997-10-24 1997-10-24 Order supporting mechanisms for use in a switch-based multi-processor system
US957298 1997-10-24

Publications (2)

Publication Number Publication Date
DE69832943D1 DE69832943D1 (de) 2006-02-02
DE69832943T2 true DE69832943T2 (de) 2006-06-29

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DE69832943T Expired - Lifetime DE69832943T2 (de) 1997-10-24 1998-10-12 Sequenzsteuerungsmechanismus für ein switch-basiertes Mehrprozessorsystem

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US (1) US6122714A (enExample)
EP (1) EP0911731B1 (enExample)
JP (1) JP4700773B2 (enExample)
DE (1) DE69832943T2 (enExample)

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US6457085B1 (en) 1999-11-04 2002-09-24 International Business Machines Corporation Method and system for data bus latency reduction using transfer size prediction for split bus designs
US6529990B1 (en) 1999-11-08 2003-03-04 International Business Machines Corporation Method and apparatus to eliminate failed snoops of transactions caused by bus timing conflicts in a distributed symmetric multiprocessor system
US6516379B1 (en) 1999-11-08 2003-02-04 International Business Machines Corporation Method and apparatus for transaction pacing to reduce destructive interference between successive transactions in a distributed symmetric multiprocessor system
US7529799B2 (en) 1999-11-08 2009-05-05 International Business Machines Corporation Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system
US6523076B1 (en) 1999-11-08 2003-02-18 International Business Machines Corporation Method and apparatus for synchronizing multiple bus arbiters on separate chips to give simultaneous grants for the purpose of breaking livelocks
US6542949B1 (en) 1999-11-08 2003-04-01 International Business Machines Corporation Method and apparatus for increased performance of a parked data bus in the non-parked direction
US6606676B1 (en) 1999-11-08 2003-08-12 International Business Machines Corporation Method and apparatus to distribute interrupts to multiple interrupt handlers in a distributed symmetric multiprocessor system
US6684279B1 (en) 1999-11-08 2004-01-27 International Business Machines Corporation Method, apparatus, and computer program product for controlling data transfer
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US6892279B2 (en) 2000-11-30 2005-05-10 Mosaid Technologies Incorporated Method and apparatus for accelerating retrieval of data from a memory system with cache by reducing latency
US6587920B2 (en) 2000-11-30 2003-07-01 Mosaid Technologies Incorporated Method and apparatus for reducing latency in a memory system
US6493801B2 (en) 2001-01-26 2002-12-10 Compaq Computer Corporation Adaptive dirty-block purging
US6842830B2 (en) * 2001-03-31 2005-01-11 Intel Corporation Mechanism for handling explicit writeback in a cache coherent multi-node architecture
US7237016B1 (en) * 2001-09-07 2007-06-26 Palau Acquisition Corporation (Delaware) Method and system to manage resource requests utilizing link-list queues within an arbiter associated with an interconnect device
US8189591B2 (en) * 2001-10-30 2012-05-29 Exar Corporation Methods, systems and computer program products for packet ordering for parallel packet transform processing
US6961827B2 (en) * 2001-11-13 2005-11-01 Sun Microsystems, Inc. Victim invalidation
US20030196081A1 (en) * 2002-04-11 2003-10-16 Raymond Savarda Methods, systems, and computer program products for processing a packet-object using multiple pipelined processing modules
US6892290B2 (en) * 2002-10-03 2005-05-10 Hewlett-Packard Development Company, L.P. Linked-list early race resolution mechanism
US8185602B2 (en) 2002-11-05 2012-05-22 Newisys, Inc. Transaction processing using multiple protocol engines in systems having multiple multi-processor clusters
JP2004171209A (ja) * 2002-11-19 2004-06-17 Matsushita Electric Ind Co Ltd 共有メモリデータ転送装置
US7636815B1 (en) 2003-04-09 2009-12-22 Klaiber Alexander C System and method for handling direct memory accesses
US8751753B1 (en) * 2003-04-09 2014-06-10 Guillermo J. Rozas Coherence de-coupling buffer
US8117392B2 (en) * 2003-10-22 2012-02-14 Intel Corporation Method and apparatus for efficient ordered stores over an interconnection network
US7856534B2 (en) * 2004-01-15 2010-12-21 Hewlett-Packard Development Company, L.P. Transaction references for requests in a multi-processor network
US7971002B1 (en) 2005-04-07 2011-06-28 Guillermo Rozas Maintaining instruction coherency in a translation-based computer system architecture
US7519778B2 (en) * 2005-08-10 2009-04-14 Faraday Technology Corp. System and method for cache coherence
US7958513B2 (en) * 2005-11-17 2011-06-07 International Business Machines Corporation Method, system and program product for communicating among processes in a symmetric multi-processing cluster environment
JP5076418B2 (ja) * 2006-09-19 2012-11-21 ソニー株式会社 共有メモリ装置
US20080098178A1 (en) * 2006-10-23 2008-04-24 Veazey Judson E Data storage on a switching system coupling multiple processors of a computer system
US9075723B2 (en) * 2011-06-17 2015-07-07 International Business Machines Corporation Efficient discard scans

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Also Published As

Publication number Publication date
EP0911731B1 (en) 2005-12-28
EP0911731A3 (en) 2000-08-09
JP4700773B2 (ja) 2011-06-15
EP0911731A2 (en) 1999-04-28
US6122714A (en) 2000-09-19
DE69832943D1 (de) 2006-02-02
JPH11282820A (ja) 1999-10-15

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