JPH11260723A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high-performance semiconductor element which has a small leakage current, stable characteristics and a high integration density by a simple, convenient and high-yield manufacturing process. SOLUTION: Catalyst element for promoting crystallization of an amorphous silicon film is selectively introduced into a plurality of linear regions 100 arranged in parallel and spaced at predetermined intervals for heat-treatment. Thereby the amorphous silicon film can be grown and crystallized in directions (transversal directions) nearly parallel to a substrate from the regions 100 to their peripheral regions. And a transversal-direction crystallized silicon film 103b defined by the two regions 100 and 100 is utilized to form an active region 103i of a semiconductor element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device having a crystalline silicon film obtained by crystallizing an amorphous silicon film as an active region and a method of manufacturing the same. In particular, the present invention is effective for a semiconductor device having a TFT (thin film transistor) provided on an insulating substrate, and can be applied to an active matrix liquid crystal display device, a contact image sensor, a three-dimensional IC, and the like. .

[0002]

2. Description of the Related Art In recent years, large and high resolution liquid crystal display devices have been developed.
High-speed, high-resolution contact image sensor, 3D IC
In order to realize such a technique, attempts have been made to form a high-performance semiconductor element on an insulating substrate such as glass or on an insulating film. In general, a thin film silicon semiconductor is used for a semiconductor element used in these devices.

[0003] The silicon semiconductor in the form of a thin film is roughly classified into two types: an amorphous silicon semiconductor (a-Si); and a crystalline silicon semiconductor. Amorphous silicon semiconductors are most commonly used because they have a low production temperature, can be relatively easily produced by a gas phase method, and have high mass productivity. Inferior to silicon semiconductors. Therefore, in order to obtain higher-speed characteristics in the future, it is strongly required to establish a method for manufacturing a semiconductor device made of a crystalline silicon semiconductor. still,
As the silicon semiconductor having crystallinity, polycrystalline silicon,
Microcrystalline silicon, amorphous silicon containing a crystalline component, semi-amorphous silicon having an intermediate state between crystalline and amorphous are known.

The following methods can be used to obtain these crystalline silicon semiconductor layers in the form of thin films.

(1) A semiconductor film having crystallinity is directly formed at the time of film formation.

(2) An amorphous semiconductor film is formed, and then the semiconductor film is made crystalline by the energy of laser light.

(3) An amorphous semiconductor film is formed, and then the semiconductor film is made crystalline by applying thermal energy.

However, in the above-mentioned method (1), crystallization proceeds simultaneously with the film formation step. Therefore, it is necessary to increase the thickness of the silicon film in order to obtain crystalline silicon having a large grain size. It is technically difficult to uniformly form a film having physical properties over the entire surface of the substrate. Furthermore, in this method, since the film formation temperature is as high as 600 ° C. or more, there is a problem in terms of cost that an inexpensive glass substrate cannot be used.

In the above method (2), the crystallization phenomenon in the melt-solidification process is utilized, so that the grain boundaries are favorably processed while having a small grain size, and a high-quality crystalline silicon film is obtained.
Taking an excimer laser, which is currently most commonly used as a laser, as an example, the first problem is that the laser light irradiation area is small and the throughput is low. And
The biggest problem is that it is difficult to obtain a silicon film with uniform crystallinity because the stability of the laser is not enough to process the entire surface of a large-area substrate uniformly. However, it is difficult to form a plurality of semiconductor elements.

Further, the method of (3) includes the steps of (1)
Compared to the method (2), there is an advantage that a large area can be dealt with, but a heat treatment at a high temperature of 600 ° C. or more for several tens of hours is required for crystallization. On the other hand, considering the use of an inexpensive glass substrate and the improvement of throughput, it is necessary to lower the heating temperature and crystallize in a shorter time. Thus, in the method (3), it is necessary to simultaneously solve conflicting problems.

In the method (3), since the solid phase crystallization phenomenon is used, the crystal grains spread in parallel to the substrate surface and have a size of several μm.
However, since the grown crystal grains collide with each other to form a grain boundary, the grain boundary acts as a trap level for carriers and is a major cause of lowering the mobility of the TFT. Would.

Therefore, a method of producing a silicon film having high quality and uniform crystallinity by a lower temperature and shorter time heat treatment utilizing the above method (3) is disclosed in JP-A-7-29.
7125 and JP-A-8-148426.

According to these publications, by introducing a trace amount of a metal element such as nickel onto the surface of an amorphous silicon film and then heating it, at a low temperature of 600 ° C. or less, a treatment time of about several hours is required. Crystallized. It is understood that this mechanism is such that crystal nucleus generation with a metal element as a nucleus occurs at an early stage of the heat treatment, and then the metal element serves as a catalyst to promote crystal growth to rapidly progress crystallization. In this sense, these metal elements are hereinafter referred to as catalyst elements. The crystalline silicon film grown by the crystallization promoted by these catalytic elements has a twin structure, whereas a crystalline silicon film obtained by crystallizing an amorphous silicon film by a normal solid-phase growth method has a twin structure. Each of the columnar crystals is in an ideal single crystal state.

Further, according to these publications, by selectively introducing such a catalytic element into a part of the amorphous silicon film and performing heat treatment, a part where the catalytic element is not introduced becomes amorphous. Only the region into which the catalytic element has been introduced is selectively crystallized while remaining in the state of the porous silicon film. By further extending the heat treatment time, the crystal is grown in a lateral direction from the region where the catalytic element is selectively introduced, that is, in a direction substantially parallel to the substrate surface.

In this lateral crystal growth region, columnar crystals whose growth directions are almost aligned in one direction are squeezed, and compared with a region where a catalyst element is directly introduced and crystal nuclei are generated randomly. The region has good crystallinity. Then, a high-performance semiconductor device is manufactured using the silicon film in the lateral crystal growth region having good crystallinity as an active region.

In Japanese Patent Application Laid-Open No. 7-297125,
In the silicon film in the lateral crystal growth region, the active region of the semiconductor element is formed by using a high-quality portion in which the growth direction is aligned in one direction. The distance between is limited. Further, in Japanese Patent Application Laid-Open No. 8-148426, the introduction region of the catalyst element is defined as a linear region, and the amount of the introduced catalyst element is controlled by the line width.

[0017]

The above-mentioned JP-A-7-29
The technology proposed in JP-A-7125 and JP-A-8-148426 is a very effective technology that enables a high-performance semiconductor device to be obtained by a simple and high-throughput manufacturing process. However, these techniques still have two major problems.

(1) First, the first problem is the effect of the catalytic element on the semiconductor element. Naturally, the presence of a large amount of the above-mentioned catalyst element in a semiconductor impairs the reliability and electrical stability of a device using the semiconductor, and is not desirable. In other words, the catalyst element that promotes crystallization is necessary when crystallizing amorphous silicon, but it is desirable that the crystallized silicon be contained as little as possible.

Conventionally, two methods have been used to achieve this object.

In the first method, a catalyst element having a strong tendency to be inactive in crystalline silicon is selected as a catalyst element, and the amount of the catalyst element required for crystallization is minimized to minimize crystallization. Is to do. However, in practice, it is very difficult to control a very small amount of a low concentration.

The second method is described in Japanese Patent Application Laid-Open No. 7-29712.
No. 5, Japanese Patent Application Laid-Open No. 8-148426 discloses a method for selectively introducing a catalytic element, that is, use of a lateral crystal growth region. As described above, the lateral crystal growth region has a uniform growth direction in one direction, and is in a more favorable crystal state. Further, at this time, the catalyst element contributing to the crystallization exists at the tip of the columnar crystal, that is, at the tip of the crystal growth. Therefore, theoretically, the catalyst element exists only at the crystal growth tip where crystallization is performed, and does not exist in the already crystallized lateral crystal growth region. Therefore, the concentration of the catalytic element in the crystalline silicon film grown in the lateral direction should be close to zero. Actually, the catalytic element concentration in the lateral crystal growth region is about one digit smaller than that in the region where the catalytic element is directly introduced and crystallized, and it is certain that there is a sufficient merit.
However, a part of the catalyst element is surely left during the lateral crystal growth. Therefore, when an active region of a plurality of thin film transistors is formed using such a lateral crystal growth region, most of the devices show good characteristics, but in some devices, the leakage current particularly when turned off tends to increase. Can be seen. An analysis of the cause of such a defective element revealed that the catalytic element was unevenly distributed at the junction between the channel region and the drain region in the active region, and that the effect was due to the residual catalytic element during the lateral crystal growth. found.

(2) The second problem is the instability of crystal growth during lateral crystal growth. The lateral crystal growth depends on the delicate concentration of the catalytic element. If the amount of the catalytic element is small, sufficient crystal growth does not occur, and even if the heating time is extended, no further crystal growth occurs. Therefore, such a poor growth region is filled with the silicon film grown by the spontaneous nucleation of the amorphous silicon film itself, or the lateral growth component by the catalytic element and the crystal component by the spontaneous nucleation. And a hybrid state. Since a semiconductor device manufactured using such a poor growth region has a large difference in characteristics from a semiconductor device manufactured using a good lateral growth region using a catalytic element, a uniform high-performance device over the entire substrate is required. I can't really get it. In addition, even if such a growth failure is out of the problem, even in a region where the lateral growth is performed at the level observed with an optical microscope, the lateral growth region may be different due to the difference in the concentration or state of the introduced catalytic element. The crystallinity of the silicon film in the semiconductor device is slightly different, which causes a characteristic difference and a variation of the semiconductor element.

The techniques proposed in the above-mentioned JP-A-7-297125 and JP-A-8-148426 are as follows.
It is intended to solve these problems, and its effectiveness is certain. However, these technologies alone were not enough, and more advanced technological reforms were needed.

The present invention has been made in order to solve such problems of the prior art, and performs a low concentration control of the catalyst element by a simpler method than in the prior art to efficiently remove the catalyst element in the selective introduction region in the lateral direction. Utilizing for crystal growth, reducing the concentration of residual catalytic elements in the active region, stabilizing the crystallinity of the silicon film constituting the active region, and manufacturing high-performance semiconductor devices and stable semiconductor devices with high yield The aim is to provide a method.

[0025]

Means for Solving the Problems The present inventors focused on the high crystallinity of a silicon film which was selectively introduced with a catalytic element, and was laterally crystal-grown from the introduction part, and utilized this to provide a high performance thin film semiconductor. We worked diligently to manufacture the equipment uniformly and stably. As a result, knowledge on the properties of the catalytic elements was obtained, and the present invention was completed.

The semiconductor device of the present invention is a semiconductor device in which an active region made of a crystalline silicon film is provided on a substrate having an insulating surface, and the active region is made of a crystalline silicon film. The catalytic element that promotes the
_S is provided and selectively introduced into a plurality of linear regions arranged substantially in parallel, and a crystal is grown in a direction substantially parallel to the substrate surface from the introduction region to a peripheral region by a heat treatment, Moreover, it is formed between two adjacent linear regions, thereby achieving the above object.

The distance W _S between the linear regions is such that the catalyst element is introduced into a single linear region, and a silicon film is grown from the introduction region to the peripheral region in a direction substantially parallel to the substrate surface. It is desirable to set the range so that a higher crystal growth rate can be obtained.

[0028] The distance W _S between the linear region is set to 300μm or less.

[0029] The catalytic element concentration in the active region by a distance W _S between the line width W _L and the linear region of the linear region is controlled desirably.

[0030] The crystallinity of the silicon film constituting the active region by a distance W _S between the line width W _L and the linear region of the linear region is controlled desirably.

[0031] It is desirable the ratio W _S / W _L between the distance W _S between the line width W _L and the linear region of the linear region is 2.5 or more and 40 or less.

The length of the linear region in the long side direction is such that when the silicon film grows from the linear region to the peripheral region,
The growth tip of the silicon film is set in a range where a portion substantially parallel to the long side direction of the linear region exists, and the active region is formed between the growth tip of the silicon film and the linear region. It is preferable that the long side direction is formed in a portion substantially parallel to the long side direction.

The length of the linear region in the long side direction is 150 μm.
It is desirable to set it to m or more.

The concentration of the catalytic element in the active region is 1 × 10
^It is desirable that the concentration be controlled to ¹⁷ atoms / cm ³ or less.

According to the method of manufacturing a semiconductor device of the present invention, there is provided a step of forming an amorphous silicon film on a substrate, and promoting crystallization of the amorphous silicon film before or after the formation of the amorphous silicon film. the catalytic element, a step of selectively introducing a plurality of linear regions arranged generally parallel with a predetermined distance W _S, amorphous silicon linear region in which the catalytic element has been introduced by heat treatment The step of selectively crystallizing the film and the heat treatment are further continued, and the amorphous silicon film is crystallized in a direction substantially parallel to the substrate surface from the selectively crystallized region to its peripheral region. A growing step, a crystalline silicon film grown in a direction substantially parallel to the substrate surface, and a semiconductor element using a portion sandwiched between two adjacent linear regions. Forming an active region comprising: Ri the above-mentioned object can be achieved.

[0036] In the step of selectively introducing the catalyst element in the linear region, by previously setting the intervals W _S between the line width W _L and the linear region of the linear region, the It is desirable to control the concentration of the catalytic element in the active region.

[0037] In the step of selectively introducing the catalyst element in the linear region, by previously setting the intervals W _S between the line width W _L and the linear region of the linear region, the It is desirable to control the crystallinity of the silicon film constituting the active region.

[0038] After the step of forming an amorphous silicon film on the substrate, a mask film having a plurality of linear openings aligned generally parallel with a predetermined distance W _S on amorphous silicon film Providing a step of selectively introducing a catalytic element into the amorphous silicon film by introducing the catalytic element from above the mask film, and removing the mask film to form a line into which the catalytic element has been introduced. It is desirable to perform a step of growing crystals in a direction substantially parallel to the substrate surface from the shape region to the peripheral region.

After performing the step of growing crystals in a direction substantially parallel to the substrate surface from the linear region into which the catalytic element has been introduced to the peripheral region, the crystallized silicon film is irradiated with an energy beam. Preferably, the method further includes a step of further promoting the crystallinity of the silicon film.

A crystalline silicon film grown in a direction substantially parallel to the substrate surface and using a portion sandwiched between two adjacent linear regions to form an active element for forming a semiconductor element. After performing the step of forming the region, it is desirable to perform a step of irradiating the energy beam to further promote the crystallinity of the silicon film.

Hereinafter, the operation of the present invention will be described.

[0042] In the present invention, the plurality of linear regions arranged generally parallel with a predetermined distance W _S, introduced a catalytic element which promotes crystallization of the amorphous silicon film by heat treatment Crystal growth from the introduction region to its peripheral region in a direction substantially parallel to the substrate surface (lateral direction), and utilizing the lateral crystal growth portion formed between two adjacent linear regions, the active region To form As shown in FIG. 1, which will be described later, in this portion, the crystal growth can be stabilized and the crystallinity can be improved, so that a high-performance semiconductor device can be obtained at a high yield.

[0043] In the present invention, to reduce the spacing W _S between the linear region, the crystalline silicon film in the transverse direction by introducing a catalytic element into the linear region of the sole from the introduction region to the peripheral region thereof It is desirable to set the range so that a larger crystal growth rate can be obtained than in the case where the crystal is grown. As a result, as shown in FIG. 1 to be described later, a stable growth state is obtained in a lateral crystal growth portion sandwiched between two adjacent catalyst element introduction regions, and crystal growth in the lateral direction from a single introduction region. Crystallinity higher than that of the silicon film formed. In particular, as shown in FIG. 2 described later, the interval W _S between the linear region 300
It is desirable to set it to μm or less.

[0044] In the present invention, the catalytic element concentration in the line width W _L and the linear region of the linear region of the two adjacent catalyst elements introduction region between lateral crystal growth region between the (active region) It depends on the interval W _S between them. Therefore, it is desirable to control the spacing W _S between the line width W _L and the linear region of the linear areas, optimal with respect to the crystal growth and device characteristics thereby to control the concentration of the catalytic element in the active region Can be a value.

Further, in the present invention, two adjacent catalytic element introduction region lateral crystal growth region sandwiched between the (active region) of the crystalline line width W _L and the linear linear region It depends on the spacing W _S between the regions. Therefore, it is desirable to control the spacing W _S between the line width W _L and the linear region of the linear region, further enhancing the stability and crystallinity of the crystal growth thereby to control the crystallinity of the active region be able to. In particular, as shown in FIGS. 3 and 4 below, that the ratio W _S / W _L between the distance W _S between the line width W _L and the linear region of the linear region to 2.5 or more and 40 or less desirable.

In the present invention, as shown in FIG. 5 described later, when the length of the linear region in the long side direction is short, sufficient one-dimensional crystal growth cannot be obtained and the crystallinity is poor. Or the introduction of an excessive amount of a catalytic element may adversely affect the reliability of the semiconductor device. Therefore, by increasing the length of the linear region in the long side direction, when the silicon film grows from the linear region to the peripheral region, the growth tip of the silicon film is aligned with the long side direction of the linear region. It is desirable to set the range in which a substantially parallel portion exists. As a result, the crystal growth in the lateral direction is performed one-dimensionally in that portion, so that sufficient crystallization can be performed with a trace amount of the catalyst element. Then, by forming an active region using the lateral crystal growth region in this portion, a highly reliable semiconductor device can be obtained.
In particular, the length in the long side direction of the linear region into which the catalyst element is introduced is desirably set to 150 μm or more.

In the present invention, it is desirable that the concentration of the catalytic element in the active region be as low as possible. However, according to experiments by the present inventors, the concentration of the catalytic element in the active region of the TFT element is 1 × 1.
It has been confirmed that a semiconductor device having a durability of less than 0 ¹⁷ atoms / cm ³ can be obtained as a product from the viewpoint of reliability. Therefore, the concentration of the catalyst element in the active region is 1
× 10 ¹⁷ atoms / cm ³ is preferably controlled as follows.

In the method of manufacturing a semiconductor device according to the present invention, before or after the step of forming an amorphous silicon film on a substrate, a catalyst element for promoting crystallization of the amorphous silicon film is added to a predetermined element. Selective introduction into a plurality of linear regions arranged substantially in parallel with an interval of, and selectively crystallize the amorphous silicon film in the linear regions in which the catalytic element is introduced by performing a heat treatment; Further, an amorphous silicon film is crystal-grown in a lateral direction (a direction substantially parallel to the substrate surface) from the linear region to the peripheral region. Then, an active region to be a semiconductor element is formed by using the lateral crystal growth portion sandwiched between two adjacent linear regions. The inner lateral crystal growth region sandwiched between two adjacent linear regions has very good crystallinity and very little residual amorphous component compared to the outer lateral crystal growth region. Very low growth failure rate. By using this region to form an active region of a semiconductor element, it becomes possible to manufacture a very high-performance semiconductor device at a high yield.

According to the present invention, the catalyst element concentration in the lateral crystal growth region sandwiched between two adjacent linear regions is as follows:
It depends on the spacing W _S between the line width W _L and the linear region of the linear region. Therefore, a distance W _S between the line width W _L and the linear region of the linear region, by examining the relationship between the concentration of the catalytic element sandwiched between the linear region of two adjacent lateral crystal growth regions in advance Every
In actual manufacturing process of the semiconductor device, so that the catalytic element concentration in the lateral crystal growth region to be the active region has a desired value, and a distance W _S between the line width W _L and the linear region of the linear region It is desirable to set in advance.

Further, in the present invention, the catalyst element is introduced into a plurality of linear regions arranged in parallel, and the crystal of the lateral crystal growth region sandwiched between two adjacent linear regions is introduced. sex, depends on the interval W _S between the line width W _L and the linear region of the linear region. Therefore, a distance W _S between the line width W _L and the linear region of the linear region, previously examined the relationship between the crystallinity of sandwiched between the linear region of two adjacent lateral crystal growth regions in advance in actual manufacturing process of a semiconductor device, such crystalline lateral crystal growth region to be the active region has a desired value, and a distance W _S between the line width W _L and the linear region of the linear region It is desirable to set in advance.

[0051] In the present invention, it is possible to control low concentration of a catalytic element concentration in the active region by a distance W _S between the line width W _L and the linear region of the linear region. In order to control the line width of the linear region and the interval between the linear regions, a mask film having a plurality of linear openings arranged substantially in parallel at predetermined intervals on the amorphous silicon film And a catalytic element may be introduced from above the mask film. Thereafter, by performing the lateral crystal growth step after removing the mask film, the catalytic element on the mask film can be prevented from adversely affecting the lateral crystal growth of the amorphous silicon film.

In the present invention, in order to further improve the characteristics of the semiconductor device, the silicon film in the lateral crystal growth region where the active region of the semiconductor device is formed is irradiated with an energy beam such as a laser beam. It is desirable to perform a step of further promoting the crystallinity of the silicon film. The crystalline silicon film crystallized by introducing a catalytic element is composed of columnar crystals, and the inside is in a single crystal state. Therefore, when the crystal grain boundary is processed by irradiation of laser light or strong light, the substrate A high-quality crystalline silicon film close to a single crystal state can be obtained over the entire surface. If this energy beam irradiation step is performed immediately after the crystallization step, there are regions where the catalytic element is localized at a high concentration on the substrate. Re-diffusion or auto doping of the catalytic element may occur. Therefore, the step of irradiating the energy beam to further promote the crystallinity of the silicon film is performed after removing the region where the catalytic element is localized at a high concentration and forming the active region to be a semiconductor element. Is desirable.

[0053]

Embodiments of the present invention will be described below.

In the semiconductor device of the present invention, a catalytic element is introduced into a plurality of linear regions arranged in parallel at predetermined intervals, and laterally crystal-grows from the introduced region to the peripheral region by heat treatment. An active region is formed by utilizing a lateral crystal growth region sandwiched between two adjacent linear regions (catalyst element introduction regions). The reason will be described with reference to FIG.

FIG. 1 is a plan view showing a region where a catalytic element is introduced and a region where a silicon film is crystallized. Here, the introduction region of the catalyst element is at least two or more regions (50 in FIG. 1).
1, 502).

When a plurality of selective introduction regions of the catalyst element are set and the interval between the introduction regions is set to a predetermined distance or less, lateral crystal growth occurs as if attracting.

As shown in FIG. 1A, the regions 501, 5
When the catalyst element is introduced into the catalyst element 02 and subjected to a heat treatment at 550 ° C. to 600 ° C., first, the silicon films in the catalyst element introduction regions 501 and 502 are crystallized, and thereafter, arrows are formed from the regions 501 and 502 to the surrounding regions. Lateral crystal growth occurs in the direction indicated by 507. Here, the region 503 is a lateral crystal growth region from the catalytic element introduction region 501, and the region 5
Reference numeral 04 denotes a lateral crystal growth region from the catalytic element introduction region 502. In the normal case, the lateral crystal growth region 50
As shown in FIG. 1A, the growth shapes of 3, 504 are symmetrical with respect to the catalyst element introduction regions 501, 502.

[0058] However, as shown in FIG. 1 (B), the distance between the catalytic element introduction region 501, 502 (distance) W _S gradually reduced, the growth shape of the lateral crystal growth regions 503 and 504 regions 501 , 502 are not symmetrical, and crystal growth occurs in such a manner as to attract each other.

When the heat treatment is further extended, as shown in FIG. 1C, the lateral crystal growth regions 503 and 5
04 and the crystal growth is stopped. At this time, the inner regions 503a and 504a and the outer regions 503b and 504 in the lateral crystal growth regions 503 and 504 are formed.
b differs in crystallinity. That is, the inner area 503
The crystallinity of a and 504a is much better than the crystallinity of the outer regions 503b and 504b.
a, 504a hardly exist. Also, the inner region 50
In 3a and 504a, the lateral crystal growth is very stable, and the defective growth rate is drastically reduced.

Therefore, in the present invention, as shown in FIG. 1C, two adjacent catalytic element introduction regions 501,
Lateral crystal growth region (inner region) sandwiched between 502
Active region (element region) 5 using 503a and 504a
05 and 506 are formed. As a result, it becomes possible to manufacture a very high-performance semiconductor device at a high yield rate which has been impossible so far.

[0061] In the present invention, the interval (distance) W _S of the linear region (catalytic element introduction region) is a very important parameter. The reason is that in the portion (inner region) sandwiched between the two catalyst element introduction regions as described above,
Asymmetric whether lateral crystal growth occurs as shown in FIG. 1 (B) is because, depending on the distance W _S between the catalytic element introduction region.

[0062] Therefore, in order to obtain the effect of the present invention as described above sufficiently it is to reduce the distance W _S between the linear region, surrounding the introduction region by introducing a catalytic element in the linear region of the sole It is desirable to set the range so that a higher crystal growth rate can be obtained than when a silicon film is grown in a direction substantially parallel to the substrate surface in the region. By setting _WS in such a range, a stable growth state can be obtained in a lateral crystal growth portion sandwiched between two adjacent catalyst element introduction regions, and the crystal can be laterally crystallized from a single introduction region. It has higher crystallinity than the grown silicon film. Therefore, by forming an active region using such a highly crystalline silicon film, a high-performance semiconductor device can be manufactured at a high yield rate.

[0063] More specifically, it is preferable to spacing W _S between the linear region is set to 300μm or less, more preferably 200μm or less. The reason will be described with reference to FIG.

[0064] FIG. 2 is a graph showing the relation between the distance W _S and lateral crystal growth distance between the linear region the catalytic element is introduced. In FIG. 2, the lateral crystal growth distance refers to the distance from the end of the catalytic element introduction region to the crystal growth tip (the boundary between the crystallized region and the amorphous region) after the treatment at a heating temperature of 580 ° C. for 11 hours. Indicates the distance. Therefore, the crystal growth rate can be obtained by dividing the lateral crystal growth distance by 11 hours.

FIG. 2 shows that the crystal growth distance changes abruptly when W _S is around 300 μm. And W
_{When S} is 400 μm or more, the crystal growth distance is a constant value, which coincides with the crystal growth distance from a single (isolated) catalytic element introduction region. That is, the interval W _S between the linear region as a boundary around 300 [mu] m, the crystal growth distance increases gradually with less. Therefore, in the present invention, by setting W _S to 300 μm or less, a higher crystal growth rate can be obtained than in the case where lateral crystal growth is performed from a single (isolated) catalyst element introduction region, and from the single introduction region. Higher crystallinity can be obtained than a silicon film grown in the lateral direction.

Further, according to FIG. 2, W _S is 300 μm
As the distance becomes smaller, the growth distance becomes longer.
Up to 200
It can be seen that the growth distance is almost saturated below μm. Therefore, in consideration of further stabilizing the growth state, it is optimal to select a region that is in a saturation state in a direction in which the growth distance increases. Furthermore, in this case, the greatest improvement in crystallinity is seen as compared with the crystal growth state from the single (isolated) catalyst element introduction region. Therefore, it is optimal to set the distance W _S between the linear regions into which the catalytic element is introduced in the present invention to 200 μm or less. In this case, a high performance thin film semiconductor device having the most excellent characteristic stability is obtained. It can be realized.

[0067] Incidentally, the lower limit of the interval W _S between the linear region in which the catalytic element is introduced depends on the size of the semiconductor device to be produced. For example, if the crystal growth direction is the length direction L _D of the active region, it is necessary to expect a deviation (growth margin) of about ± 10 μm from the center of the growth boundary, so that W _S / 2> L _D + 10 + α. (Μm). In the above formula, α varies depending on the element design, the manufacturing apparatus, and the like, but is considered to be, for example, about 1 μm to 4 μm.

By the way, as described in the subject, it is difficult to introduce a small amount of a catalytic element, and in order to solve this problem, Japanese Patent Application Laid-Open No. 8-148426 discloses a linear method for introducing a catalytic element. The amount of the catalytic element is controlled by the line width of the region. In this technique, the controllability is extremely excellent and the effectiveness is high as compared with the case where the amount of introduction is directly controlled to a very small amount. However, in the present invention, the technique disclosed in this publication alone is not sufficient, and it is necessary to control the concentration of the catalytic element at a higher level. The reason is that in the case where the introduction region of the catalyst element is constituted by a plurality of linear regions (line & space shape) arranged in parallel at a predetermined interval, the lateral direction sandwiched between the two linear regions This is because the concentration of the catalyst element in the active region formed by the crystal growth silicon film cannot be controlled only by the line width of the introduction region. As a result of the inventors' research, the catalytic element concentration in the active region is:
If introduction region of the catalytic element is constituted by a plurality of linear regions arranged in parallel with a predetermined distance (line and space shape), not only the line width W _L of the linear region, between the linear region it was found that also depends on the interval W _S. Thus, by controlling the concentration of the catalytic element in the active region by a distance W _S between the line width W _L and the linear region of the linear region the catalytic element is introduced in the present invention, the crystal growth and device characteristics The concentration of the catalyst element can be set so as to be an optimum value. As a result, not only the excellent effects of the present invention can be obtained, but also the stability and reliability of the semiconductor device characteristics can be improved.

Further, in the present invention, the crystallinity of the laterally crystallized silicon film constituting the active region is superior to that of the conventional silicon film grown laterally from a single catalyst element introduction region. by elements to optimize the spacing W _S between the line width W _L and the linear region of the linear region to be introduced, it is possible to further improve the stability and crystallinity of the crystal growth. In other words, the crystallinity of the lateral crystal growth silicon film formed between the two catalytic element introduction region, depends on the interval W _S between the line width W _L and the linear region of the linear region the catalytic element is introduced By controlling these two parameters in the present invention, the crystallinity of the active region can be controlled to achieve an optimal state.

[0070] Specifically, constituting the catalyst element concentration and an active region in the active region by using two parameters of the interval W _S between the line width W _L and the linear region of the linear region the catalytic element is introduced In order to control the crystallinity of the silicon film, the ratio W
_A method using _S / W _L is exemplified. Preferably W _S / W _L
Is controlled to be 2.5 or more and 40 or less, and more preferably 5 or more and 30 or less. The reason will be described with reference to FIGS.

[0071] Figure 3 is the ratio W _S / W of the line width W _L of the interval W _S and the catalytic element introduction region between the linear region the catalytic element is introduced
₅ is a graph showing the relationship between _L and the concentration of a catalytic element in an active region constituted by a laterally crystal-grown silicon film between the regions into which _L is introduced.

According to FIG. 3, the concentration of the catalytic element remaining in the active region during the lateral crystal growth process is W _S / W _L
Increases rapidly as the value decreases. That is, the catalyst element concentration is increased and the line width W _L of the introduction region becomes large, it tends to increase the distance W _S between the introduction region is smaller. On the other hand, the catalyst element is necessary for crystal growth,
From the viewpoint of the stability and reliability of the characteristics of the semiconductor element, it is desired to reduce the concentration of the catalyst element as much as possible. According to FIG. 3, the concentration of the catalytic element in the active region shows a sharp increasing tendency when the value of W _S / W _L is around 2.5 as a boundary and below. Therefore, when the value of W _S / W _L is 2.5 or less, not only the concentration of the catalyst element becomes extremely high but also the concentration tends to sharply increase. The concentration of the catalyst element therein greatly varies, destabilizing the device characteristics and greatly varying. Therefore, the ratio W _S / W _L of the line width W _L of the interval W _S and the catalytic element introduction region between the linear region the catalytic element is introduced in the present invention is desirably at least 2.5 or more.

Further, it can be seen from FIG. 3 that when the value of W _S / W _L is about 5 or more, the tendency of the catalyst element concentration in the active region to decrease is almost saturated and the value is stable at a constant value. That is, by setting W _S / W _L to a value of 5 or more, the concentration of the catalyst element in the active region is stabilized at an extremely low concentration, is not largely influenced by external process factors, and further improves the device characteristics. Stability and reliability can be improved. Accordingly, in the present invention, the distance W _S between the linear regions into which the catalytic element is introduced is described.
The ratio W _S / W _L of the line width W _L of the catalytic element introduction region and is more preferably 5 or more.

Next, the ratio W _S in FIG. 4 is a line width W _L of the interval W _S and the catalytic element introduction region between the linear region the catalytic element is introduced
And / W _L, which is a graph showing the relationship between the crystallinity of the formed active region by lateral crystal growth silicon film between the introduction region. In FIG. 4, the crystallinity of the active region is obtained by calculating the full width at half maximum of the primary peak waveform of the Raman band corresponding to the phonon peculiar to the semiconductor in the Raman spectrum of the active region obtained by Raman spectroscopy. Was evaluated based on the value. The full width at half maximum of the Raman peak is about 3 cm ^-1 in a single crystal, and the smaller the value, the better the crystallinity. In FIG. 4, the vertical axis indicates the full width at half maximum of the Raman peak.

[0075] According to FIG. 4, the ratio W _S / W _L of the line width W _L of the interval W _S and the catalytic element introduction region between the linear region the catalytic element is introduced, beside between the introduction region It can be seen that there is a correlation between the crystallinity of the active region formed by the directional crystal growth silicon film. That is, in FIG. 4, W _S / W _L
Is about 30 or more, the crystallinity starts to deteriorate (the full width at half maximum of the Raman peak becomes large), and when it is about 40 or more, it rapidly deteriorates. In particular, in the rapidly deteriorated region where the value of W _S / W _L is about 40 or more, sufficient lateral crystal growth has not occurred, and
This is a so-called poor growth state with many residual amorphous components.
When a semiconductor element is manufactured using the silicon film in such a state, not only sufficient performance is not obtained, but also variation between individual elements naturally increases. Therefore, in the present invention, the ratio W _S / W _L of the distance W _S between the linear regions into which the catalyst element is introduced and the line width W _L of the catalyst element introduction region is preferably about 40 or less, more preferably. 30 or less.

[0076] In the present invention, in addition to the ratio W _S / W _L of the line width W _L of the interval W _S and the catalytic element introduction region between the linear region the catalytic element is introduced, the long side of the linear region The length in the direction is also an important parameter.

In the present invention, a silicon film obtained by one-dimensionally growing a crystal in the lateral direction is used as an active region. Does not cause sufficient one-dimensional crystal growth, and the crystal growth spreads in all directions as shown in FIG. This FIG.
In the figure, 901 indicates a catalytic element introduction region, 902 indicates a lateral crystal growth region, 903 indicates an uncrystallized region, and 904 indicates a crystal growth direction. In such a case, the lateral crystal growth region 9
No. 02 is inferior in crystallinity as compared with one-dimensionally grown crystals, and many residual amorphous (uncrystallized) components are observed. Further, since the required amount of the catalyst element also increases, it is necessary to introduce an excessive amount of the catalyst element, which adversely affects the reliability of the semiconductor element. Therefore, in the present invention, as shown in FIG. 5B, the length 907 in the long side direction of the linear region 901 into which the catalyst element is introduced is changed to the linear region 90.
When the silicon film grows from 1 to its peripheral region, the growth tip 905 of the silicon film (the boundary between the crystallized region 902 and the amorphous region 903) is substantially parallel to the long side direction of the linear region 901. It is desirable to set in the range where the portion exists. In other words, in the portion 906 where the crystal growth tip 905 is substantially parallel to the long side direction of the linear region 901, crystal growth in the horizontal direction is performed one-dimensionally, there is almost no remaining amorphous component, Sufficient crystallization can be performed with the amount of the catalyst element. Then, by utilizing the lateral crystal growth region in such a portion 906, an element region of the semiconductor device is formed at a position as shown by 908 in FIG. 5B to obtain a highly reliable semiconductor element. be able to.

Specifically, the length of the linear region into which the catalytic element is introduced in the long side direction is desirably set to 150 μm or more. By setting this length to 150 μm, a portion 906 where the growth tip 905 shown in FIG. 5B is substantially parallel to the linear region 901 is generated at about 20 μm. Considering the element size and the directional stability of the crystal, the element fabrication region needs to have a range of at least this degree. Therefore,
In the present invention, it is desirable that the length in the long side direction of all the linear regions into which the catalytic element is introduced be 150 μm or more.

[0079] Now, the line width of the interval W _S and the catalytic element introduction region between the linear region the catalytic element is introduced in the present invention W _L
Can control the concentration of the catalyst element in the active region of the semiconductor device by the ratio W _S / W _L, and its effectiveness has been described above. However, the actual concentration of the catalyst element in the active region is 1 × 10
^It is desirable that the concentration be controlled to ¹⁷ atoms / cm ³ or less.

The lower the concentration of the catalytic element in the active region, the better, but according to experiments by the present inventors, the concentration of the catalytic element in the active region of the TFT element is 1 × 10 ¹⁷ atoms / s.
It has been confirmed that a semiconductor device having a durability of less than cm ³ can be obtained as a product from the viewpoint of reliability.
Therefore, in the present invention, it is desirable that the concentration of the catalytic element in the active region of the semiconductor device be 1 × 10 ¹⁷ atoms / cm ³ or less. Here, it is desirable that the concentration of the catalytic element be defined by the minimum value obtained by the secondary ion mass spectrometry.
It is about × 10 ¹⁶ atoms / cm ^3, which is about one digit lower than the above control value, so that sufficient density management can be performed.

In the present invention, as a simpler and more reliable means for confirming the concentration of the catalytic element in the active region, the active region is immersed in a selective etching solution of the catalytic element to cause etching damage such as minute holes on the surface. There is a method to confirm whether or not. At this time, it is desirable to control the concentration of the catalyst element in the active region to a low concentration to the extent that etching damage does not occur. The reason is as follows.

The catalytic elements in the active region are not dispersed uniformly but exist locally and gather. Therefore, rather than using a measuring device to totally measure the concentration of a catalytic element in a region corresponding to the spatial resolution, practical information on the catalytic element can be obtained by using the above method.

More specifically, 0.5% of hydrofluoric acid and 0.1% of hydrogen peroxide were used as a selective etching solution for the catalytic element.
The active area is immersed in an aqueous solution containing 5% for about 1 hour. After the treatment, when the surface of the silicon film is observed with an optical microscope, micro holes 14 as shown in FIG. 6 are observed. FIG. 6 is a sketch of the surface of the silicon film obtained by performing the above-described processing after the lateral crystal growth. FIG. 6A shows a state in which the concentration of the catalytic element is not controlled, and FIG. Shows a state in which the low concentration control of the catalyst element concentration is performed. Since the catalytic element is localized at the growth tip and causes crystal growth, the catalyst element has a property of being unevenly distributed in the introduction portion 11, the growth tip and the growth boundary (the portion where the crystallization regions collide) 13, and the point 14 is unevenly distributed. The micropores generated by removing the catalyst element that has been removed by the etching process are shown. The active region is the lateral crystal growth region 1
2 is manufactured.

In FIG. 6A, the introduction part 11 and the growth boundary 13 are shown.
A small amount of fine holes 14 due to a large amount of catalytic elements can be seen in the horizontal crystal growth region 12 where the active region is formed. That is, the amount of the catalyst element enough to make a hole by the above-mentioned etching also exists in the active region.

On the other hand, in FIG. 6B in which the concentration of the catalyst element is controlled to be low according to the present invention, some small holes 14 can be seen at the introduction portion 11 and the growth boundary 13, but the active region is not. No microholes are generated in the formed lateral crystal growth region 12. Accordingly, it can be seen that the active region does not have the amount of the catalyst element enough to form a hole by the above-mentioned etching, and the concentration is extremely low.

When a TFT element is actually manufactured using both of them, the reliability differs greatly. 6A shows a large deterioration in the characteristics of the TFT elements, and the tendency largely varies among the elements, but the one shown in FIG. 6B shows almost no deterioration in the characteristics of all the elements. .

In the present invention, as a method of controlling the crystallinity of the active region, the Raman spectrum of the active region obtained by the Raman spectroscopy includes a method of controlling the primary peak waveform of the Raman band corresponding to the phonon inherent to the semiconductor. There is a method of obtaining the full width at half maximum of the peak. At this time, it is desirable to control the peak full width at half maximum to be 6.5 cm ^-1 or less.

The Raman spectrum clearly reflects the state of lattice vibrations in Si, and the peak width of the above-mentioned peak is widened due to its crystallinity collapse. For example, the Raman peak full width at half maximum of a silicon film formed by a conventional solid phase growth method without using a catalytic element is a value of 7 cm ^-1 or more. Therefore, in the present invention, by controlling the full width at half maximum of the Raman peak of the active region to be 6.5 cm ^-1 or less, it is possible to prevent the normal solid-phase-grown silicon film from being mixed by natural nucleation. . Therefore, it is possible to stably obtain high-quality crystalline silicon in which the lateral crystal growth component due to the catalytic element is dominant, and to stably manufacture a high-performance semiconductor element.

In the present invention, Ni, Co, Pd, P are used as catalyst elements for promoting crystallization of the amorphous silicon film.
t, Cu, Ag, Au, In, Sn, Al, Sb and the like can be used. If one or more of these elements are selected, the effect of promoting crystallization can be obtained in a small amount, so that a sufficient crystal growth state can be obtained and the adverse effect on the semiconductor element can be minimized.

In particular, the most remarkable effect can be obtained when Ni is used. The following can be considered for this reason.

The catalyst element does not act alone, but acts on the crystal growth by bonding to the silicon film to form silicide.
It is considered that the crystal structure at that time acts like a kind of template when the amorphous silicon film is crystallized, and promotes the crystallization of the amorphous silicon film. Ni forms silicide called NiSi ₂ with _two Sis. This NiSi ₂ has a fluorite type crystal structure, and the crystal structure is very similar to the diamond structure of single crystal silicon. In addition, the lattice constant of NiSi ₂ is 5.406 Å, which is close to the lattice constant of 5.430 Å of the diamond structure of crystalline silicon. As described above, NiSi ₂ is considered to be the best as a template for crystallizing an amorphous silicon film, and therefore, it is particularly preferable to use Ni as the catalyst element in the present invention.

The semiconductor device of the present invention can be manufactured as follows.

Before or after the step of forming an amorphous silicon film on a substrate, a plurality of catalytic elements that promote crystallization of the amorphous silicon film are arranged in parallel at predetermined intervals. And a heat treatment is performed to selectively crystallize the amorphous silicon film in the linear region into which the catalytic element has been introduced. Further, the amorphous silicon film is laterally extended from the linear region to the peripheral region (in a direction substantially parallel to the substrate surface).
After crystal growth, an active region to be a semiconductor element is formed by using a laterally crystal-grown silicon film portion sandwiched between two adjacent linear regions.

At this time, the catalyst element may be introduced after the formation of the silicon film or before the formation of the silicon film. Before the formation of the silicon film, a catalyst element is added to the surface of the underlayer.

The features of the present invention are that a catalytic element is selectively introduced into a plurality of linear regions arranged in parallel to grow an amorphous silicon film, and that a catalyst element is formed between two adjacent linear regions. In which the active region of the semiconductor element is formed using the lateral crystal growth silicon film existing in the portion sandwiched between the two.

As described above, the catalyst element introduced 2
The lateral crystal growth region sandwiched between the linear regions has very good crystallinity as compared to the outer lateral crystal growth region, and the residual amorphous component is extremely small. Decreases sharply. Then, by forming the active region of the semiconductor element using the region, it becomes possible to manufacture a very high-performance semiconductor device at a high yield rate which has been impossible until now.

In the present invention, the catalytic element is introduced into a plurality of linear regions arranged in parallel. The catalytic element concentration in the lateral crystal growth region sandwiched between two adjacent linear regions is as follows. It depends on the spacing W _S between the line width W _L and the linear region of the linear region. Therefore, a distance W _S between the line width W _L and the linear region of the linear region, by examining the relationship between the concentration of the catalytic element sandwiched between the linear region of two adjacent lateral crystal growth regions in advance Place in a manufacturing process of an actual semiconductor device, so that the catalytic element concentration in the lateral crystal growth region to be the active region becomes a desired value, the interval W _S between the line width W _L and the linear region of the linear region Is preferably set in advance. This makes it possible to reliably control and manage the concentration of the catalyst element in the active region, thereby greatly improving the stability and reliability of the semiconductor element.

In the present invention, the catalyst element is introduced into a plurality of linear regions arranged in parallel. However, the crystallinity of the lateral crystal growth region sandwiched between two adjacent linear regions has and on the distance W _S between the line width W _L and the linear region of the linear region. Therefore, a distance W _S between the line width W _L and the linear region of the linear region, previously examined the relationship between the crystallinity of sandwiched between the linear region of two adjacent lateral crystal growth regions in advance in actual manufacturing process of a semiconductor device, such crystalline lateral crystal growth region to be the active region has a desired value, and a distance W _S between the line width W _L and the linear region of the linear region It is desirable to set in advance. This makes it possible to reliably control and manage the low concentration of the crystallinity in the active region, thereby greatly improving the stability of the semiconductor element and further improving the performance.

[0099] In the present invention, it is possible to control low concentration of a catalytic element concentration in the active region by a distance W _S between the line width W _L and the linear region of the linear region, this is a very effective This is as described above. Here, a method of controlling the line width of the linear region and the interval between the linear regions by using the following mask film may be used.

After the formation of the amorphous silicon film, a mask film having a plurality of linear openings arranged substantially in parallel at predetermined intervals is provided thereon, and the catalyst element is coated on the mask film from above the mask film. By introducing the catalyst element, a catalytic element is selectively introduced into the amorphous silicon film. Then, after the mask film is removed, a step of performing crystal growth in a direction substantially parallel to the substrate surface from the linear region into which the catalytic element has been introduced to the peripheral region is performed.

Here, in the conventional crystal growth method by selective introduction of a catalyst element, a mask film such as a silicon oxide film is provided on an amorphous silicon film, a predetermined region of the mask film is opened, and the catalyst element is formed on the entire surface of the substrate. And a heat treatment process for crystallization was performed as it was. Although the catalyst element in the opening of the mask film causes crystallization by this heat treatment step, the catalyst element exists on the mask film even in other regions covered by the mask film. The catalytic element on the mask film depends on the heat treatment temperature and time, the thickness and film quality of the mask film, etc., but may diffuse into the mask film and reach the lower silicon film during the heat treatment step. In such a state, not only is it difficult to control the concentration of the catalyst element in the active region according to the present invention, but also a catalyst element that has not contributed to the crystal growth at all is introduced into the active region, It greatly affects the reliability of the device. Therefore, in order to sufficiently bring out the effects of the present invention, after selectively introducing a catalytic element into the amorphous silicon film using a mask film, the mask film is removed to completely remove the catalytic element on the mask film. It is preferable that the heat treatment is performed after the catalytic element is not present in the region other than the selective introduction region of the catalytic element on the substrate to grow the lateral crystal of the amorphous silicon film.

Although the semiconductor device manufactured according to the present invention has a very high performance, the lateral crystal growth region in which the active region of the semiconductor device is formed in order to further improve the driving characteristics such as the mobility. It is desirable to perform a step of irradiating the silicon film with an energy beam such as a laser beam to further promote the crystallinity of the silicon film.

When the crystalline silicon film is irradiated with an energy beam, the crystal grain boundary is intensively treated due to the difference in melting point between the crystalline silicon film and the amorphous silicon film. Here, in a crystalline silicon film formed by a normal solid-phase growth method, the crystal structure is in a twin state, so that the inside of a crystal grain boundary remains as a twin defect even after laser irradiation. On the other hand, the crystalline silicon film crystallized by introducing the catalytic element of the present invention is composed of columnar crystals, and the inside thereof is in a single crystal state, so that the crystal grains are irradiated by laser light or strong light. When the boundary portion is processed, a high-quality crystalline silicon film close to a single crystal state can be obtained over the entire surface of the substrate. Therefore, in the present invention, by performing a step of irradiating the silicon film in the lateral crystal growth region with an energy beam to further promote the crystallinity of the silicon film, the current driving capability such as the mobility of the obtained semiconductor element is obtained. Can be dramatically improved, and a higher-performance semiconductor device can be manufactured.

Here, the step of further stimulating the crystallinity of the silicon film by irradiating the energy beam is carried out in such a manner that the catalytic element is concentrated at a high concentration, such as a selective introduction region of the catalytic element or a region where lateral crystal growth has collided. It is desirable to remove the existing region and form the active region to be a semiconductor element in an island shape. The reason is as follows.

If the above step is performed immediately after the crystallization step, there are regions where the catalytic element is localized at a high concentration on the substrate. This is because element re-diffusion and auto doping occur. In this case, the effect of controlling the concentration of the catalytic element is reduced, and the reliability of the semiconductor element characteristics is reduced. Therefore, in the present invention, the step of further stimulating the crystallinity of the silicon film by irradiating the energy beam was performed by removing a region where the catalytic element was localized at a high concentration to form an active region to be a semiconductor element. It is desirable to do it later.

The energy beam has a wavelength of 500 n.
The use of strong light of m or less is desirable because the absorption coefficient for the silicon film is extremely high, and only the silicon film can be instantaneously heated without thermally damaging the glass substrate. In addition, when laser light is used, it is desirable because it is possible to increase the output by simply heating the silicon film at a melting point of 1414 ° C. In particular, since the excimer laser beam has a large output, the beam size upon irradiating the substrate can be increased, it is easy to cope with a large-area substrate, and the output is relatively stable. Therefore, it is most desirable to use an excimer laser having a wavelength of 400 nm or less as the energy beam.

(Embodiment 1) Embodiment 1 of the present invention will be described below.
Will be described. In the first embodiment, an example in which the present invention is applied to an active matrix substrate for a liquid crystal display device in which a plurality of N-type TFTs (thin film transistors) are provided on a glass substrate will be described.

FIG. 7 is a plan view for explaining the active matrix substrate of Embodiment 1 and a method for manufacturing the same.
FIG. 8 is a sectional view of the TFT portion in FIG. 7 (A) to 7 (E) and FIGS. 8 (A) to 8 (F)
The manufacturing method of the active matrix substrate of the present embodiment is shown in the order of steps. Actually, hundreds of thousands or more N-type TFTs are formed on the active matrix substrate of the present embodiment. However, in FIG. 7, the TFTs are simplified to 12 TFTs of 3 rows × 4 columns. Also, in FIG. 8, the arrangement of the catalyst element introduction portion 100 and the channel and source / drain directions of the TFT is different from the TFT arrangement of FIG. 7 by 90 °, for the sake of easy explanation. Even if the direction of the TFT is actually different by 90 °, the effect of the present invention is not impaired.

As shown in FIGS. 7 (E) and 8 (F),
The active matrix substrate of the first embodiment is an N-type TFT
A plurality of TFTs 121 are provided, and the TFT 121 is formed on a glass substrate 101 via an insulating base film 102 such as a silicon oxide film. On the insulating base film 102, a TFT
An island-shaped crystalline silicon film 103i constituting 121 is formed. The central portion of the crystalline silicon film 103i is a channel region 111, and both side portions are source / drain regions 112 and 113. A gate electrode 109 made of aluminum or the like is provided on the channel region 111 with a gate insulating film 108 interposed therebetween. The surface of the gate electrode 109 has an oxide layer 110
Coated with The entire surface of the TFT 121 is covered with an interlayer insulating film 115, and contact holes 115a are formed in portions of the interlayer insulating film 115 corresponding to the source / drain regions 112 and 113. The source / drain regions 112 and 113 are connected to the electrode wirings 116 and 117 via the contact holes 115a.

In the first embodiment, the channel region 111 and the source / drain regions 112 and 11 of the TFT are provided.
The crystalline silicon film 103i to be 3 is formed by selectively introducing a catalyst element that promotes crystallization of the amorphous silicon film 103 into a plurality of linear regions 100 arranged in parallel at a predetermined interval, and The crystal is grown from the linear region 100 to the peripheral region in the direction 106 parallel to the substrate surface by the processing, and is sandwiched between two adjacent linear regions (catalyst element introduction regions) 100, 100. It consists of a lateral crystal growth region.

The active matrix substrate can be manufactured, for example, as follows.

First, as shown in FIG. 8A, a thickness of 30 mm is formed on a glass substrate 101 by, for example, a sputtering method.
A base film 102 of about 0 nm made of silicon oxide is formed. The base film 102 is provided to prevent impurities from diffusing from the glass substrate 101.

Next, by a low pressure CVD method or a plasma CVD method, the thickness is 25 nm to 100 nm, for example, 50 nm.
Intrinsic (I-type) amorphous silicon film (a-Si film) 103
Is formed.

Subsequently, an insulating thin film such as a silicon oxide film or a silicon nitride film is deposited on the a-Si film 103. This insulating thin film becomes the mask film 104 when a catalyst element described later is introduced. In the first embodiment, the insulating thin film is TEOS (Tetra Ethoxy Ortho S.E.).
A silicon oxide film decomposed and deposited by RF plasma CVD together with oxygen was used as a raw material.
The thickness of the silicon oxide film is desirably 50 nm to 250 nm. If the thickness is smaller than this, the catalytic element diffuses to the lower layer. If the thickness is larger than that, crystal growth cannot be performed well. In the first embodiment, the thickness of the silicon oxide film is set to 150 nm.
And

Thereafter, the insulating thin film on the a-Si film 103 is patterned to form a mask film 104. Through the through holes of the mask film 104, a
-The Si film 103 is exposed. That is, when the state shown in FIG. 8A is viewed from above, the mask film is formed in a plurality of linear regions 100 in which the a-Si films 103 are arranged in parallel at intervals as shown in FIG. It is exposed in a slit shape by the through hole 104, and the other portions are in a masked state.

[0116] TFT121 Here, the ratio W _S / W _L between the distance W _S between the line width W _L and the through hole of the linear through holes serving as a catalyst element introduction region in a later step, to be formed later
Is set in advance so that the crystallinity of the active region 103i and the concentration of the catalytic element in the film are in a desired state. Specific _WS
The value of / W _L, preferably not less 2.5 or more and 40 or less, and more preferably is 5 or more and 30 or less. In the present embodiment, the line width W _L of the slit-shaped through-holes 1
W _S / W _L was set to 15 at 0 μm and the interval W _S between the through holes was set to 150 μm.

Next, as shown in FIG. 8A, a-Si
Nickel 10 is applied to an area 100 where the surface of the film 103 is exposed.
5 so that the ethanol solution in which
Hold. In this embodiment, nickel acetate is used as the solute, and the nickel concentration in the ethanol solution is 10 ppm.
It was made to become.

Subsequently, the solution was applied to the substrate 101 by a spinner.
The substrate 101 is spread evenly on top and dried.
Surface (the surface of the mask film 104 made of silicon oxide and a-
A small amount of nickel 105 is added to the surface of the region 100 where the Si film 103 is exposed. By this step, the region 10
That is, nickel is selectively introduced into the portion of the a-Si film 103 exposed at 0. Then, this is subjected to a pre-annealing treatment in an inert atmosphere, for example, a nitrogen atmosphere at a temperature of 400 ° C. to 550 ° C. for several minutes to 30 minutes. In this embodiment, the heat treatment is performed at 500 ° C. for 10 minutes.

At the time of this pre-annealing, as shown in FIG. 8B, in the region 100, silicidation of nickel 105 added to the surface of the a-Si film 103 or selective crystallization of the silicon film 103 occur. And the above 500
By the pre-annealing at 10 ° C. for 10 minutes, a crystalline silicon film 103 a containing the remaining a-Si component is formed in the region 100. On the other hand, under these annealing conditions, the mask film 10
4 cannot be reached by the mask film 104 and reach the underlying a-Si layer.
In regions other than 0, crystal growth does not occur and the region is left as an a-Si region 103d in an amorphous state.

Thereafter, the silicon oxide film 104 used as the mask film 104 is removed by etching. The etching at this time has a sufficient selectivity with respect to the underlying silicon film 103 as an etchant (etchant).
Was performed by wet etching using buffered hydrofluoric acid (BHF).

Next, the substrate 101 is again subjected to a heat treatment in an inert atmosphere, for example, a nitrogen atmosphere at a temperature of 540 ° C. to 620 ° C. for several hours to several tens of hours. In the present embodiment, as an example, the treatment is performed at 580 ° C. for 5 hours.

By this heat treatment, the region 100 (103a) previously selectively crystallized is sufficiently crystallized.
As shown by an arrow 106 in (C), crystal growth is performed in a lateral direction (a direction parallel to the substrate) from the region 100 to a peripheral region thereof.

Here, as shown in FIG. 7A, in a region sandwiched between the linear regions 100 into which nickel is selectively introduced, a crystalline silicon film 103b formed by lateral crystal growth is formed. The crystalline silicon films 103b grown from different introduction regions collide with each other, and
3e is formed. The outermost linear region 100
Also in the region outside the region, the lateral crystal growth is performed, and the crystalline silicon film 103c is formed. The outer region where the growth does not reach is left as it is as the amorphous silicon film region 103d, and the boundary between the lateral crystal growth silicon film 103c and the amorphous silicon film region 103d becomes the growth tip 103f.

Here, the TFT 121 shown in FIG. 8 is the TFT on the rightmost line on the paper of FIG. 7, and the linear region 100 shown in FIG. 8C is a linear region of the rightmost line. is there. In the linear region shown in FIG. 8C, another linear region 100 exists on the left side of the drawing, but no linear region exists on the right side. Conventionally, the lateral crystal growth regions are not distinguished, but in the present invention, at least two linear regions 10 are formed.
The inner region 103b and the outer region 103c sandwiched between 0 and 100 are distinguished. This is because, as described above, the inner region 103b and the outer region 103c have different crystal states, different crystallinities, and different crystal growth rates.

Crystal growth distance obtained by this heat treatment (crystal growth distance in the direction parallel to the substrate indicated by arrow 106)
Is 75 μm or more, which is the distance between adjacent crystal growths in the inner region 103b, but only 40 μm in the outer region 103c. According to SIMS measurement, the nickel element concentration in the inner region 103b where the active region is formed later is 5 × 10 ¹⁶ atoms / c.
At about m ³ , the value is almost one digit lower than the conventional value, and the low density control was sufficiently performed.

The substrate 101 in this state was immersed in an aqueous solution containing 0.5% of hydrofluoric acid and 0.5% of hydrogen peroxide at room temperature for about 1 hour, and the state of nickel was examined.
Micro-etched holes made of nickel were found in the introduction region 103a and the growth boundaries 103e and 103f, but the presence of nickel was not confirmed at all in the regions 103b and 103c where lateral crystal growth was performed.

Further, an inner region 103b serving as an active region
The crystallinity of the laterally-grown silicon film was evaluated by Raman spectroscopy. The Raman peak full width at half maximum was about 5.5 cm ⁻¹ , indicating that a good crystal state was stably obtained. . Generally, a silicon film formed by a normal solid phase growth method without using nickel has a Raman peak full width at half maximum of about 7 cm ^-1 , and the lateral crystal growth silicon film 103b of the present embodiment is much higher than that. It has crystallinity.

Subsequently, unnecessary portions of the amorphous silicon film 10 are removed.
3 is removed to perform element isolation. By this step, FIG.
As shown in (B), the lateral crystal growth silicon film 103b
Is used to form an island-shaped crystalline silicon film 103i which will later become the active region (source / drain regions 112 and 113 and channel region 11) of the TFT, as shown in FIGS.
The state of (D) is obtained. What is important here is that the silicon film 103i of the active region has two linear regions 100,
This is to use the lateral crystal growth region 103b sandwiched between the 100. That is, the nickel-introduced portion 103a, the growth boundary portion 103e, and the growth tip portion 103f are not used as element regions because high-concentration nickel is localized, as can be seen from the experiment in which the state of nickel was examined. Completely removed. Also, the lateral crystal growth region 103c outside the introduction region is not used at all as the active region. Therefore, the element region 103i is shown in FIG.
The active regions of all the devices are formed using the lateral crystal growth region 103b sandwiched between the nickel-introduced regions 100 on both sides.

Thereafter, the crystalline silicon film 1 serving as an active region is formed.
A silicon oxide film having a thickness of 20 nm to 150 nm, here 100 nm, is formed as the gate insulating film 108 so as to cover 03i. Here, the silicon oxide film is formed by TEOS
(Tetra Ethoxy Ortho Silica
te) as a raw material, and the substrate temperature is 150 ° C.
It was performed by decomposing and depositing at -600 ° C, preferably 300-450 ° C by RF plasma CVD. The silicon oxide film is made of TEOS as a raw material, and the substrate temperature is set to 350 ° C. to 650 ° C., preferably 400 ° C. to 55 ° C. by a reduced pressure CVD method or a normal pressure CVD method together with ozone gas.
It may be formed by processing at 0 ° C. After this film formation, in order to improve the bulk characteristics of the gate insulating film 108 itself and the interface characteristics between the crystalline silicon film and the gate insulating film, at 400 ° C. to 600 ° C. for 30 minutes to 60 minutes in an inert gas atmosphere. Annealing is performed.

Next, as shown in FIG. 8E, an aluminum film having a thickness of 400 nm to 800 nm, for example, 600 nm is formed by a sputtering method. Then, the gate electrode 109 is formed by patterning the aluminum film. As shown in FIG. 7D, the gate electrode 109 simultaneously constitutes the gate bus line 109 in plan view.
Further, the surface of the aluminum electrode is anodized to form an oxide layer 110 on the surface. This anodization was performed in an ethylene glycol solution containing tartaric acid at 1% to 5%, and the voltage was first increased to 220 V at a constant current, and the state was maintained for 1 hour to terminate the treatment. The thickness of the obtained oxide layer 110 was 200 nm. Note that the thickness of the oxide layer 110 is a length that defines the offset gate region in the subsequent ion doping process, so that the length of the offset gate region can be determined in the anodic oxidation process.

Subsequently, an impurity (phosphorus) is implanted into the active region by ion doping using the gate electrode 109 and the surrounding oxide layer 110 as a mask. Phosphine (PH ₃ ) is used as the doping gas, the acceleration voltage is 60 kV to 90 kV, for example, 80 kV, and the dose is 1
× 10 ¹⁵ cm ^-2 to 8 × 10 ¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵
cm ^-2 . By this step, the regions 112 and 113 into which the impurities are implanted later become the source / drain regions of the TFT, and the gate electrode 109 and the surrounding oxide layer 110
The region 111 to which the impurity is not implanted and which is masked later becomes a channel region of the TFT later.

Thereafter, as shown in FIG. 8E, annealing is performed by irradiation with a laser beam 114 to activate the ion-implanted impurities and, at the same time, to crystallize the portion where the crystallinity has deteriorated in the impurity introducing step. Improve sex. At this time, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used as a laser,
Energy density 150mJ / cm ² ~400mJ / c
m ² , preferably 200 mJ / cm ^{2 to} 250 mJ / cm
Irradiation is performed in ² . The N-type impurity (phosphorus) regions 112 and 113 thus formed have a sheet resistance of 200 to 80.
It was 0 Ω / □.

Next, a silicon oxide film or a silicon nitride film having a thickness of about 600 nm is formed as the interlayer insulating film 115.
In the case of using a silicon oxide film, if a silicon oxide film is deposited by a plasma CVD method using TEOS as a raw material and oxygen, or a reduced pressure CVD method or a normal pressure CVD method using ozone and ozone, a step is formed. A good interlayer insulating film having excellent coverage can be obtained. In addition, when a silicon nitride film formed by a plasma CVD method using SiH ₄ and NH ₃ as a source gas is used, hydrogen atoms are supplied to the interface between the active region and the gate insulating film, and the unpaired bond that degrades TFT characteristics is provided. It has the effect of reducing hands.

Next, a contact hole 115a is formed by selectively etching the interlayer insulating film 115, and a source electrode wiring 116 of the TFT is formed by a two-layer film of a metal material, for example, titanium nitride and aluminum. . At this time, the titanium nitride film is provided as a barrier film for preventing aluminum from diffusing into the semiconductor layer. Since the TFT 121 is an element for switching a pixel electrode, a pixel electrode 117 made of a transparent conductive film such as ITO is formed on the other drain electrode 116. Thus, a video signal is supplied through the source bus line 116 shown in FIG. 7E, and necessary charges are written to the gate 117 based on the gate signal of the gate bus line 109.

Finally, at 350 ° C. in a hydrogen atmosphere of 1 atm.
After annealing for 30 minutes, the TFT 1 shown in FIG.
21 is completed. Further, if necessary, the TFT 121
In order to protect the TFT 121, a protective film made of a silicon nitride film or the like may be provided on the TFT 121.

The TFT 121 thus obtained is:
Very high performance with a field effect mobility of about 100 cm ² / Vs and a threshold voltage of about 2.5 V, and hardly any deterioration in characteristics even after repeated measurements or durability tests by bias or temperature stress. The reliability was much higher than the conventional one. In addition, each TF
The performance of T was evenly uniform with the above values, and the non-uniformity of characteristics due to poor lateral growth and the like, which had been seen in the past, was improved, and the production yield was significantly improved. Further, the leakage current in the TFT off region where the catalytic element is particularly problematic is 5 times smaller than the conventional 10 pA to 15 pA.
It could be reduced to about pA.

Further, when the lighting evaluation was actually performed using the active matrix substrate of this embodiment, a high-definition liquid crystal display device having a very low pixel defect and a high contrast ratio was obtained.

In the first embodiment, it is necessary to uniformly manufacture hundreds of thousands to millions of N-type TFTs on a substrate.
Although T has been described, the TFT of this embodiment can be used not only as a driver circuit of an active matrix type liquid crystal display device or as an element constituting a pixel portion, but also as a thin film integrated circuit.
When the TFT of this embodiment is used for a thin film integrated circuit,
A contact hole may be formed also on the gate electrode 109 and a necessary wiring may be provided (Embodiment 2) Hereinafter, Embodiment 2 of the present invention will be described. In the second embodiment, NTFT and PT constituting a peripheral driving circuit and a general thin film integrated circuit in an active matrix type liquid crystal display device are used.
An example in which the present invention is applied to a circuit having a CMOS structure in which an FT is formed complementarily on a glass substrate will be described.

FIG. 9 is a plan view for explaining a manufacturing process of the CMOS structure circuit according to the second embodiment, and FIG. 10 is a cross-sectional view taken along line AA ′ of FIG. FIGS. 10A to 10E show a method of manufacturing a CMOS structure circuit according to the present embodiment in the order of steps.

As shown in FIG. 10E, the second embodiment
In the CMOS structure circuit described above, an N-type TFT 222 and a P-type TFT 223 are formed on a glass substrate 201 via an insulating base film 202 such as a silicon oxide film. On the insulating base film 202, each of the TFTs 222, 223
Island-shaped crystalline silicon film (element region) 203 constituting
n and 203p are formed adjacent to each other. The central portions of the crystalline silicon films 203n and 203p are an N channel region 211n and a P channel region 211p, respectively. N channel region 2 in crystalline silicon film 203n
Both sides of 11n are N-type source / drain regions 212n and 213n of N-type TFT, and both sides of P-channel region 211P in crystalline silicon film 203p are P-type source / drain regions 212p and 21P of P-type TFT.
3p.

On the N channel region 211n and the P channel region 211p, gate electrodes 209n and 209p made of an aluminum film or the like are provided via a gate insulating film 208. The entire surface of the TFTs 222 and 223 is covered with the interlayer insulating film 215.
5, the source / drain region 2 of the N-type TFT 222
Contact holes 215n are formed in portions corresponding to 12n and 213n, and a P-type TFT 22 is formed in the interlayer insulating film 216.
Contact holes 215p are formed in portions corresponding to the third source / drain regions 212p and 213p. The source / drain regions 212n and 213n of the N-type TFT 222 are connected to the electrode wirings 218 and 219 through the contact holes 215n. On the other hand, the source / drain region 212 of the P-type TFT 222
p and 213p are connected to electrode wirings 218 and 219 via a contact hole 215p.

In the second embodiment, the element region 20
3n and 203p are, as shown in FIG. 9, a plurality of linear regions 200n and 200p arranged in parallel at a predetermined interval.
Is selectively introduced with a catalytic element for promoting crystallization of the amorphous silicon film 203, and the linear region 200 is formed by heat treatment.
And its peripheral region in the direction 206 parallel to the substrate surface, and comprises a lateral crystal growth region sandwiched between two linear regions (catalyst element introduction regions) 200n and 200p.

This CMOS circuit can be manufactured, for example, as follows.

First, as shown in FIG. 10A, a base film 202 made of silicon oxide having a thickness of about 300 nm is formed on a glass substrate 201 by, for example, a CVD method or a PVD method.

Next, a 25 n-thick
An intrinsic (I-type) amorphous silicon film (a-Si film) 203 having a thickness of m to 100 nm, for example, 50 nm is formed.

Subsequently, a photoresist resin (photoresist) is applied on the a-Si film 203, and is exposed and developed to form a photoresist mask film 204. The through holes in the mask film 204 expose the a-Si film 203 in a slit shape in the linear region 200n and the linear region 200p. That is, when the state of FIG. 10A is viewed from above, as shown in FIG.
At 0p, the a-Si film 203 is exposed, and the other portions are masked by the mask film 204. As described above, in the present embodiment, it is not necessary to form a special mask film as in the first embodiment, and the selective introduction of the catalytic element can be performed using the photoresist as the mask film.

[0147] TFT22 Here, the ratio W _S / W _L between the distance W _S between the line width W _L and the through hole of the linear through holes serving as a catalyst element introduction region in a later step, to be formed later
The crystallinity of the 2,223 active regions 203n, 203p and the concentration of the catalytic element in the film are set in advance so as to be in a desired state. Specific values of W _S / W _L are 2.5 or more and 4
It is preferably 0 or less, more preferably 5 or more and 3 or more.
0 or less. In the present embodiment, 10 [mu] m line width W _L of the slit-shaped through-holes, spacing W _S between the through-holes
It was set the W _S / W _L to 10 as 100μm.

Further, in this embodiment, as shown in FIG. 9, one TFT is manufactured from one catalyst element introduction region, so that the length of the linear regions 200n and 200p into which the catalyst element is introduced is increased. The length L in the side direction is also an important parameter. The value of L is desirably 150 μm or more. In the present embodiment, it is set to 200 μm in consideration of the size of the TFT (the channel width in FIG. 9).

After the formation of the mask film 204, FIG.
As shown in FIG.
Is deposited in a thin film. In the present embodiment, the thickness of the nickel thin film 205 is controlled to be 1 nm by increasing the distance between the deposition source and the substrate to be larger than usual and reducing the deposition rate. The nickel 2 on the substrate 201 at this time
When the areal density of No. 05 was actually measured, it was 4 × 10 ¹³ atoms
s / cm ² .

Next, as shown in FIG. 10B, by removing the mask film 204, the nickel thin film 205 on the mask film 204 is lifted off, and selectively in the region 200n and the region 200p of the a-Si film 203. This means that a very small amount of nickel 205 has been introduced. Then, the regions 200n and 200p are crystallized by performing an annealing process in an inert atmosphere, for example, at a heating temperature of 550 ° C. for 16 hours.

At this time, in the region 200n and the region 200p, the amorphous silicon film 203 is crystallized in the direction perpendicular to the substrate 201 with nickel added to the surface of the a-Si film 203 as a nucleus, A silicon film 203a is formed. Then, in the peripheral region of the region 200n and the region 200p, as shown by an arrow 206 in FIGS. 9 and 10B, crystal growth is performed from the region 200n and the region 200p in a lateral direction (a direction parallel to the substrate).

As can be seen from FIG. 9, the crystal growth direction 206 is not one-dimensional but diverges in all directions.
Then, the linear region 200 in which nickel is selectively introduced is provided.
In a region sandwiched between n and 200p, a crystalline silicon film 203b formed by lateral crystal growth is formed.
The lateral crystal growth regions 203b grown from 00n and 200p collide with each other to form a crystal grain boundary 203e. Linear region 200 in which nickel is selectively introduced.
n, the lateral crystal growth also occurs outside of 200p, but the crystallinity and crystal state of the lateral crystal growth region 20 are inside.
The crystalline silicon film 203c is inferior to b. Further, the outer region where the growth does not reach remains as the amorphous silicon film region 203d. Conventionally,
In the case of manufacturing a CMOS structure circuit having such an N-type TFT and a P-type TFT in a complementary manner, only one nickel-introduced region is provided between each TFT, and silicon is laterally grown on both sides thereof. Since the active region of the TFT was formed using the film, the favorable crystal state of the inner region could not be used.

In this embodiment, the crystal growth distance (horizontal crystal growth distance on line AA ′ in FIG. 9) is 50 μm or more where adjacent crystal growths collide with each other in the inner horizontal crystal growth region 203b. Has grown only about 30 μm in the lateral crystal growth region 203c. Then, during the growth, that is, inside the lateral crystal growth region 20.
Inner area 203b until 3b hits each other
By observing the state of the growth end, it was confirmed that a portion parallel to the long side direction of the nickel selective introduction regions 200n and 200p was present over about 70 μm. That is, this region is a region where one-dimensional growth is performed, whereas the TFT to be manufactured in this embodiment is
Since the size in the same direction is 50 μm, an active region of a TFT can be manufactured using a portion having good crystallinity.

Further, the nickel element concentration in the inner lateral crystal growth region 203b where the active region is to be formed later is:
According to the SIMS measurement, it was about 5 × 10 ¹⁶ atoms / cm ³ , and the low concentration control was sufficiently performed.

The substrate 201 in this state was immersed in an aqueous solution containing 0.5% of hydrofluoric acid and 0.5% of hydrogen peroxide at room temperature for about 1 hour, and the state of nickel was examined.
Microetched holes made of nickel were found in the introduction region 203a and the growth boundaries 203e and 203f, but no nickel could be confirmed in any of the regions 203b and 203c where lateral crystal growth was performed.

Further, an inner region 203b serving as an active region
The crystallinity of the laterally-grown silicon film was evaluated by Raman spectroscopy. The Raman peak full width at half maximum was about 5.5 cm ⁻¹ , indicating that a good crystal state was stably obtained. .

Thereafter, as shown in FIG. 10C, the active regions (element regions) 203n and 203p of the TFT are formed in a later step.
The crystalline silicon film to be formed is left, and the other region is removed by etching to perform element isolation. At this time, the active region 2
03n and 203p are arranged in plan as shown in FIG. That is, the nickel selective introduction regions 200n and 20n
0p laterally-grown silicon film 203b
To form an island-shaped crystalline silicon film 203 which will later become an active region (source / drain region and channel region) of the TFT.
n and 203p are formed, and the nickel introduction portion 203a, the growth boundary portion 203e, and the growth front end portion 203f are completely removed without using them as active regions. The lateral crystal growth region 203c outside the introduction region is not used at all as the active region.

Next, as shown in FIG. 10C, the crystalline silicon film 203n is
Promotes crystallinity of 203p. Conventionally, laser light irradiation was performed before the element separation step of the silicon film. However, the introduction portion 203 where a large amount of nickel is localized.
a. In order to completely remove the possibility of nickel back diffusion or autodoping from the growth boundaries 203e and 203f and to further exert the excellent effects of the present invention, the element as in this embodiment is required. It is desirable to perform energy beam irradiation after the separation.

The laser light 207 at this time is X
eCl excimer laser (wavelength 308 nm, pulse width 4
0 nsec). The irradiation condition of the laser beam is such that the substrate is heated to 200 ° C. to 450 ° C., for example, 400 ° C. during the irradiation, and the energy density is 200 mJ / cm ^{2 to} 350 mJ /
Irradiation was performed at a density of cm ² , for example, 250 mJ / cm ² . The beam size was formed to be 150 mm × 1 mm long on the surface of the substrate 201, and the beam size was 0.1 mm in the direction perpendicular to the long direction.
Scanning was performed sequentially with a step width of 1 mm. This allows
This means that laser irradiation was performed 10 times in total at any one point of the island-shaped crystalline silicon films 203n and 203p.

Subsequently, a silicon oxide film having a thickness of 100 nm is formed as a gate insulating film 208 so as to cover the crystalline silicon films 203n and 203p serving as the active regions. In the present embodiment, the gate insulating film 208 is formed by TEOS
At a substrate temperature of 350 ° C. together with oxygen,
Decomposition and deposition were performed by the F plasma CVD method. After the film formation, in order to improve the bulk characteristics of the gate insulating film 208 itself and the interface characteristics between the crystalline silicon film and the gate insulating film, the film is heated at 400 ° C. to 600 ° C. for 30 minutes to 60 hours in an inert gas atmosphere.
Anneal treatment was performed.

Thereafter, as shown in FIG. 10D, an aluminum film (containing 0.1 to 2% silicon) having a thickness of 400 nm to 800 nm, for example, 500 nm is formed by a sputtering method, and the aluminum film is patterned. Thus, gate electrodes 209n and 209p are formed.

Next, the gate electrodes 209n and 209n are formed in the active regions 203n and 203p by the ion doping method.
Impurities (phosphorus and boron) are implanted using p as a mask. Phosphine (PH ₃ ) as doping gas
And diborane (B ₂ H ₆ ), and in the former case, the acceleration voltage is 60 kV to 90 kV, for example, 80 kV, and in the latter case, it is 40 kV to 80 kV, for example, 65 kV, and the dose is 1 × 10 ¹⁵ cm ⁻² to 8 ×. 10 ¹⁵ cm ^-2 , eg phosphorus 2
× 10 ¹⁵ cm ^-2 and boron is 5 × 10 ¹⁵ cm ^-2 . By this step, the regions which are masked by the gate electrodes 209n and 209p and are not implanted with impurities become channel regions 211n and 211p of the TFT later. At the time of this doping, selective doping of each element is performed by covering a region where doping is unnecessary with a photoresist. As a result, N-type impurity regions 212n and 213
n and P type impurity regions 212p and 213p are formed,
As shown in FIG. 10D, an N-channel TFT (N-type TFT
FT) and a P-channel TFT (P-type TFT) can be formed.

Thereafter, as shown in FIG. 10D, annealing is performed by irradiation with laser light 214 to activate the ion-implanted impurities. As the laser light 214, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nsec) was used, and the laser light was irradiated at an energy density of 250 mJ / cm ² at two shots per location.

Subsequently, as shown in FIG. 10E, a silicon oxide film having a thickness of 600 nm is formed as an interlayer insulating film 215 by a plasma CVD method, and contact holes 215n and 215p are formed in the silicon oxide film. For example,
The electrode wirings 218, 219 and 220 of the TFT are formed by a two-layer film of titanium nitride and aluminum.

Finally, under a hydrogen atmosphere of 1 atm.
30 ° C. for 30 minutes to obtain an N-channel TFT 2
22 and the P-channel TFT 223 are completed. Further, a protective film made of a silicon nitride film or the like may be provided on the TFTs 222 and 223 for the purpose of protecting the TFTs 222 and 223 as necessary.

The CM of the present embodiment obtained as described above
In the OS structure circuit, the field-effect mobility of each TFT is 150 cm ² / Vs to 1 for the N-channel TFT 222.
80 cm ² / Vs, 100 for P-channel TFT 223
cm ² / Vs~120cm ² / Vs, which is high, and the threshold voltage N
The channel type TFT 222 exhibited very good characteristics of 1.5 V to 2 V, and the P channel type TFT 223 exhibited excellent characteristics of -2 V to -3 V. Moreover, even when a durability test was performed by a bias or a temperature stress, almost no characteristic deterioration was observed, and the reliability was significantly improved as compared with the conventional one. further,
Leakage current in TFT off region is also N channel type TFT2
22 and 5 pA for the P-channel type TFT 223, which were lower than the conventional method. In addition, the non-uniformity of characteristics due to poor crystal growth in the lateral direction and the like was also improved, and the production yield was greatly improved.

Although the second embodiment based on the present invention has been specifically described above, the present invention is not limited to the above-described embodiment, and various modifications based on the technical concept of the present invention are possible. is there.

For example, in the above-described two embodiments, as a method for introducing nickel, a method in which an aqueous solution in which a nickel salt is dissolved is applied to the surface of an amorphous silicon film, or a method in which a nickel thin film is formed by a vapor deposition method. A method of selectively adding a trace amount of nickel to perform crystal growth was employed. However, before the amorphous silicon film is formed, nickel may be selectively introduced into the surface of the base film, and nickel may be diffused from a lower layer of the amorphous silicon film to perform crystal growth. That is, crystal growth may be performed from the upper surface side or the lower surface side of the amorphous silicon film. Various other methods can be used as a method for introducing nickel. For example, as a solvent for dissolving a nickel salt, a method of diffusing an SOG (spin-on-glass) material from a SiO ₂ film as a solvent may be used, a method of forming a thin film by a sputtering method or a plating method, or a method of directly introducing by an ion doping method. Also available. Further, as impurity metal elements that promote crystallization, in addition to nickel, cobalt, palladium, platinum, copper, silver, gold,
The same effect can be obtained by using indium, tin, aluminum, and antimony.

In the second embodiment, as a means for promoting the crystallinity of the crystalline silicon film, a heating method using an excimer laser, which is a pulse laser, is used. However, other lasers (for example, a continuous oscillation Ar laser or the like) are used. ) Can also perform the same processing. Further, a so-called RTA in which the sample is heated to 1000 to 1200 ° C. (temperature of a silicon monitor) in a short time by using infrared light or a flash lamp (strong light equivalent to laser light) instead of laser light to heat the sample. (Rapid thermal annealing) or RTP
A heat treatment called (rapid thermal process) may be used. Further, as an application of the present invention, in addition to the active matrix type substrate for liquid crystal display, for example,
Contact image sensor, thermal head with built-in driver, organic EL (Electro lumines)
An optical writing element or display element with a built-in driver using a light emitting element or the like as a light emitting element, a three-dimensional IC, or the like can be considered. By using the present invention, high performance such as high speed and high resolution of these elements can be realized.

Further, the present invention can be widely applied not only to the MOS transistor described in the above embodiment but also to a whole semiconductor process including a bipolar transistor and an electrostatic induction transistor using a crystalline semiconductor as an element material. .

[0171]

As described above in detail, in the case of the present invention, the active region is formed by utilizing the lateral crystal growth region having good and stable crystallinity formed between two adjacent linear regions. By forming the region, a high-performance semiconductor device can be obtained at a high yield rate.

According to the second aspect of the present invention, the distance W _S between the linear regions is adjusted by introducing a catalytic element into a single linear region and forming a silicon film in the lateral direction from the introduction region to the peripheral region. By setting the crystal growth rate in a range where a higher crystal growth rate can be obtained than in the case of crystal growth, lateral crystal growth is stabilized in a portion sandwiched between two adjacent catalytic element introduction regions, and higher crystallinity is obtained. be able to.

[0173] In particular, as claimed in claim 3, it is desirable to set the interval W _S between the linear region 300μm or less.

[0174] When according to claim 4 of the present invention, it is possible by the distance W _S between the line width W _L and the linear region of the linear region to control the catalytic element concentration in the active region, the crystal growth Stabilization and optimization of device characteristics can be easily performed.

In the case of claim 5 of the present invention,
It is possible to control the crystallinity of the active region by a distance W _S between the linear region the line width W _L and the linear region, it is possible to further improve the stability and crystallinity of the crystal growth.

[0176] In particular, as in claim 6, it is desirable the ratio W _S / W _L between the distance W _S between the line width W _L and the linear region of the linear region to 2.5 or more and 40 or less.

According to the seventh aspect of the present invention, the length of the linear region in the long side direction is set such that when the silicon film grows from the linear region to the peripheral region, the growth tip of the silicon film is formed. By setting an area that is substantially parallel to the long side direction of the linear area and using the lateral crystal growth area in the area to form an active area, a sufficient amount of a small amount of catalytic element can be obtained. By performing crystal growth, a high-performance semiconductor device can be obtained, and the reliability of the semiconductor device can be increased.

In particular, it is desirable to set the length of the linear region into which the catalytic element is introduced in the long side direction to be 150 μm or more.

According to the ninth aspect of the present invention, by controlling the concentration of the catalyst element in the active region to 1 × 10 ¹⁷ atoms / cm ³ or less, a semiconductor device having high reliability and durability as a product is provided. Is obtained.

In the case of the method of manufacturing a semiconductor device according to the present invention, before or after the step of forming an amorphous silicon film on a substrate, a catalyst element for promoting crystallization of the amorphous silicon film is added with a predetermined amount. The amorphous silicon film is selectively introduced into a plurality of linear regions arranged substantially in parallel at intervals, and the amorphous silicon film is laterally crystal-grown from the linear regions to the peripheral regions by heat treatment. Then, an active region to be a semiconductor element is formed using the lateral crystal growth silicon film portion sandwiched between two adjacent linear regions. This makes it possible to manufacture a very high-performance semiconductor device at a high yield rate.

[0181] If according to claim 11 of the present invention, by setting the interval W _S between the line width W _L and the linear region of the linear region in advance, the catalyst of the lateral crystal growth region to be the active region Since the element concentration can be controlled to a desired value, a high-performance and highly reliable semiconductor device can be manufactured with good controllability.

[0182] Also, in the case of claim 12 of the present invention, by setting the interval W _S between the line width W _L and the linear region of the linear region in advance, lateral crystal growth region to be the active region Can be controlled to a desired value, so that a high-performance and highly reliable semiconductor device can be manufactured with good controllability.

According to the thirteenth aspect of the present invention, a mask film having a plurality of linear openings arranged substantially in parallel at predetermined intervals is provided on the amorphous silicon film. By introducing the catalytic element from above, the line width of the linear region and the interval between the linear regions can be controlled.
Thereafter, by performing the lateral crystal growth step after removing the mask film, the catalytic element on the mask film can be prevented from adversely affecting the lateral crystal growth of the amorphous silicon film. A semiconductor device having high performance and high reliability can be manufactured with higher yield.

According to the fourteenth aspect of the present invention, the silicon film in the lateral crystal growth region where the active region of the semiconductor device is formed is irradiated with an energy beam such as a laser beam to reduce the crystallinity of the silicon film. By further promoting, a semiconductor device having more excellent characteristics can be manufactured.

According to the fifteenth aspect of the present invention, an active region serving as a semiconductor element is formed by removing a region where a catalytic element is localized at a high concentration, and then the silicon film is irradiated with an energy beam. By performing a process that further promotes the crystallinity of the catalyst element, re-diffusion and auto-doping of the catalyst element from the region where the catalyst element present on the substrate is localized at a high concentration to the lateral crystal growth region that becomes the active region And the like can be prevented from occurring, and the yield of the semiconductor device can be further improved.

As described above, by using the present invention, a high-performance semiconductor element having stable characteristics with little leakage current can be realized, and a high-performance semiconductor device with a high degree of integration can be obtained by a simple manufacturing process. . In addition, the non-defective rate can be greatly improved in the manufacturing process, and the cost of the product can be reduced.

In particular, in a liquid crystal display device, a pixel switching TFT required for an active matrix substrate
Monolithic type active matrix driver that forms the active matrix section and the peripheral drive circuit section on the same substrate, while simultaneously satisfying the improvement of the switching characteristics of the TFT and the high performance and high integration required for the TFTs constituting the peripheral drive circuit section. This is very effective because a substrate can be realized and the module can be made compact, high-performance, and low in cost.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining an outline of the present invention.

FIG. 2 is a graph showing a relationship between an interval between linear regions into which a catalytic element is introduced and a crystal growth distance in a lateral direction.

FIG. 3 shows an interval between linear regions and a ratio of a line width of the linear regions (W
₅ is a graph showing the relationship between ( _S / W _L ) and the concentration of a catalytic element in an active region.

FIG. 4 shows an interval between linear regions and a ratio of line width of linear regions (W
₅ is a graph showing the relationship between ( _S / W _L ) and Raman peak full width at half maximum.

FIG. 5 is a plan view for explaining the outline of the present invention.

FIG. 6 is a diagram showing a result of confirming a state of existence of a catalyst element.

FIG. 7 is a plan view for explaining the semiconductor device of Embodiment 1 and a method for manufacturing the same.

FIG. 8 is a sectional view illustrating the method of manufacturing the semiconductor device of the first embodiment in the order of steps.

FIG. 9 is a plan view for explaining the method for manufacturing the semiconductor device according to the second embodiment.

FIG. 10 is a sectional view illustrating the method of manufacturing the semiconductor device of the second embodiment in the order of steps;

[Explanation of symbols]

100, 200n, 200p Linear region 101, 201 Glass substrate 102, 202 Base film 103, 203 Amorphous silicon film 103a, 203a Crystalline silicon film (catalyst element introduction region) 103b, 203b Lateral crystal growth region inside 103c, 203c Outside lateral crystal growth region 103d, 203d Amorphous silicon film region 103e, 103f, 203e, 203f Growth boundary portion 103i, 203n, 203p Active region 104, 204 Mask film 105, 205 Catalyst element 106, 206 Crystal Growth direction 108, 208 Gate insulating film 109, 209n, 209p Gate electrode 110 Anodized layer 111, 211n, 211p Channel region 112, 113, 212n, 213n, 212p, 21
3p source / drain region 114, 207, 214 laser light 115, 215 interlayer insulating film 115a, 215n, 215p contact hole 116, 117, 218, 219, 220 electrode / wiring 121 pixel TFT 222 N-channel TFT 223 P-channel TFT

Continued on the front page (72) Inventor Hiromi Sakamoto 22-22 Nagaikecho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation

Claims (15)

[Claims] 1. A semiconductor device having an active region comprising a crystalline silicon film provided on a substrate having an insulating surface, wherein the active region promotes crystallization of an amorphous silicon film. the element is selectively introduced into a plurality of linear regions arranged generally parallel with a predetermined interval W _S, the crystal growth direction generally parallel to the substrate surface by heat treatment from the introduction region to the peripheral region thereof And a semiconductor device formed between two adjacent linear regions. 2. An interval W _S between the linear regions is such that the catalyst element is introduced into a single linear region, and the silicon film is crystallized from the introduction region to the peripheral region in a direction substantially parallel to the substrate surface. The semiconductor device according to claim 1, wherein the semiconductor device is set in a range in which a higher crystal growth rate can be obtained than when the crystal is grown. 3. A distance W _S between the linear region is 300μm
3. The semiconductor device according to claim 2, wherein: Wherein any of the line width W _L and the linear region spacing W _S and by the active region in the catalyst element concentration claims 1 to be controlled 3 of the linear region 13. The semiconductor device according to claim 1. 5. The intervals W claims by the _{S-crystalline} silicon film constituting the active region is controlled 1 to claim 4 between the line width W _L and the linear region of the linear region The semiconductor device according to any one of the above. 6. The claim 4 or claim 5 ratio W _S / W _L is 2.5 or more and 40 or less between the distance W _S between the line width W _L and the linear region of the linear region Semiconductor device. 7. The length of the linear region in the long side direction is such that when the silicon film grows from the linear region to the peripheral region, the growth tip of the silicon film is longer than the linear region. It is set in a range where there is a part that is substantially parallel to the side direction,
7. The semiconductor device according to claim 1, wherein the active region is formed in a portion where a growth tip portion of the silicon film and a long side direction of the linear region are substantially parallel. 8. 8. The length of the linear region in the long side direction is 150.
The semiconductor device according to claim 7, wherein the thickness is set to μm or more. 9. A catalyst element concentration in the active region is 1 × 1.
5. The pressure is controlled to 0 ¹⁷ atoms / cm ³ or less.
3. The semiconductor device according to claim 1. 10. A step of forming an amorphous silicon film on a substrate, and before or after the formation of the amorphous silicon film, a catalyst element for promoting crystallization of the amorphous silicon film is provided at a predetermined interval. Opening _WS and selectively introducing it into a plurality of linear regions arranged substantially in parallel; and heat-treating to selectively crystallize the amorphous silicon film in the linear regions into which the catalytic element has been introduced. A step of continuing the heat treatment to grow crystals in a direction substantially parallel to the substrate surface from a region where the amorphous silicon film is selectively crystallized to a peripheral region thereof; Forming an active region serving as a semiconductor element by using a portion of a crystalline silicon film that is grown in a direction substantially parallel to the substrate and that is sandwiched between two adjacent linear regions; A method for manufacturing a semiconductor device including: 11. A process for selectively introducing the catalyst element in the linear region, by previously setting the intervals W _S between the line width W _L and the linear region of the linear region Controlling the concentration of a catalytic element in the active region.
0. A method for manufacturing a semiconductor device according to item 0. 12. A process for selectively introducing the catalyst element in the linear region, by previously setting the intervals W _S between the line width W _L and the linear region of the linear region The method of manufacturing a semiconductor device according to claim 10, wherein crystallinity of a silicon film constituting the active region is controlled. 13. A mask having the after the step of forming an amorphous silicon film on a substrate, a plurality of linear openings aligned generally parallel with a predetermined distance W _S on amorphous silicon film A step of selectively introducing a catalytic element to the amorphous silicon film by introducing the catalytic element from above the mask film, and removing the mask film to thereby introduce the catalytic element. 13. The method of manufacturing a semiconductor device according to claim 10, wherein a step of growing crystals in a direction substantially parallel to a substrate surface from the linear region to the peripheral region is performed. 14. An energy beam is applied to the crystallized silicon film after performing a step of growing crystals in a direction substantially parallel to the substrate surface from the linear region into which the catalytic element has been introduced to the peripheral region. Irradiating the silicon film to further promote the crystallinity of the silicon film.
The method of manufacturing a semiconductor device according to claim 1. 15. A semiconductor element using a crystalline silicon film grown in a direction substantially parallel to the surface of the substrate and sandwiched between two adjacent linear regions. The method of manufacturing a semiconductor device according to claim 14, wherein after performing the step of forming the active region, a step of irradiating the energy beam to further promote the crystallinity of the silicon film is performed.