JP3496763B2 - Thin film transistor, method of manufacturing the same, and liquid crystal display - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a TFT (thin film transistor) provided on an insulating substrate such as glass and a manufacturing method thereof. In particular, the present invention relates to a semiconductor device that can be used in an active matrix type liquid crystal display device and a manufacturing method thereof.

[0002]

2. Description of the Related Art As a semiconductor device having TFTs on an insulating substrate such as glass, active matrix type liquid crystal display devices and image sensors using these TFTs for driving pixels are known. T used in these devices
A thin film silicon semiconductor is generally used for the FT. The thin film silicon semiconductor is roughly classified into two types, that is, an amorphous silicon semiconductor (a-Si) and a crystalline silicon semiconductor. Amorphous silicon semiconductors are most commonly used because they have a low production temperature, can be produced relatively easily by a vapor phase method, and have high mass productivity. However, since the physical properties such as conductivity are inferior to those of crystalline silicon semiconductors, in order to obtain higher-speed operation characteristics in the future, T containing crystalline silicon semiconductors will be used.
There has been a strong demand for establishment of an FT production method. As the crystalline silicon semiconductor, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystalline component, semi-amorphous silicon having an intermediate state between crystalline and amorphous are known. .

As a method for obtaining these crystalline thin film silicon semiconductors, (1) a crystalline film is directly formed at the time of film formation. (2) An amorphous semiconductor film is formed and crystallized by the energy of laser light. (3) An amorphous semiconductor film is formed and crystallized by applying heat energy.

Methods such as the above are known. However, in the method (1), crystallization progresses at the same time as the film forming step. Therefore, in order to obtain crystalline silicon having a large grain size, it is necessary to increase the thickness of the silicon film, and the film having good semiconductor physical properties. It is technically difficult to form a uniform film over the entire surface of the substrate. Further, since the film forming temperature is as high as 600 ° C. or higher, there is a problem in productivity and cost that an inexpensive glass substrate cannot be used.

Further, in the method (2), since the crystallization phenomenon in the melting and solidifying process is utilized, the grain boundaries are favorably treated with a small grain size, and a high quality crystalline silicon film is obtained. on the other hand,
Taking the most commonly used excimer laser as an example, there is the problem that the irradiation area of the laser beam is small and the throughput is low, and the throughput stability is required to uniformly process the entire surface of a large area substrate. Has a problem that is not enough. The use of laser light is
There is a strong sense of next-generation technology.

The method (3) has an advantage over the methods (1) and (2) in that it can be applied to a large area, but during crystallization, a heat treatment at a high temperature of 600 ° C. or higher for several tens of hours is performed. Is necessary. That is,
Considering the use of an inexpensive glass substrate and the improvement of throughput, it is necessary to simultaneously solve the conflicting problems of lowering the heating temperature and crystallizing in a shorter time. Also,
In the method (3), since the solid-phase crystallization phenomenon is used, the crystal grains spread parallel to the substrate surface and even those having a grain size of several μm appear, but the grown crystal grains collide with each other and form grain boundaries. Therefore, the grain boundaries act as a trap level for carriers, which is a major cause of lowering the mobility of carriers in the TFT.

Therefore, in order to solve all of the above-mentioned various problems, in the above method (3), the temperature required for crystallization can be lowered and the processing time can be shortened. A method for producing a crystalline silicon thin film in which the influence of the above is minimized has been proposed by the applicant of the present application in Japanese Patent Application No. 5-218156. This proposed technology is the technology underlying the present invention and is not the prior art of the present invention.

In this method, by introducing an impurity element such as Ni into the amorphous silicon film as a nucleus for crystal growth, the nucleation rate in the initial stage of crystallization and the subsequent nucleus growth rate are dramatically improved. , 58 like never before thought
A crystalline silicon film having sufficient characteristics can be obtained by heat treatment at a temperature of 0 ° C. or lower for about 4 hours. The mechanism of this crystallization is that the generation of crystal nuclei with the impurity element as a nucleus occurs early in the heating step, and thereafter, the impurity element serves as a catalyst to promote crystallization and the crystal growth rapidly progresses. Hereinafter, these impurity elements are referred to as catalyst elements.

By utilizing this method, a catalytic element is selectively introduced into a part of the substrate to selectively form a crystalline silicon film and an amorphous silicon film in the same substrate as in laser crystallization. Can be formed. Further, if the heat treatment is continued thereafter, the crystal growth portion is laterally (direction parallel to the substrate surface) from the crystallized portion where the catalytic element is selectively introduced to the amorphous portion in the peripheral portion. Phenomenon occurs. In this lateral crystal growth region, needle-like or columnar crystals extend in parallel with the substrate along the growth direction, and there are no crystal grain boundaries in the growth direction. Therefore, a high-performance TFT can be realized by forming the channel portion of the TFT by utilizing this lateral crystal growth region.

Taking a row, a TFT channel portion is formed as shown in FIG. FIG. 16 is a plan view of a TFT using the lateral crystal growth region as seen from the top surface of the substrate. That is, a mask 806 made of a silicon dioxide film or the like is deposited on the amorphous silicon film formed on the entire surface of the substrate, a hole for adding a catalytic element is opened as a catalytic element adding region 800 in the mask 806, and the catalytic element is introduced. To do. Next, when a heat treatment is performed at a temperature of about 550 ° C. for about 4 hours, the amorphous silicon film in the catalytic element addition region 800 is crystallized,
The other part of the amorphous silicon film remains as amorphous silicon. When the heat treatment is further continued for about 8 hours, lateral crystal growth proceeds in the growth direction as indicated by arrow 801 centering on the catalytic element addition region 800, and the lateral crystal growth region 8
02 is formed.

Thereafter, utilizing this lateral crystal growth region 802, a TFT is manufactured according to a conventional method. At this time, the source region 80 is added to the lateral crystal growth region 802.
3, the channel region 804 and the drain region 805 are shown in FIG.
As shown in (A), by arranging them so as to be adjacent to each other along the arrow 801, the direction in which the carriers move and the crystal growth direction 801 are the same direction, and there is no crystal grain boundary in the moving direction of the carriers. A TFT can be realized. In addition, the source region 80 is formed against the lateral crystal growth region 802.
3, the channel region 804 and the drain region 805 are shown in FIG.
As shown in FIG. 6 (B), by providing the arrow 801 adjacently along the vertical direction, the direction in which carriers move and the crystal growth direction 801 intersect and a large number of crystal grain boundaries Will be crossed. As a result, the source-drain resistance increases and mobility decreases, but T
A TFT having a small leak current during the FT-off operation can be obtained.

[0012]

[Patent Document 1] Japanese Patent Application No. 5-21
The technique of 8156 is very effective as described above. On the other hand, to use the above technique, at least T
It is envisioned that a lateral crystal growth distance over the channel region of the FT is required. A region where lateral crystal growth does not reach remains as an amorphous silicon film, so if lateral crystal growth is insufficient, there is a laterally grown crystalline silicon film and an amorphous silicon film in the channel region. Therefore, it is expected that the characteristics of the TFT will be greatly deteriorated. However, in order to obtain a long lateral crystal growth, a heat treatment for a long time is required, which is a major cause of lowering the throughput.

In the above-mentioned Japanese Patent Application No. 5-218156, FIG.
As shown in FIG. 6, the catalytic element is introduced in a rectangular shape. In this method, since the catalytic element added to the amorphous silicon film diffuses in all directions, the lateral crystal growth distance varies depending on the pattern shape and size for adding the catalytic element, as will be shown later. Is expected to occur. A consideration regarding this cause will be described with reference to FIG. In the lateral crystal growth region 902, the catalyst element is directly added, and the catalyst element unevenly distributed at the end of the previously crystallized portion of the range corresponding to the catalyst element addition region 900 is diffused to the surroundings.

For example, the catalyst element addition region 900 is shown in FIG.
In the case of a rectangular shape, the degree of freedom in the lateral crystal growth direction 901 at the corner 906 is theoretically 270 ° C., and the density of the catalytic element is substantially higher than that of the other peripheral portion 907 of the catalytic element addition region 900. It will be small. Therefore, the corner 906
In this case, the lateral crystal growth distance is shorter than that in other portions, and the catalytic element in the peripheral portion is incorporated in the corner portion 906. As a result, the smaller the pattern of the catalyst element added region 900, the shorter the lateral crystal growth distance. In particular, it is assumed that a TFT having a small size such as a pixel switching element on an active matrix substrate cannot obtain a sufficient lateral crystal growth distance.

In the lateral crystal growth, natural nucleation of the a-Si film existing in the growth direction during the crystal growth or impurities such as oxygen, carbon, nitrogen and other metal elements in the a-Si film. Due to the effect of, the phenomenon that the crystal growth direction is branched occurs. If the distance of the lateral crystal growth is increased, the needle-like crystals or columnar crystals that constitute the lateral crystal growth region will have more branches and bends at their tips.
It is assumed that it will be difficult to obtain a high-quality crystalline silicon film in which crystal growth directions are one-dimensionally aligned. Further, as shown in FIG. 17, the corner portion 9 of the catalytic element addition region 900 is
In the vicinity of 06, the crystal growth direction is particularly disturbed for the above-mentioned reason, and the characteristics of the crystal in the other lateral crystal growth regions are greatly affected. In a TFT using a crystalline silicon film, aligning the crystal growth directions is
It is indispensable for improving the performance of the device, and the phenomenon as described above is expected to remain as a major problem.

The present invention has been made to solve the above-mentioned problems of the prior arts (1) to (3), in which a TFT is efficiently formed in a lateral crystal growth region and high carrier mobility is achieved. To provide a semiconductor device capable of forming a TFT having high performance and stable characteristics by realization over the entire surface of a substrate and further shortening a time required for crystallization, and a manufacturing method thereof. To aim.

[0017]

To be more specific, the present invention has the following features.

A semiconductor device of the present invention is a semiconductor device in which a channel region is formed on a substrate having an insulating surface by using a crystalline silicon film, and the channel region is an amorphous silicon film. By selectively introducing a catalyst element that promotes crystallization of the silicon film linearly and performing heat treatment at a predetermined annealing temperature, the substrate surface is formed in the peripheral portion of the linear region where the catalyst element is selectively introduced. der parallel to
Be one that is formed by the crystalline silicon film laterally grown crystal is the minor axis direction of the linear region I, before
In the channel region, the lateral crystal growth distance is constant.
It is characterized in that it is configured by utilizing the following region, thereby achieving the above object.

The semiconductor device of the present invention has a crystalline property.
Substrate with an insulating surface in the channel region using an iodine film
A semiconductor device having the above structure, wherein the channel region
Is a catalyst that promotes crystallization of the amorphous silicon film.
Annealing temperature determined by introducing linearly the medium element selectively
The catalytic element is selectively introduced by heat treatment depending on the temperature.
Parallel to the substrate surface at the periphery of the linear region
The lateral direction from the linear region in the minor axis direction of the linear region
Formed by a crystalline silicon film that has been crystal-grown in the opposite direction
And the channel region is the end of the linear region.
From the longitudinal direction of the linear region to the lateral crystal growth distance.
More than the distance (b) to the area where the distance is constant
It is arranged so that
The above object is achieved.

A method of manufacturing a semiconductor device according to the present invention is performed on a substrate.
The step of forming an amorphous silicon film on the
Later, the catalytic elements that promote crystallization are selectively linearized.
The step of introducing the amorphous silicon film into the amorphous silicon film by heating.
A linear region in which the catalytic element is crystallized and selectively introduced.
In the peripheral part of the area, in a direction approximately parallel to the substrate surface
There is a lateral direction from the linear region in the short axis direction of the linear region.
Direction crystal growth, and the substrate surface
Crystallinity of the region where crystal growth was performed in a direction substantially parallel to the
And a step of forming a thin film transistor with an iodine film.
In the method for manufacturing a conductor device, the thin film transistor
The channel region has a constant lateral crystal growth distance.
It is characterized in that it is formed in the area
The purpose is achieved.

A method of manufacturing a semiconductor device according to the present invention is performed on a substrate.
The step of forming an amorphous silicon film on the
Later, the catalytic elements that promote crystallization are selectively linearized.
The step of introducing the amorphous silicon film into the amorphous silicon film by heating.
A linear region in which the catalytic element is crystallized and selectively introduced.
In the peripheral part of the area, in a direction approximately parallel to the substrate surface
There is a lateral direction from the linear region in the short axis direction of the linear region.
Direction crystal growth, and the substrate surface
Crystallinity of the region where crystal growth was performed in a direction substantially parallel to the
And a step of forming a thin film transistor with an iodine film.
In the method of manufacturing a conductor device, the channel region is
From the end of the linear region in the long axis direction of the linear region,
To the region where the crystal growth distance in the direction is constant
(B) It is characterized in that it is arranged so that
By doing so, the above object is achieved.

In the present invention, the channel region may be formed such that the crystalline silicon is formed so that the number of branches or bends from the one-dimensional crystal direction is 1 or less with respect to the crystal direction. is there.

In the present invention, the channel region may be located within 30 μm from the introduction region of the catalyst element.

The semiconductor device of the present invention is a semiconductor device in which a channel region is formed on a substrate having an insulating surface by using a crystalline silicon film, and the channel region is an amorphous silicon film. By selectively introducing a catalyst element that promotes crystallization of the silicon film linearly and performing heat treatment at a predetermined annealing temperature, the substrate surface is formed in the peripheral portion of the linear region where the catalyst element is selectively introduced. Which is formed by a crystalline silicon film that is crystal-grown in parallel with, in the long axis direction of the linear region into which the catalytic element is introduced, the distance between the channel region and the end of the linear region is The crystalline silicon having a one-dimensional crystallographic direction is formed from the channel region at the annealing temperature, whereby the above object can be achieved.

In the present invention, the distance between the channel region and the end of the linear region in the major axis direction of the linear region into which the catalytic element is introduced may be 30 μm or more. The semiconductor device of the present invention is a semiconductor device in which a channel region is formed on a substrate having an insulating surface by using a crystalline silicon film, and the channel region is an amorphous silicon film. In the peripheral portion of the linear region in which the catalyst element is selectively introduced, the catalyst element that promotes crystallization is selectively introduced in a linear shape, and the crystal is grown parallel to the substrate surface. Which is formed by a crystalline silicon film, and the length of the linear region into which the catalytic element is introduced in the major axis direction is a predetermined length at which the distance that the crystalline silicon grows from the linear region is saturated. The length is set to the above length, whereby the above object can be achieved.

In the present invention, the predetermined length in the major axis direction of the linear region into which the catalytic element is introduced is 120 μm.
It may be more than this.

The semiconductor device of the present invention is a semiconductor device in which a channel region is formed on a substrate having an insulating surface by using a crystalline silicon film, and the channel region is an amorphous silicon film. A catalyst element that promotes crystallization of the silicon film is selectively introduced linearly and heat-treated, in the peripheral portion of the linear region where the catalyst element is selectively introduced,
It is formed by a crystalline silicon film that has been crystal-grown parallel to the substrate surface, and the width in the direction intersecting the major axis direction of the linear region into which the catalytic element is introduced is such that the crystalline silicon is the line. The width is set to be equal to or larger than a predetermined width at which the growth distance from the circular region is saturated, whereby the above object is achieved.

In the present invention, the predetermined width of the linear region into which the catalytic element is introduced may be 5 μm or more.

The semiconductor device of the present invention is a semiconductor device in which a channel region is formed on a substrate having an insulating surface by using a crystalline silicon film, and a crystal of the silicon film is formed on an amorphous silicon film. A catalytic element that promotes the formation of a catalyst is selectively introduced into a linear shape, and by heat treatment, in the peripheral portion of one linear region into which the catalytic element is selectively introduced, the substrate surface is parallel to the substrate surface. A plurality of thin film transistors are provided by utilizing the crystalline silicon film that has been crystal-grown in (1), and thereby the above object can be achieved.

In the present invention, a thin film transistor may be formed on both sides of one linear region into which the catalyst element is introduced.

In the present invention, in the channel region, a catalyst element that promotes crystallization of the silicon film is selectively introduced linearly into the amorphous silicon film, and the catalyst element is selectively heated by heat treatment. In some cases, the crystalline silicon film is formed by irradiating laser light or high-intensity light after crystal growth parallel to the substrate surface in the peripheral portion of the linear region introduced in the above.

In the present invention, the catalytic element is Ni,
Co, Pd, Pt, Cu, Ag, Au, In, Sn, A
One or more kinds of elements selected from 1, P, As, and Sb may be used.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming an amorphous silicon film on a substrate, and before or after the step, a catalytic element that promotes crystallization is selectively linearized. A step of crystallizing the amorphous silicon film by heating and performing crystal growth in a direction substantially parallel to the substrate surface in the peripheral portion of the linear region into which the catalytic element is selectively introduced; And a step of forming a thin film transistor with a crystalline silicon film in a region where crystal growth is performed in a direction substantially parallel to the surface of the substrate, wherein the position of the channel region is the catalytic element. From the introduction region, the annealing temperature is set so as to be within the range where the crystalline silicon film is formed, whereby the above-mentioned object can be achieved.

In the present invention, the channel region may be formed at a position within a distance of 120 μm from the introduction region of the catalyst element.

In the present invention, the channel region is within a range in which the crystalline silicon has a one-dimensional crystal direction, and the crystalline silicon has a one-dimensional crystal direction with respect to the crystal direction. The number of branches or bends from the direction may be formed in a range of 2 or less.

In the present invention, the channel region may be formed at a position within 60 μm from the introduction region of the catalyst element.

In the present invention, the channel region may be formed such that the crystalline silicon is branched or bent from the one-dimensional crystal direction in the crystal direction in a range of 1 or less. .

In the present invention, the channel region may be located within 30 μm from the introduction region of the catalyst element.

In the method for manufacturing a semiconductor device of the present invention, a step of forming an amorphous silicon film on a substrate, and before or after the step, a catalytic element that promotes crystallization is selectively introduced linearly. A step of crystallizing the amorphous silicon film by heating and performing crystal growth in a direction substantially parallel to the substrate surface in the peripheral portion of the linear region into which the catalytic element is selectively introduced; A step of forming a thin film transistor with a crystalline silicon film in a region where crystal growth is performed in a direction substantially parallel to the substrate surface, in a linear region in which the catalytic element is introduced In the long axis direction, the distance between the end of the linear region and the channel region of the thin film transistor in the long axis direction of the linear region is one-dimensionally bonded from the channel region at the annealing temperature. The thin film transistor to be within the scope of crystalline silicon having a direction is formed are the configuration, by its, it is possible to achieve the above object.

In the present invention, the end of the linear region in the major axis direction of the linear region into which the catalytic element is introduced,
The thin film transistor may be configured such that the distance from the channel region of the thin film transistor in the long axis direction of the linear region is 30 μm or more.

In the method for manufacturing a semiconductor device of the present invention, a step of forming an amorphous silicon film on a substrate, and before or after the step, a catalytic element that promotes crystallization is selectively linearly introduced. And a step of crystallizing the amorphous silicon film by heating and performing crystal growth in a direction substantially parallel to the substrate surface in the peripheral portion of the linear region selectively introduced with the catalytic element. And a step of forming a thin film transistor with a crystalline silicon film in a region where crystal growth is performed in a direction substantially parallel to the substrate surface, in a linear region into which the catalytic element is introduced The length in the major axis direction is set to a length equal to or longer than a predetermined length at which the distance that the crystalline silicon grows from the linear region is saturated, whereby the above object is achieved.

In the present invention, the predetermined length in the major axis direction of the linear region into which the catalytic element is introduced is 120 μm.
It may be more than this.

According to the method for manufacturing a semiconductor device of the present invention, a step of forming an amorphous silicon film on a substrate, and before or after the step, a catalyst element that promotes crystallization is selectively linearly introduced. And a step of crystallizing the amorphous silicon film by heating and performing crystal growth in a direction substantially parallel to the substrate surface in the peripheral portion of the linear region selectively introduced with the catalytic element. And a step of forming a thin film transistor with a crystalline silicon film in a region where crystal growth is performed in a direction substantially parallel to the substrate surface, in a linear region into which the catalytic element is introduced The width in the direction intersecting with the major axis direction is set to a width equal to or larger than a predetermined width at which the distance that the crystalline silicon grows from the linear region is saturated, thereby achieving the above object.

In the present invention, the predetermined width of the linear region into which the catalytic element is introduced may be 5 μm or more.

In the method for manufacturing a semiconductor device of the present invention, a step of forming an amorphous silicon film on a substrate, and before or after the step, a catalytic element that promotes crystallization is selectively linearly introduced. And a step of crystallizing the amorphous silicon film by heating and performing crystal growth in a direction substantially parallel to the substrate surface in the peripheral portion of the linear region into which the catalytic element is selectively introduced. And the above-mentioned catalytic element was introduced 1
A step of forming a plurality of thin film transistors with a crystalline silicon film in a region in which crystal growth is performed in a direction substantially parallel to the substrate surface from the linear region of the book, at least, and thereby, The above object can be achieved.

In the present invention, thin film transistors may be formed on both sides of one linear region into which the catalyst element is introduced.

In the present invention, a step of forming an amorphous silicon film on a substrate, and a step of selectively introducing linearly a catalyst element that promotes crystallization before or after the step, A step of crystallizing the amorphous silicon film by heating, and performing crystal growth in a direction substantially parallel to the substrate surface in the peripheral portion of the linear region into which the catalytic element is selectively introduced; Laser light or intense light after the step of promoting crystallinity of the crystalline silicon film in a region where crystal growth is performed in a direction substantially parallel to the substrate surface, and forming a thin film transistor with the silicon film. And the step of performing.

In the present invention, the catalytic element is Ni,
Co, Pd, Pt, Cu, Ag, Au, In, Sn, A
One or more kinds of elements selected from 1, P, As, and Sb may be used.

The operation of the present invention will be described below.

The operation of the semiconductor device and the manufacturing method thereof according to the present invention will be described. At the initial stage of growth, the lateral crystal growth distance L extends in proportion to the annealing time, but of these, the lateral crystal growth distance L saturates at a predetermined lateral growth distance L and no further growth occurs. The reason why there is a limit value for the lateral growth distance L is that the a-Si region in the growth direction grows by spontaneous nucleation, and the lateral crystal growth region collides with a normal crystal growth region to complete the growth. . What is important here is the point at which the lateral crystal growth distance is no longer proportional to the annealing time, at which point the growth starts in the a-Si region, and the normal crystal growth region mixes with the lateral crystal growth region. That is, in the region where the lateral crystal growth distance exceeds the range in which the crystalline silicon film is formed at the annealing temperature from the introduction region of the catalyst element, needle-like crystals or columnar crystals and ordinary solid-phase growth methods are used. Twins are mixed together and the crystallinity is extremely poor. Therefore, by using the crystalline silicon film in the region where the lateral crystal growth distance is within the range where the crystalline silicon film is formed at the annealing temperature from the introduction region of the catalyst element, as an example, the lateral crystal growth distance is Is 1
By forming the channel region of the TFT with a thickness of 20 μm or less, a desired semiconductor device having good characteristics can be obtained.

Further, as the lateral crystal growth distance increases, the number of branches and bends of needle-like crystals or columnar crystals exponentially increases. This is because not only branching and bending due to impurities but also nucleation of the a-Si region in the growth direction contributes as the annealing time increases. As an example, a region in which the average number of branching / bending of needle-like crystals or columnar crystals is 2 or less (for example, a region within a lateral crystal growth distance of 60 μm) is a good crystal in which the growth direction is almost one-dimensionally aligned. In addition, when the average number of branching / bending of needle-like crystals or columnar crystals is 1 or less (horizontal crystal growth distance of 30 μm or less), a near-ideal lateral crystal growth silicon film is obtained. By forming the channel portion of the TFT with a crystalline silicon film having an average number of branching / bending of 2 or less, more preferably 1 or less, TF
It is possible to obtain a TFT having excellent T characteristics, especially mobility. Therefore, as a position forming the channel portion of the TFT, the channel region is arranged within the range where the crystalline silicon film is formed at the annealing temperature from the introduction region of the catalyst element, and more preferably 60 μm or less. Even more optimally, it is even better if it is 30 μm or less.

Further, the operation of another semiconductor device of the present invention and a method of manufacturing the same will be described. In the region where the distance from the end of the catalyst element addition region is outside the range where crystalline silicon having a one-dimensional crystal direction at the annealing temperature is formed from the channel region, the lateral crystal growth distance L is reduced. To be This, as explained earlier,
This is because the crystal growth direction diverges at the corners of the catalyst element addition region, and the catalyst element is consumed in large amounts only at those parts, so that the lateral crystal growth distance L becomes extremely short near the corners. That is, the distance from the end of the catalytic element addition region is
From the channel region, in the lateral crystal growth region outside the range where crystalline silicon having a one-dimensional crystal direction at the annealing temperature is formed, the catalyst element is insufficient,
Due to the influence of the disorder in the crystal growth direction at the end of the catalyst element addition region, one-dimensional lateral crystal growth is not performed.

Therefore, the lateral crystal growth is within a range in which the distance from the end of the catalytic element added region in the Y direction is such that crystalline silicon having a one-dimensional crystallographic direction is formed from the channel region at the annealing temperature. In the region, the lateral crystal growth distance L is stable, and a lateral crystal growth silicon film in which the crystal growth directions are one-dimensionally aligned is obtained. Therefore, the TFT is located at a position such that the distance from the end of the catalyst element addition region in the Y direction is within the range from the channel region where crystalline silicon having a one-dimensional crystal direction is formed at the annealing temperature.
By forming the channel region of, a semiconductor device having better performance and stability than the conventional one can be obtained. T within such a range that crystalline silicon having a one-dimensional crystallographic direction is formed at the annealing temperature from the channel region.
The position where the channel region of the FT is formed is within the range where crystalline silicon having a one-dimensional crystal orientation is formed from the channel region at the annealing temperature, and preferably 30.
It may be at least μm. The present invention can thereby achieve the above object.

Next, the operation of the semiconductor device and the method of manufacturing the same according to another embodiment of the present invention will be described.
The above-mentioned measurement point of the lateral crystal growth distance L is a position near the center in the major axis direction of the catalytic element addition region. When the width of the catalyst element added region in the X direction is a predetermined width such as 40 μm, the length of the linear region into which the catalyst element is introduced in the major axis direction is such that the crystalline silicon is the linear region. It is set to a length equal to or longer than a predetermined length at which the distance to grow from is saturated. At this time, a decrease in the lateral crystal growth distance L is observed. Further, even if the catalyst element addition amount is increased, the change in the lateral crystal growth distance L with respect to the length of the catalyst addition region in the major axis direction is merely shifted in the direction in which the lateral crystal growth distance L is increased, The dependence of the growth distance L on the area of the catalyst element addition region, for example, the length in the major axis direction, does not change.

This is because, as described above, the crystal growth direction diverges at the corners of the catalyst element addition region, and the catalyst element is consumed in large amounts only at those corners. This is because L becomes extremely short. That is, if the length of the catalyst-added region in the major axis direction is less than a predetermined length at which the distance that the crystalline silicon grows from the linear region is saturated, a lateral crystal growth region having a sufficient distance cannot be obtained. . In addition, since the catalytic element is insufficient, it is not possible to obtain a high-quality lateral crystal growth region in which the growth direction is one-dimensionally aligned due to the influence of the disorder of the crystal growth direction at the end of the catalyst element addition region. . Therefore, by setting the length in the major axis direction of the catalytic element addition region to be equal to or longer than the predetermined length at which the distance at which the crystalline silicon grows from the linear region is saturated, a constant lateral crystal growth distance L is obtained. Obtained stably. This makes it possible not only to facilitate the subsequent manufacturing steps, but also to obtain a semiconductor device having excellent characteristics in terms of the lateral crystal growth silicon film in which the crystal growth directions are one-dimensionally aligned.

The length of the catalyst element added region in the major axis direction is preferably 120 μm or more.

Further, the operation of another semiconductor device of the present invention and a method of manufacturing the same will be described. The measurement point of the lateral crystal growth distance L is a position near the center in the long axis direction of the catalyst element addition region, and the length of the catalyst element addition region in the long axis direction (Y direction) is 200 μm as an example. When the width of the catalytic element added region is set to be less than a predetermined width at which the distance that the crystalline silicon grows from the linear region is saturated, the lateral crystal growth distance L decreases. Further, when the width of the catalyst element added region is extremely small, for example, less than 1 μm, lateral crystal growth does not occur. That is, in the case where the width of the catalytic element addition region is set to be less than a predetermined width at which the growth distance from the linear region is saturated, not only a lateral crystal growth region having a sufficient distance cannot be obtained,
The lateral crystal growth distance L also varies greatly and is not practical.

Therefore, when the width of the catalytic element-added region is set to a width equal to or larger than a predetermined width at which the distance that the crystalline silicon grows from the linear region is saturated, a constant lateral crystal growth distance L is obtained. Since it is stably obtained, the subsequent manufacturing process can be easily performed, and a high-performance semiconductor device having excellent uniformity can be obtained. The predetermined width is preferably 5 μm.

Further, the operation of another semiconductor device of the present invention and a method of manufacturing the same will be described. A semiconductor device having a plurality of TFTs on one substrate by forming a plurality of TFTs by a lateral crystal growth silicon film grown from one catalyst element addition region by linearly extending the catalyst element addition region As a result, a semiconductor device having extremely excellent uniformity can be obtained. TFT using crystalline silicon film in channel region
Since the characteristics of (1) are mainly determined by the crystallinity of the crystalline silicon film, a subtle difference in crystallinity appears as a variation in the characteristics of the device.

According to the present invention, a plurality of TFTs are formed on the crystalline silicon film laterally grown from one catalyst element-added region, so that the crystalline silicon films forming the channel regions of the plurality of TFTs are formed. A semiconductor device having similar crystallinity and, as a result, a semiconductor device excellent in uniformity of operation characteristics with little variation in characteristic surface among the plurality of TFTs can be obtained. INDUSTRIAL APPLICABILITY The present invention is particularly effective in the case where tens of thousands of elements are formed on one substrate such as an active matrix substrate of a liquid crystal display device. The characteristics can be greatly reduced to the line-wise variation between the TFT columns in each row direction or each column direction.

Further, according to another semiconductor device of the present invention and a method of manufacturing the same, by using the laterally grown crystalline silicon film on not only one side of the linear catalytic element-added region but also both sides thereof, the device Variation can be halved. Further, by utilizing both sides of this linear catalytic element-added region to fabricate an N-type TFT on one side and a P-type TFT on the other side, CMOS (complementary metal-oxide film-silicon) of stable characteristics can be obtained. A structural transistor) circuit is obtained.

As described above, the present invention is roughly divided into five inventions. In the semiconductor device and the manufacturing method thereof, by irradiating the crystalline silicon film laterally grown by heat treatment with laser light or light with high illuminance, the crystal grain boundary portion of the crystalline silicon film is focused. The carrier trap level density due to the crystal grain boundaries, which is particularly problematic in solid-phase-grown crystalline silicon, can be greatly reduced by the annealing, and the crystallinity can be further improved.

Further, according to another semiconductor device of the present invention and a method for manufacturing the same, a remarkable effect can be obtained even when Ni is used as a catalytic element. Co, Pd, Pt, Cu,
Ag, Au, In, Sn, Al, P, As and Sb can be used. A single element or a plurality of elements selected from these elements have a small amount (about 10 ¹⁸ cm ⁻³ ) of the effect of promoting crystallization, and therefore have no problem on the semiconductor element.

[0064]

BEST MODE FOR CARRYING OUT THE INVENTION The features of the present invention will be described with reference to FIG. FIG. 10 is a plan view of a TFT utilizing a lateral crystal growth region according to the present invention when viewed from the top surface of a substrate. That is, a mask 703 made of a silicon dioxide film or the like is deposited on the amorphous silicon film formed on the entire surface of the substrate, and a hole for adding a catalyst element is formed in the mask 703 as a catalyst element addition region (hereinafter referred to as a region) 700. , Introducing a catalytic element. The amorphous silicon film in the range including the region 700 of the silicon dioxide film is crystallized, lateral crystal growth proceeds around the region 700, and a lateral crystal growth region 701 is formed. A channel region 702 of the transistor is formed using the lateral crystal growth region 701. Each variable a, b, c, d shown in FIG. 10 is an amount indicating the gist of the present invention, as described below.

The features of the semiconductor device and the method of manufacturing the same according to the embodiments of the present invention will be described below. FIG. 11 is a graph showing the annealing time dependency of the lateral crystal growth distance L at the annealing temperature of 580 ° C. with respect to the distance L from the region 700 to the tip of the lateral crystal growth region 701.
From FIG. 11, it can be seen that the lateral crystal growth distance L extends in proportion to the annealing time at the initial stage of growth, but the lateral crystal growth distance L is saturated at the lateral growth distance of about 140 μm, and no further growth occurs. The reason why the limit value of the lateral growth distance L exists is that the a-Si region grows in the growth direction due to spontaneous nucleation, and the lateral crystal growth region collides with a normal crystal growth region of the a-Si region. And the growth ends.

What is important here is the lateral crystal growth distance L.
Is a point that is no longer proportional to the annealing time. From this point, the growth starts in the a-Si region, and the normal crystal growth region is mixed with the lateral crystal growth region 701. That is, as can be seen from FIG. 11, in the region where the lateral crystal growth distance L exceeds 120 μm, needle crystals or columnar crystals are mixed with twin crystals obtained by the usual solid phase growth method, and the crystallinity becomes extremely poor. ing. Therefore,
Utilizing the crystalline silicon film in the region where the lateral crystal growth distance L is 120 μm or less, that is, in FIG.
Channel region 702 side end portion of 00 and the channel region 70
By forming the channel region 702 of the TFT by using the crystalline silicon film in which the distance a between the region 700 of No. 2 and the end on the opposite side is 120 μm or less, a semiconductor device having desired desired characteristics can be obtained. .

FIG. 12 is a graph in which the number of branches or bends in one needle-shaped crystal forming the lateral crystal growth region is plotted on the vertical axis and the horizontal crystal growth distance L is plotted on the horizontal axis. The graph in FIG. 12 shows a TEM (Transmission Elector).
on Microscopy; the number of branches and bends of one needle crystal or columnar crystal is measured by observation, and the data are averaged. In FIG. 12, when the lateral crystal growth distance L increases, the number of branches and bends of the needle-like crystals or columnar crystals exponentially increases not only due to the branching and bends due to impurities but also to the increase of the annealing time. This is because the nuclei generated in the a-Si region in the growth direction come to contribute.

The region in which the average number of branching / bending of needle-like crystals or columnar crystals is 2 or less, specifically, in the region in which the lateral crystal growth distance L is 60 μm or less, as shown in FIG. A region that exhibits good crystallinity that is almost one-dimensionally aligned, and that has an average number of branching / bending of needle-like crystals or columnar crystals of 1 or less, specifically, as shown in FIG. In the region where the growth distance L is within 30 μm, a lateral crystal growth silicon film close to the ideal is obtained.
The channel number 702 of the TFT is a crystalline silicon film having an average number of branching / bending of 2 or less, and more preferably 1 or less.
By configuring the above, a TFT having extremely excellent TFT characteristics, particularly carrier mobility, can be obtained. Therefore, as a position forming the channel portion 702 of the TFT,
The distance a in FIG. 10 is selected from the region 700 within a range where the crystalline silicon film is formed at the annealing temperature,
It is even better if it is preferably 60 μm or less, and most preferably 30 μm or less.

Next, the features of the semiconductor device and the manufacturing method thereof according to another embodiment will be described. Figure 13
11 is a graph showing the lateral crystal growth distance L in the X direction with respect to the position of the distance b along the Y direction from the long-axis direction end of the region 700 in FIG. 10. The graph of FIG. 13 shows data measured after annealing the amorphous silicon film at an annealing temperature of 550 ° C. for 16 hours. FIG.
As can be seen from the above, in the region where the distance b from the end of the region 70 is 30 μm or less, the lateral crystal growth distance L is reduced. This is because, as described earlier with reference to FIG. 17, the crystal growth direction diverges at the corner 906 of the region 900, and the catalytic element is consumed in a large amount only in that part, so that the lateral direction near the corner 906. This is because the crystal growth distance L becomes extremely short.

That is, in FIG. 10, in the lateral crystal growth region 701 in which the distance b from the end of the region 700 is 30 μm or less, the catalytic element is insufficient and the crystal at the end of the region 700 is insufficient. Under the influence of the disorder of the growth direction, one-dimensional lateral crystal growth is not performed. Therefore, in FIG. 10, in the lateral crystal growth region where the distance b from the end of the region 700 in the Y direction is 30 μm or more, the lateral crystal growth distance L is stable and the crystal growth directions are one-dimensionally aligned. A laterally grown silicon film is obtained. Therefore, the TFT is placed at a position such that the distance b from the end of the region 700 in the Y direction is 30 μm or more.
By forming the channel region 702 of, a semiconductor device having higher performance and stability than the conventional one can be obtained.

Next, the features of the semiconductor device and the manufacturing method thereof according to another embodiment will be described. Figure 14
In FIG. 10, the length c of the region 700 in the long axis direction (Y direction)
5 is a graph showing a lateral crystal growth distance L in the X direction with respect to. In FIG. 14, the measurement point of the lateral crystal growth distance L is a position near the center in the major axis direction c of the region 700, and the width d in the X direction of the region 700 is 40 μm.
The graph of FIG. 14 shows data measured after annealing the amorphous silicon film at an annealing temperature of 550 ° C. for 16 hours.

As can be seen from FIG. 14, when the length c in the major axis direction of the region 700 is 120 μm or less, the lateral crystal growth distance L decreases. Further, when the catalyst element addition amount is increased, a characteristic curve k showing the lateral crystal growth distance L is obtained.
Shifts to the characteristic curve j only in the direction in which the lateral crystal growth distance L increases as a whole, and the dependence of the growth distance on the major axis length c of the region 700 does not change. As described above, this is the corner 9 of the area 900 in FIG.
At 06, the crystal growth direction diverges, and the catalytic element is consumed in a large amount only in that portion, so that the lateral crystal growth distance L becomes extremely short in the vicinity of the corner 906. That is, in FIG. 10, when the length c in the major axis direction of the region 700 is 120 μm or less, the lateral crystal growth region 701 having a sufficient lateral growth distance L cannot be obtained.

Further, since the catalytic element is insufficient, it is affected by the disorder of the crystal growth direction at the end portion of the region 700, and the high-quality lateral crystal growth region 701 with the growth direction aligned in one dimension is formed. Can't get Therefore, in FIG. 10, by setting the length c in the major axis direction of the region 700 to be 120 μm or more, a constant lateral crystal growth distance L can be stably obtained. For this reason, not only the subsequent manufacturing process can be facilitated, but also the lateral direction crystal growth silicon film in which the crystal growth directions are one-dimensionally aligned can provide a semiconductor device having excellent characteristics.

Next, the features of the semiconductor device and the manufacturing method thereof according to another embodiment will be described. Figure 15 shows
11 is a graph showing the lateral crystal growth distance L in the X direction with respect to the width d of the short side (X direction) of the region 700 in FIG. 10. In FIG. 15, the measurement point of the lateral crystal growth distance L is a position near the center of the region 700 in the major axis direction c, and the length c in the major axis direction (Y direction) of the region 700 is 200.
μm. The graph of FIG. 15 shows data measured after annealing the amorphous silicon film at an annealing temperature of 550 ° C. for 16 hours.

As can be seen from FIG. 15, in the region where the width d of the region 700 is 5 μm or less, the lateral crystal growth distance L decreases. Furthermore, it was confirmed that lateral crystal growth did not occur when the width d of the region 700 was 1 μm or less. That is, in FIG. 10, when the width d of the region 700 is 5 μm or less, not only the lateral crystal growth region 701 having a sufficient distance cannot be obtained, but also the lateral crystal growth distance L has a large variation, which is not practical. Therefore, in FIG.
By setting the width d of 00 to 5 μm or more, a constant lateral crystal growth distance L can be stably obtained, so that the subsequent manufacturing process can be facilitated, and a high-performance semiconductor device excellent in uniformity is obtained. Is obtained.

Next, the features of the semiconductor device and the manufacturing method thereof according to another embodiment will be described. Area 700
Are linearly extended and a plurality of TFTs are formed from a lateral crystal growth silicon film grown from one region 700, so that a semiconductor device having a plurality of TFTs on one substrate has uniform uniformity. A very good semiconductor device can be obtained. The characteristics of the TFT using the crystalline silicon film in the channel region 702 are mainly determined by the crystallinity of the crystalline silicon film. For this reason, subtle differences in crystallinity appear as variations in device characteristics.

In the present invention, a plurality of TFTs are formed on the crystalline silicon film laterally crystal-grown from one region 700, so that the crystalline silicon films forming the channel regions 702 of the plurality of TFTs are the same. As a result, it is possible to obtain a semiconductor device having excellent uniformity with little variation in the characteristic surface among the plurality of TFTs.

The present invention is particularly effective when tens of thousands of elements are formed on one substrate such as an active matrix substrate of a liquid crystal display device, and it has been point-wise scattered for each individual TFT. Further, the characteristics of the TFT can be greatly reduced to a line variation between the TFT columns in each row direction or each column direction.

Further, in the semiconductor device and the manufacturing method thereof according to another embodiment, by using the laterally grown crystalline silicon films not only on one side of the linear region 700 but also on both sides, the variation of the element is further reduced by half. it can. Further, by utilizing both sides of the linear region 700 to form an N-type TFT on one side and a P-type TFT on the other side, a CMOS circuit having stable characteristics can be obtained.

As described above, the present invention is roughly divided into five inventions. In a method of manufacturing a semiconductor device, a crystalline silicon film laterally grown by heat treatment is irradiated with laser light or high-intensity light so that the crystal grain boundary portion of the crystalline silicon film is focused. The carrier trap level density due to the crystal grain boundaries, which is particularly problematic in solid-phase-grown crystalline silicon, can be greatly reduced by the annealing, and the crystallinity can be further improved.

In the method of manufacturing a semiconductor device, a remarkable effect can be obtained even when Ni is used as a catalyst element. Other types of catalyst element that can be used include Co, Pd, Pt, and Cu. , Ag, Au, I
n, Sn, Al, P, As, and Sb can be used. A single element or a plurality of elements selected from these elements have a small amount (about 10 ¹⁸ cm ⁻³ ) of the effect of promoting crystallization, and therefore have no problem on the semiconductor element.

[Embodiment 1] A semiconductor device and a method of manufacturing the same according to Embodiment 1 of the present invention will be described. In this example, a case where the present invention is used in a step of manufacturing an N-type TFT on a glass substrate will be described. The TFT of this embodiment can be used not only in a driver circuit and a pixel portion of an active matrix type liquid crystal display device but also as a semiconductor element constituting a CPU (central processing unit) on the same glass substrate. it can. It goes without saying that the TFT in which the present invention is applied can be applied not only to the liquid crystal display device but also to a generally-known thin film integrated circuit.

FIG. 1 shows an outline of the manufacturing process of the TFT described in this embodiment, in which TF using a lateral crystal growth region is used.
It is a top view when T is seen from the substrate upper surface. 2 is a cross-sectional view taken along the section line AA ′ of FIG.
The manufacturing process sequentially proceeds in the order of (A) → FIG. 2 (F).

First, a base film 102 made of silicon oxide and having a film thickness of about 200 nm is formed on a glass substrate 101 by, for example, a sputtering method. This silicon oxide film is provided to prevent diffusion of impurities from the glass substrate 101. Next, a film thickness of 25 to 100 n is formed by a low pressure CVD method (chemical vapor deposition method) or a plasma CVD method.
An intrinsic (I-type) amorphous silicon film (a-Si film) 103 having a thickness of, for example, 80 nm is formed.

Next, a mask 104, which is formed of a silicon oxide film or a silicon nitride film, and in which the linear region 100 is formed as a through hole, is provided. In the region 100 of the mask 104, the a-Si film 103 is exposed like a slit. That is, when the state of FIG. 2A is viewed from above, the a-Si film 103 is exposed in a slit shape in the region 100 and the other portion is covered with the mask 104 as shown in FIG. Has become. In FIG. 1, a cross section taken along a cutting plane line AA ′ is shown in FIG.
Corresponding to. In this embodiment, as shown in FIG. 1A, the source region 111, the channel region 110, and the drain region 112 are arranged in this order along the direction perpendicular to the major axis direction of the region 100 to form a TFT. Although prepared, as shown in FIG. 1B, the source region 111 and the channel region 1 are formed.
Even when the 10 and the drain region 112 are sequentially arranged along the direction parallel to the long axis direction of the region 100, a TFT can be produced without any problem by the same method.

After providing the mask 104, FIG.
As shown in, an aqueous solution 105 of nickel salt such as nickel acetate or nickel nitrate is applied to the entire surface of the glass substrate 101, and then dried with a spinner to a uniform film thickness. At this time, the concentration of nickel in the aqueous solution 105 is 5
A suitable range is 0 to 200 ppm, preferably 100 ppm. In the region 100, the deposited Ni ions are a
This means that the trace amount of nickel is selectively added to the portion corresponding to the region 100 of the a-Si film 103, which is in contact with the -Si film 103. Then, this is heated under a hydrogen reducing atmosphere, preferably under a hydrogen reducing atmosphere having a hydrogen partial pressure of 0.1 to 1 atm or under an inert atmosphere (atmospheric pressure) at a heating temperature of 520 to 520. Annealing is performed at 580 ° C. for several hours to several tens hours, for example, at 580 ° C. for 16 hours to crystallize the a-Si film 103.

At this time, in the portion corresponding to the region 100 where the trace amount of nickel was added, the glass substrate 1
01, the a-Si film 103 is crystallized in the direction perpendicular to 01, and a crystalline silicon film 103a is formed. And
In the peripheral region of the region 100, crystal growth is performed in the lateral direction (direction parallel to the substrate) from the region 100 as shown by an arrow 106 in FIG. Is formed. Other a-S
The i film region remains as the a-Si film 103 as it is. In the crystal growth, the lateral crystal growth distance L in the direction parallel to the substrate indicated by arrow 106 is about 140 μm.

After that, the mask 104 is removed, and unnecessary portions of the crystalline silicon film 103b are removed to perform element isolation. At this time, the channel region 110 of the TFT is later separated by a distance a from the catalyst element (Ni in this embodiment) added region 100.
The crystalline silicon film 103b is patterned so that the position is within 120 μm. That is, FIG. 1 (A)
In, the channel region 110 of the TFT is formed by setting the distance a to 120 μm or less. If the value of the distance a is more preferably 60 μm or less, and most preferably 30 μm or less, a better effect can be obtained for the above reason.

In this example, the a-Si film 103 was patterned so that the distance a was 20 μm. In addition, the TF is arranged in the arrangement as shown in FIG.
In constructing T, the channel region 110 of the region 100
The effect of the present invention can be obtained by patterning the crystalline silicon film 103b such that the distance a ′ from the side end to the end of the channel region 110 opposite to the region 100 is 120 μm or less. By the following steps,
2D is obtained by forming an island-shaped crystalline silicon film 103b to be an active region, which includes the source region 111, the drain region 112, and the channel region 110.

Next, a silicon oxide film having a film thickness of 20 to 150 nm, here 100 nm, is formed over the gate insulating film 1 so as to cover the crystalline silicon film 103b which becomes the active region.
The film is formed as 07. For the formation of the silicon oxide film, here, TEOS (Tetra Eth Oxy Silan) is used as a raw material, and the substrate temperature is 150 to 600 ° C., preferably 30 with oxygen.
It was decomposed and deposited at 0 to 450 ° C. by the RF plasma CVD method. Alternatively, TEOS may be formed together with ozone gas by a low pressure CVD method or a normal pressure CVD method at a substrate temperature of 350 to 600 ° C., preferably 400 to 550 ° C. After the film formation, in order to improve the bulk characteristics of the gate insulating film 107 itself and the interface characteristics of the crystalline silicon film 103b / gate insulating film 107, annealing is performed at 400 to 600 ° C. for 30 to 60 minutes in an inert gas atmosphere. It was

Subsequently, by the sputtering method,
Aluminum having a film thickness of 400 to 800 nm, for example 600 nm, is formed. Then, the aluminum film is patterned to form the gate electrode 108. Further, the surface of the gate electrode 108 of aluminum is anodized to form an oxide layer 109 on the surface. This state is shown in Fig. 2 (E).
Equivalent to. The anodization is performed in an ethylene glycol solution containing tartaric acid in an amount of 1 to 5%.
The voltage of the gate electrode 108 is increased to V, and the state is maintained for 1 hour to complete the process. The thickness of the obtained oxide layer 109 is 200 nm. Since the oxide layer 109 has a film thickness for forming an offset gate region in a later ion doping process, the length of the offset gate region described later can be determined in the anodizing process.

Next, an impurity (phosphorus) is implanted into the crystalline silicon film 103b by ion doping using the gate electrode 108 and the oxide layer 109 around it as a mask to form the active region. Phosphine (PH ₃ ) is used as a doping gas, and the acceleration voltage is 60 to
90 kV, for example 80 kV, the doping amount is 1 × 10 ¹⁵ to 8
It is set to x10 ¹⁵ cm ^-2 , for example, 2 x 10 ¹⁵ cm ^-2 . By this step, the crystalline silicon film 10 into which impurities are injected
The regions 111a and 112a of 3b will later become the source / drain regions 111 and 112 of the TFT, respectively.
Region 110a of the crystalline silicon film which is masked by the oxide layer 109 and its surroundings and is not implanted with the impurities.
Will later become the channel region 110 of the TFT.

After that, as shown in FIG. 2E, annealing is performed by laser light irradiation to activate the ion-implanted impurities, and at the same time, crystalline silicon whose crystallinity is deteriorated in the above-mentioned impurity introduction step is used. Improve the crystallinity of the film. At this time, the laser used is a XeC1 excimer laser (wavelength 308 nm, pulse width 40 nse
c), energy density 150-400 mJ / cm
² , preferably 200 to 250 mJ / cm ² of laser light irradiation. N-type impurities (phosphorus) thus formed
The sheet resistance of the regions 111 and 112, which are regions, is 2
It was 00 to 800 Ω / □.

Subsequently, a silicon oxide film or a silicon nitride film having a film thickness of about 600 nm is formed as an interlayer insulating film 113. When a silicon oxide film is used, the step coverage is excellent if TEOS is used as a raw material and the interlayer insulating film 113 is formed by a plasma CVD method using this and oxygen, or a low pressure CVD method using ozone or an atmospheric pressure CVD method. A good interlayer insulating film 113 is obtained. Also, SiH ₄ and NH ₃
If the inter-layer insulation film 113 is formed using a silicon nitride film formed by plasma CVD method using
The source region 111 and the channel region 11 shown in (E)
0 and the active region 11 consisting of the drain region 112
6 / supplying hydrogen atoms to the interface of the gate insulating film 107,
This has the effect of reducing dangling bonds that deteriorate the FT characteristics.

Next, a contact hole 117 is formed in the interlayer insulating film 113, and a multilayer film of a metal material such as titanium nitride and aluminum is patterned to form a source electrode of the TFT and its wiring 114, and a drain electrode. The wiring 115 is formed. Finally, annealing is performed in a hydrogen atmosphere at 1 atm at 350 ° C. for 30 minutes, and then, as shown in FIG.
The TFT 118 shown in (F) is completed.

When the TFT 118 is used as an element for switching a pixel electrode of an active matrix type liquid crystal display element, for example, one of the electrodes 114 and 115 is a transparent conductive film such as ITO (indium tin oxide). Electrodes 114, 11 connected to a pixel electrode composed of
It suffices to input a display signal from any one of the other electrodes of 5. When the TFT 118 is used in a thin film integrated circuit, a contact hole is also formed on the gate electrode 108, and the gate electrode 10 is formed through this contact hole.
Wiring required to be connected with 8 may be provided.

N-type T produced according to the above-mentioned embodiment
FT118 has a field effect mobility of 80 to 120 cm ² / V.
s and a threshold voltage of 2 to 3 V, which is a good characteristic. Further, it solves various problems envisaged in Japanese Patent Application No. 5-218156 by the applicant of the present application.

[Embodiment 2] A semiconductor device and a method of manufacturing the same according to Embodiment 2 of the present invention will be described. In this example, a case where the present invention is used in a process of manufacturing a P-type TFT on a glass substrate will be described.

In the following, FIG. 3 shows the outline of the manufacturing process of the TFT described in this embodiment, and is a plan view of the TFT utilizing the lateral crystal growth region as seen from the upper surface of the substrate. FIG. 4 is a cross-sectional view taken along the section line BB ′ in FIG. 3, and the manufacturing process sequentially proceeds in the order of FIG. 4 (A) → FIG. 4 (F).

First, as shown in FIG. 4A, a silicon oxide or silicon nitride film having a film thickness of about 200 nm, for example, a base film 202 made of a silicon oxide film is formed on a glass substrate 201 by, for example, a sputtering method. To do.
Next, by low pressure CVD method or plasma CVD method,
Intrinsic (I type) with a film thickness of 25 to 100 nm, for example 50 nm
And an amorphous silicon film (a-Si film) 203 is formed.

Next, a mask 204 formed of a silicon oxide film, a silicon nitride film, or the like and having linear regions 200 formed as through holes is provided. The region 200 of the mask 204 exposes the a-Si film 203 in a slit shape. That is, when the state of FIG. 4A is viewed from above, the a-Si film 203 is exposed in a slit shape in the region 200 as shown in FIG. 3, and the other portions are masked. . In FIG. 3, the cross section taken along the cutting plane line BB ′ corresponds to FIG. 4 (E) or FIG. 4 (F). In this embodiment, as shown in FIG. 3A, the source region 211, the channel region 210 and the drain region 212 are replaced by the region 200.
A TFT is manufactured in a state of being arranged in this order along a direction perpendicular to the long axis direction of the source region 211, the channel region 210, and the drain region 212 as shown in FIG. Even in the state where the TFTs are sequentially arranged along the direction parallel to the long axis direction, the TFT can be manufactured by the same method without any problem.

After the mask 204 is provided, FIG.
As shown in FIG.
20 nm, for example 2 nm, nickel silicide film 205 (chemical formula NiSi x, 0.4 ≦ X ≦ 2.5, for example X = 2.
0) is deposited. Then, this is annealed in a hydrogen reducing atmosphere or an inert atmosphere at a heating temperature of 520 to 580 ° C. for several hours to several tens of hours, for example, at 550 ° C. for 16 hours to be crystallized.

At this time, in the portion of the a-Si film 203 corresponding to the region 200 where the trace amount of nickel is added,
Crystallization of the a-Si film 203 occurs in the direction perpendicular to the substrate 201 to form a crystalline silicon film 203a. In the peripheral region of the region 200, crystal growth is performed in the lateral direction (direction parallel to the substrate) from the region 200 as indicated by an arrow 206 in FIG. The film 203b is formed. The other a-Si film regions remain as the a-Si film 203 as they are. In the crystal growth, the lateral crystal growth distance L in the direction parallel to the substrate indicated by arrow 206 is 80.
It is about μm. After that, the mask 204 is removed, an unnecessary portion of the crystalline silicon film 203b is removed, and element isolation is performed.

At this time, in FIG. 3A, from one end portion in the long axis direction of the channel region 210 of the TFT described later,
The crystalline silicon film 203b is patterned so that the distance b to the same side end portion along the long axis direction of the catalyst element (Ni in this embodiment) added region 200 is 30 μm or more. In this example, the crystalline silicon film 203b was patterned so that the distance b was 60 μm.
Further, as shown in FIG. 3B, the source region 211, the channel region 210, and the drain region 212 are replaced by the region 2
When the TFTs are arranged in this order along the direction perpendicular to the major axis direction of 00, crystallization is performed so that the distance b ′ defined similarly to the distance b is 30 μm or more. The effects of the present invention can be obtained by patterning the silicon film 203b.

Through the above steps, the island-shaped crystalline silicon film 203b, which will be the activation region of the TFT source region 211, the channel region 210 and the drain region 212, is formed later, and the state of FIG. obtain.

Next, a silicon oxide film having a film thickness of 20 to 150 nm, here 100 nm, is formed on the gate insulating film 20 so as to cover the crystalline silicon film 203b which becomes the active region.
The film is formed as 7. In this embodiment, the gate insulating film 207
A sputtering method was used as the film forming method. For sputtering, silicon oxide is used as a target, the substrate temperature during sputtering is in the range of 200 to 400 ° C., for example 350 ° C., the sputtering atmosphere is oxygen and argon, and argon / oxygen = 0 to 0.5, for example. 0.
It was set to 1 or less.

Subsequently, by the sputtering method,
An aluminum film having a film thickness of 400 nm is formed. And
The aluminum film is patterned to form the gate electrode 208.
Formed. Then, by ion doping method,
The active electrode is used as a mask to form impurities (bores) in the active region.
Inject. As a doping gas, diborane (B
₂H₆), The acceleration voltage is 40 kV to 80 kV, for example,
65kV, dose amount 1 × 10¹⁵~ 8 × 10¹⁵cm
^-2, For example 5 × 10¹⁵cm^-2And By this process
Each region of the crystalline silicon film 203b in which impurities are injected.
Areas 211a and 212a will be the source regions 21 of the TFT later.
1 and the drain region 212 and becomes the gate electrode 208.
Crystalline silicon film 20 which is masked by the silicon and is not implanted with impurities
The region 210a of 3b will be the channel region 21 of the TFT later.
It becomes 0.

Thereafter, as shown in FIG. 4 (E), annealing is performed by laser light irradiation to activate the ion-implanted impurities, and at the same time, the crystalline silicon whose crystallinity is deteriorated in the above-mentioned impurity introduction step is used. The crystallinity of the portion of the film 203b is improved. At this time, the laser used is
KrF excimer laser (wavelength 248 nm, pulse width 2
0 nsec), energy density 150 to 400 m
Irradiation was performed at J / cm ² , preferably 200 to 250 mJ / cm ² . P-type impurities (boron) thus formed
The sheet resistance of the source region 211 and the drain region 212, which are regions, was 500 to 900 Ω / □.

Subsequently, a silicon oxide film with a thickness of about 600 nm is formed as an interlayer insulating film 213. In the case of using a silicon oxide film, if TEOS is used as a raw material and a silicon oxide film is formed by a plasma CVD method with this and oxygen, or a low pressure CVD method with ozone or a normal pressure CVD method, excellent step coverage is obtained. An interlayer insulating film 213 is obtained.

Next, a contact hole 216 is formed in the interlayer insulating film 213, and a source electrode and its wiring 214 of the TFT and a drain electrode and its wiring 215 are formed by a metal material, for example, a multilayer film of titanium nitride and aluminum.
To form. And finally, 3 in a hydrogen plasma atmosphere
After annealing at 50 ° C. for 30 minutes, T shown in FIG.
Complete FT218.

When the TFT 218 is used as an element for switching a pixel electrode of an active matrix type liquid crystal display element, for example, the electrode 214 or the electrode 2 is used.
One of the electrodes 15 is connected to a pixel electrode made of a transparent conductive film such as ITO, and a display signal is input from the other electrode. Further, when the TFT 218 is used in a thin film integrated circuit, a contact hole may be formed also on the gate electrode 208, and wiring required to be connected to the gate electrode 208 may be provided through the contact hole.

P-type T produced according to the above-mentioned embodiment
The FT exhibited good characteristics such as a field effect mobility of 60 to 80 cm ² / Vs and a threshold voltage of -5 to -8V.

[Embodiment 3] A semiconductor device and a method of manufacturing the same according to a third embodiment of the present invention will be described.

FIG. 5 is a plan view showing the outline of the present embodiment and is a plan view of a TFT utilizing a lateral crystal growth region as seen from the upper surface of the substrate. The source region 311 and the drain region 31 are shown in FIG.
2 and a TF made with a channel region 310
T, catalytic element addition region 300, lateral crystal growth region 30
It is a figure which shows the positional relationship with 3b.

A base film and an a-Si film 303 are formed on the glass substrate by the same steps as those in the first and second embodiments. Next, as a mask 304 for injecting a catalytic element that promotes crystallization of the a-Si film 303, a film thickness of 10 nm to 20 nm
A silicon oxide film is formed with a film thickness of 50 nm in the range of 0 nm. This silicon oxide film is patterned to form a region 3
By etching the portion 00, the a-Si film 303
A region 300, which is a through hole for selectively adding the catalytic element, is formed. At this time, in the area 300,
The length of the side facing the active region of the TFT to be formed later, that is, the distance c that is the length in the major axis direction of the substantially rectangular region 300 shown in FIG. 5 is set to 120 μm or more. .

Thereafter, the mask 304 is used to form a region 300 in which the a-Si film 303 is exposed in a slit shape.
Then, a small amount of an element such as nickel that promotes crystallization is added in the same manner as in the first and second embodiments. Then, the a-Si film 303 is annealed at a heating temperature of 550 ° C. for about 16 hours in an inert atmosphere to be crystallized. Here, the a-Si film 30 in the region 300 is formed.
3, a vertically grown crystalline silicon film 303a formed by crystal growth in a film thickness direction which is a direction perpendicular to the glass substrate surface of the a-Si film 303 is formed.
00, a laterally grown crystalline silicon film 303b is formed by crystal growth in the lateral direction parallel to the glass substrate.
The growth distance L of the laterally grown crystalline silicon film 303b in the direction of arrow 306 is about 80 μm.

When a plurality of regions 300 for adding a catalytic element as described above are present on the substrate, the lateral growth silicon film 303b based on any of the regions 300 has a stable constant lateral direction. The crystal growth distance L is obtained.
After that, the mask 304 is removed, and unnecessary portions of the laterally grown crystalline silicon film 303b are removed to perform element isolation.

Through the above steps, the source region 311, the drain region 312 and the channel region 3 of the TFT will be described later.
Island-like crystalline silicon film 30 serving as an active region
3, and thereafter, the target TFT 313 is completed through the same steps as those in the first and second embodiments.

[Embodiment 4] A semiconductor device and a method of manufacturing the same according to Embodiment 4 of the present invention will be described.

FIG. 6 is a plan view showing the outline of the present embodiment, and is a plan view of a TFT using a lateral crystal growth region as seen from the upper surface of the substrate. The source region 411 and the drain region 41 are shown in FIG.
2, and the TFT manufactured including the channel region 410
FIG. 5 is a diagram showing a positional relationship between a region 400 to which a catalyst element is added and a lateral crystal growth region 403b.

A base film and an a-Si film 403 are formed on the glass substrate by the same steps as those in the first and second embodiments. Next, as a mask 404 for adding a catalytic element that promotes crystallization of the a-Si film 403, a silicon oxide film having a thickness of 10 nm to 200 nm, for example, 20 nm, which has a region 400 for adding the catalytic element as a through hole. Form a film. By patterning this silicon oxide film and etching the region 400, the a-Si film 4 is formed.
A region 400 for selectively adding a catalytic element is formed in 03. At this time, in FIG. 6, the width d along the X direction of the region 400 to which the catalyst element is added is set to be 5 μm or more.

Thereafter, the mask 404 is applied to the region 400 where the a-Si film 403 is exposed in a slit shape,
A small amount of an element such as nickel that promotes crystallization is added. Then, this is heated under an inert atmosphere at a heating temperature of 55.
Crystallize by annealing at 0 ° C. for about 16 hours.
In the region 400, a vertically grown crystalline silicon film 403a is formed by crystal growth along the film thickness direction that is a direction perpendicular to the surface of the glass substrate of the a-Si film, and in the peripheral portion of the region 400, from the region 400, A laterally grown crystalline silicon film 403 which is crystal-grown along a lateral direction which is a direction parallel to the glass substrate.
b (hereinafter, the vertically grown crystalline silicon film 403a and the laterally grown crystalline silicon film 403b may be collectively referred to as reference numeral 403) are formed. Laterally grown crystalline silicon film 40
The growth distance L of 3b in the direction of arrow 406 is about 80 μm. When there are a plurality of regions 400 to which the catalytic element is added as described above on the substrate, a stable constant lateral crystal growth distance L can be obtained in any lateral growth silicon film 403b. To be Then mask 4
04 is removed, an unnecessary portion of the laterally grown crystalline silicon film 403b is removed, and element isolation is performed.

Through the above steps, the source region 41 is formed later.
1, the island-shaped crystalline silicon film 403 which becomes the active region of the TFT 413 having the drain region 412 and the channel region 410 is formed. Thereafter, the target TFT 413 is manufactured through the same steps as those in the first and second embodiments. To do.

[Fifth Embodiment] A fifth embodiment of the semiconductor device and the method for manufacturing the same according to the present invention will be described. In this embodiment, a case where the present invention is used in a process of manufacturing a plurality of TFTs on a glass substrate will be described. The semiconductor device of this embodiment can be used not only in a driver circuit and a pixel portion of an active matrix type liquid crystal display device but also in a thin film integrated circuit. Here, a pixel switching TFT of an active matrix portion in the liquid crystal display device is used.
The case of application to is explained.

FIG. 7 shows an outline of the manufacturing process of the active matrix display portion of the liquid crystal display device described in this embodiment, and is a plan view of the TFT utilizing the lateral crystal growth region as seen from the upper surface of the substrate. . In this embodiment, FIG.
The manufacturing process sequentially proceeds from (A) to FIG. 7 (E). Actually, the active matrix display portion of the liquid crystal display device is configured to include tens of thousands of TFTs or more. In this embodiment, a 3 × 3 active matrix display portion is used for the purpose of briefly explaining the gist of the present invention.

First, a base film made of silicon oxide is formed on a glass substrate, an a-Si film having a film thickness of about 50 nm is formed, and an a-Si film 503 is formed. After that, a mask 504 for selectively adding a catalytic element that promotes crystallization of the a-Si film 503 is provided, and a through hole for selectively adding the catalytic element is formed so that the a-Si film 503 is exposed linearly. A region 500 that is a hole is formed.

After forming the mask 504, a nickel film having a film thickness of 1 nm is formed by a vapor deposition method. Then, this glass substrate is placed in an inert atmosphere, for example, at 550 ° C. for 16 hours.
Anneal for about time to crystallize the a-Si film 503. At this time, in FIG. 7A, in the region 500 where a small amount of nickel is added, crystallization of the a-Si film 503 occurs in the direction perpendicular to the glass substrate surface,
A crystalline silicon film 503a is formed. And area 5
In the peripheral area of 00, as shown by arrow 506, area 5
Crystal growth is carried out in the lateral direction (direction parallel to the substrate) from 00 to form a crystalline silicon film 503b which is laterally crystal grown. The other regions of the a-Si film 503 remain as the a-Si film 503. Then the mask 504
Are removed to obtain the state of FIG.

Next, an unnecessary portion of the crystalline silicon film 503b which has undergone lateral crystal growth is removed to perform element isolation. At this time, as shown in FIG. 7B, a plurality of (three in this embodiment) lateral crystal silicon films 503b formed by lateral crystal growth from one nickel-added region 500 are described in each of the embodiments. The active region 503c is formed. At this time, in FIG. 7B, the distance a described in each of the embodiments is 1
If the active region 503c is formed at a position within 20 μm, the distance b is 30 μm or more, and the width d is 5 μm or more,
As described in each of the above-described embodiments, further favorable effects can be achieved. This active region 503c will be
It is a region that becomes a source region, a channel region, and a drain region of the TFT. FIG. 7B corresponds to a state in which a resist pattern is formed at the time of patterning the a-Si film 503. Then, unnecessary portions of the lateral crystalline silicon film 503b are etched to obtain the state shown in FIG. 7C.

Next, a silicon oxide film having a film thickness of about 120 nm is formed as a gate insulating film so as to cover the active region 503c of the crystalline silicon film 503b, and subsequently,
An aluminum film having a film thickness of about 500 nm is formed. Then, the aluminum film is patterned to form a gate electrode / wiring 508 as shown in FIG. After that, impurities (phosphorus or boron) are implanted into the active region 503c by ion doping using the gate electrode 508 as a mask. Through this step, the regions 511a and 512a into which the impurities are implanted become the source region 511 and the drain region 512 of the TFT 513 later, and the regions 510 masked by the gate electrode 508 and into which the impurities are not implanted.
The a will later become the channel region 510 of the TFT 513.

After that, annealing is performed by laser light irradiation to activate the ion-implanted impurities, and at the same time, the crystallinity of the crystalline silicon film constituting the active region 503c whose crystallinity is deteriorated in the above-described impurity introduction step is formed. Improve.

Then, a silicon oxide film with a film thickness of about 600 nm is formed as an interlayer insulating film. Subsequently, as shown in FIG. 7E, a contact hole is formed in the interlayer insulating film, and a source electrode of the TFT 513, a wiring 514 connected to the source electrode, and a drain electrode are formed by a metal material, for example, a multilayer film of titanium nitride and aluminum. 515 is formed. After that, the electrode 515 is connected to the pixel electrode 516 formed of a transparent conductive film such as ITO and annealed at 350 ° C. for 30 minutes in a hydrogen atmosphere to complete the TFT 513 shown in FIG.

In the active matrix substrate manufactured in this example, since three TFTs 513 are manufactured by the laterally grown crystalline silicon film 503b grown from one region 500, these three TFTs 513 are the same as each other. Will have the following operating characteristics.

Conventionally, when a 3 × 3 active matrix substrate is manufactured by using a TFT using a crystalline silicon film in a channel region, nine TFTs are formed due to the difference in crystallinity of the crystalline silicon film forming each TFT. The operating characteristics varied among the TFTs. On the other hand, in this embodiment, three TFs are used.
To the extent that variations occur between groups that include T513,
The density of variations that may occur can be reduced, and the compensation process required when the variations occur is facilitated.
In an actual active matrix substrate having m × n TFTs, variations in operating characteristics between m × n TFTs are
The density can be reduced due to variations in operating characteristics among the m TFT groups. As a result, for example, the manufacturing process of the active matrix substrate can be simplified. In addition, in this embodiment, the TFT 513 is manufactured by using the laterally grown crystalline silicon film 503b on one side in the width direction of the region 500 of the laterally grown crystalline silicon film 503b grown from the linear region 500. The TFT 5 is formed by utilizing the laterally grown crystalline silicon film 503b on both sides of the region 500 in the width direction.
By manufacturing 13, the variation in characteristics between the TFTs 513 can be further reduced by half.

[Sixth Embodiment] A sixth embodiment of the present invention will be described. In this embodiment, N-type TF is formed on the glass substrate.
A case where the present invention is used in a process of manufacturing a circuit having a CMOS structure in which T and a type PTFT are configured in a complementary type will be described. In this example, regarding the laterally grown crystalline silicon film laterally grown from one region for adding a catalytic element, the laterally grown crystalline silicon films on both sides in the width direction of the one region are N-type. TFT and P-type T
A case of configuring the FT will be described.

FIG. 8 is a plan view showing the outline of the manufacturing process of the TFT described in this embodiment. FIG. 9 is a cross-sectional view taken along the section line CC ′ of FIG. 8. 9 (A) to 9
The manufacturing process sequentially proceeds in the order of (E).

First, as shown in FIG. 9A, a film having a thickness of 1 is formed on a glass substrate 601 by, for example, a sputtering method.
A base film 602 made of silicon oxide having a thickness of about 00 nm is formed. Next, by a low pressure CVD method, a film thickness of 25 to 100 n
An intrinsic (I-type) amorphous silicon film (a-Si film) 603 having a film thickness of 50 nm is formed within the range of m.

Next, a mask 604 formed of a silicon oxide film or a silicon nitride film having a film thickness of about 50 nm is provided. The mask 604 is selectively removed to form a region 600 which serves as an injection port for adding a catalytic element.
Therefore, the a-Si film 603 is exposed linearly through the region 600. That is, when the state of FIG. 9 (A) is viewed from above,
As shown in FIG. 8, the a-Si film 603 is exposed through the region 600 for injecting the catalytic element, and the a-Si film 6 is exposed.
The other portions of 03 are masked.
At this time, in FIG. 8, the length c in the major axis direction of the region 600 is 120 μm or more, and the width d is 5 μm or more.
A region 600 is formed. As a result, a sufficient lateral crystal growth distance L can be obtained in the subsequent process.

After forming the mask 604, an aqueous solution of nickel salt such as nickel acetate or nickel nitrate is applied to the entire surface of the glass substrate 601, and then dried by a spinner to a uniform film thickness. At this time, the nickel concentration in the aqueous solution is appropriately 50 to 200 ppm, preferably 100 ppm. In the region 600, the deposited Ni ions are in contact with the a-Si film 603, which means that the trace amount of nickel was selectively added to the region of the a-Si film 603 corresponding to the region 600. And
This is annealed at 550 ° C. for 16 hours in a hydrogen reducing atmosphere or an inert atmosphere to form an a-Si film 60.
Crystallize 3.

At this time, as shown in FIG. 9B, in the region 600 in which a small amount of nickel has been added, the a-Si film 603 is crystallized in the direction perpendicular to the substrate 601, and crystallized. Silicon film 603a is formed. Then, in the peripheral area of the area 600, in FIG.
As indicated by an arrow 606, crystal growth is performed from the region 600 in a horizontal direction which is a direction parallel to the glass substrate, and a laterally crystal-grown silicon film 603b is formed. The other regions of the a-Si film 603 remain as the a-Si film. Subsequently, the mask 604 is removed and laser light is irradiated to promote the crystallinity of the crystalline silicon film 603b. As the laser light at this time, a XeCl excimer laser (wavelength 308 nm, pulse width 40 nse
c) was used. The irradiation condition of the laser light is that the glass substrate is heated to 200 to 450 ° C., for example, 400 ° C. at the time of irradiation,
Within an energy density range of 200 to 400 mJ / cm ² ,
For example, the irradiation was performed with an energy density of 300 mJ / cm ² .

After that, as shown in FIG.
The crystalline silicon film 603b to be the active regions 603n and 603p including the drain region, the channel region, and the drain region of the FT is left, and the other regions are removed by etching to perform element isolation. At this time, in FIG. 8, by forming the crystalline silicon films 603b to be the activated regions 603n and 603p so that the distance a is 120 μm or less and the distance b is 30 μm or more, the crystal growth direction is one-dimensional. The channel region of the TFT can be formed by the high quality laterally grown crystalline silicon film 603b.

A film thickness of 100 n is formed so as to cover the respective crystalline silicon films 603b to be the active regions 603n and 603p.
A silicon oxide film of m is formed as the gate insulating film 607. In this embodiment, TEOS is used as a material for forming the gate insulating film 607, and the substrate temperature is 350 ° C. together with oxygen.
Then, it was decomposed and deposited by the RF plasma CVD method.

Subsequently, as shown in FIG. 9D, the aluminum (0.1 to 0.1 nm) is formed by the sputtering method to a film thickness of 400 to 800 nm, for example, 600 nm.
Then, the aluminum film is patterned to form gate electrodes 608 and 609.

Next, impurities (phosphorus and boron) are implanted into each active region 603b by ion doping using the gate electrodes 608 and 609 as masks. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) were used as the doping gas, and the acceleration voltage was 60 in the former case.
In the range of ~ 90kV, for example 80kV, in the case of the latter,
In the range of 40 kV to 80 kV, for example, 65 kV, and the dose amount is selected in the range of 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, phosphorus is 2 × 10 ¹⁵ cm ⁻² and boron is 5 × 10 5.
The dose amount is ¹⁵ cm ^-2 .

By this step, the gate electrodes 608, 6
Regions masked by 09 and into which impurities are not implanted will later become channel regions 610 and 611 of the TFTs 620 and 621, respectively. At the time of doping, each element is selectively doped by covering a region where doping is unnecessary with a photoresist. As a result, N-type impurity regions 612 and 613 and P-type impurity regions 614 and 615 are formed, and as shown in FIG.
A T (hereinafter, NTFT) 620 and a P-channel TFT (hereinafter, PTFT) 621 can be formed.

After that, as shown in FIG. 9D, annealing is performed by irradiation with laser light to activate the ion-implanted impurities. As the laser light, a KrF excimer laser (wavelength 248 nm, pulse width 20 nse
Using c), the irradiation conditions of the laser beam were such that the energy density was 250 mJ / cm ² and two shots were irradiated at one location.

Subsequently, as shown in FIG. 9E, the film thickness 6
A silicon oxide film having a thickness of 00 nm is formed as an interlayer insulating film 616 by a plasma CVD method, contact holes 622, 623, 624, and 625 are formed in the film, and a TFT 620 is formed using a metal material such as a multilayer film of titanium nitride and aluminum. , 621 electrodes and wires 617,
618 and 619 are formed. Finally, annealing is performed in a hydrogen plasma atmosphere at 350 ° C. for 30 minutes to remove TF.
Complete T620 and 621.

CMOS manufactured according to the above embodiments
In the semiconductor circuit having the structure, each TFT 6
The field effect mobility of carriers of 20, 621 is NTFT.
620 140-170 cm ² / Vs, PTFT621
Is as high as 100 to 130 cm ² / Vs, and the threshold voltage is NT
FT620 1.5-2V, PTFT621 -2--
It shows a very good characteristic of 3V.

Although the sixth embodiment of the present invention has been specifically described above, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the technical idea of the present invention. is there.

For example, in the above-mentioned six examples,
As a method for introducing nickel, a nickel salt aqueous solution is applied to the surface of the amorphous silicon film, or a nickel silicide thin film or a nickel thin film (which is extremely thin and therefore difficult to observe as a film) is selected. A method was adopted in which a small amount of nickel was added, and the amorphous silicon film was grown from this portion. However, before forming the amorphous silicon film, for example, a method of selectively adding a small amount of nickel to the surface of the base film 102 in FIG. 2 may be used. That is, crystal growth may be performed from the upper surface side or the lower surface side of the amorphous silicon film. Further, as a method of adding nickel, a method of selectively implanting nickel ions into the amorphous silicon film by using an ion doping method may be adopted. In this case, it also has a feature that the concentration of nickel element can be controlled. Further, instead of forming a nickel thin film, a small amount of nickel may be added by plasma treatment using a Ni electrode. Further, as an impurity metal element that promotes crystallization of amorphous silicon, cobalt, palladium, platinum, copper, silver, gold, indium, tin, aluminum, phosphorus, arsenic, and antimony may be used in addition to nickel. The effect is obtained.

Further, in each of the above-mentioned embodiments, the heating method by excimer laser irradiation which is a pulse laser is used as a means for promoting the crystallinity of the crystalline silicon film, but other lasers (for example, continuous wave Ar laser, etc.) are used. ), The same processing is possible. Also, instead of laser light, infrared light or flash lamp can be used for 900 ~
So-called RT that heats the sample by raising it to 1200 ° C
Light with high illuminance equivalent to so-called laser light such as A (rapid thermal annealing) (RTP, also called rapid thermal process) may be used.

Further, as an application of the present invention, in addition to the active matrix type substrate for liquid crystal display, for example, a contact type image sensor, a driver built-in thermal head, an organic EL (electroluminescence element), etc. are used as light emitting elements. It is possible to use a driver-embedded writing element, display element, three-dimensional IC (integrated circuit), or the like. By using the present invention, high performance such as high speed and high resolution of these elements can be realized. Furthermore, the present invention is not limited to the MOS type transistors described in the above embodiments, but can be widely applied to a wide variety of semiconductor processes including bipolar transistors and static induction transistors using crystalline semiconductors as element materials.

[0152]

Industrial Applicability By using the present invention, in a semiconductor device and a method for manufacturing the same in which a thin film transistor is formed by using a crystalline silicon film that has been crystal-grown parallel to the substrate, the manufacturing process is simplified, and a large area substrate is obtained. A semiconductor device having a high-performance thin film transistor having uniform and stable characteristics over the entire area can be obtained. Particularly in a liquid crystal display device, the characteristics of the pixel switching TFT required for the active matrix substrate and the high performance required for the TFTs forming the peripheral drive circuit section are simultaneously satisfied, and the active matrix section is formed on the same substrate. A driver monolithic active matrix substrate that constitutes a peripheral drive circuit section can be realized, and the module can be made compact, high performance, and low cost.

[Brief description of drawings]

FIG. 1 is a plan view of a TFT using a lateral crystal growth region according to a first embodiment of the present invention when viewed from the top surface of a substrate.

FIG. 2 is a cross-sectional view taken along the line AA ′ in FIG. 1 showing the manufacturing process of the first embodiment.

FIG. 3 is a plan view of a TFT utilizing a lateral crystal growth region in a second embodiment as seen from the top surface of a substrate.

FIG. 4 is a cross-sectional view taken along the line BB ′ in FIG. 3 showing the manufacturing process of the second embodiment.

FIG. 5 is a plan view of a TFT using a lateral crystal growth region in a third embodiment as seen from the top surface of a substrate.

FIG. 6 is a plan view of a TFT using a lateral crystal growth region in a fourth embodiment as seen from the top surface of a substrate.

FIG. 7 is a plan view of a TFT using a lateral crystal growth region in a fifth embodiment as seen from the top surface of a substrate.

FIG. 8 is a plan view of a TFT utilizing a lateral crystal growth region in a sixth embodiment as seen from the top surface of a substrate.

9 is a cross-sectional view taken along the section line CC ′ of FIG.

FIG. 10 is a plan view of a TFT using a lateral crystal growth region according to the present invention when viewed from the top surface of a substrate.

FIG. 11 is a graph showing the annealing time dependence of the lateral crystal growth distance L with respect to the annealing time in the present invention.

FIG. 12 is a graph of lateral crystal growth distance L against the number of branches or bends in one needle crystal in the present invention.

FIG. 13 is a graph showing a lateral crystal growth distance L at a distance b in the present invention.

FIG. 14 is a graph showing the lateral crystal growth distance L in the X direction with respect to the length c in the present invention.

FIG. 15 is a graph showing the lateral crystal growth distance L in the X direction with respect to the width d in the present invention.

FIG. 16 is a plan view of a TFT that uses a lateral crystal growth region in the configuration that is the basis of the present invention, as seen from the top surface of a substrate.

FIG. 17 is a plan view for explaining the non-uniformity of lateral crystal growth in the structure which is the basis of the present invention.

[Explanation of symbols]

100, 200, 300, 400, 500, 600 Nickel trace addition region 101, 201, 601 Glass substrate 102, 202, 602 Underlayer film 104, 204, 304, 404, 504, 604 Mask 106, 206, 306, 406, 506 , 606 Crystal growth direction 107, 207, 607 Gate insulating film 108, 208, 508, 608, 609 Gate electrode 109 Anodized layer 110, 210, 310, 410, 510, 610, 6
11, 702 Channel regions 111, 211, 311, 411, 511 Source regions 112, 212, 312, 412, 512 Drain regions 113, 213, 616 Interlayer insulators 114, 115, 214, 215, 515, 617, 6
19 electrodes

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-7-99314 (JP, A) JP-A-7-74366 (JP, A) JP-A-7-66425 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/20 H01L 29/786 H01L 21/336

Claims (4)

(57) [Claims] 1. A semiconductor device in which a channel region is formed on a substrate having an insulating surface by using a crystalline silicon film, wherein the channel region is an amorphous silicon film and a crystal of the silicon film. By selectively introducing a catalytic element that promotes chemical conversion into a linear shape and performing a heat treatment at a predetermined annealing temperature, in a peripheral portion of the linear area where the catalytic element is selectively introduced, the element is parallel to the substrate surface. The lateral direction which is the minor axis direction of the linear region
Direction , the channel region has a constant crystal growth distance in the lateral direction.
A semiconductor device , characterized in that it is configured by utilizing a region that becomes 2. A semiconductor device in which a channel region is formed on a substrate having an insulating surface by using a crystalline silicon film, the channel region being an amorphous silicon film and a crystal of the silicon film. By selectively introducing a catalytic element that promotes chemical conversion into a linear shape and performing a heat treatment at a predetermined annealing temperature, in a peripheral portion of the linear area where the catalytic element is selectively introduced, the element is parallel to the substrate surface. From the linear region to the shortness of the linear region
It is formed by a crystalline silicon film which is crystallized in a lateral direction which is an axial direction, and the channel region has a linear region extending from an end of the linear region.
The lateral crystal growth distance becomes constant along the long axis of the region.
Placed so that it is at least the distance (b) to the area
A semiconductor device characterized in that 3. A step of forming an amorphous silicon film on a substrate, a step of selectively introducing linearly a catalyst element that promotes crystallization before or after the step, and a step of heating the non-crystalline silicon film. The crystalline silicon film is crystallized, and in the peripheral portion of the linear region into which the catalytic element is selectively introduced, a direction substantially parallel to the substrate surface and extending from the linear region to the linear region.
And a step of forming a thin film transistor of a crystalline silicon film and the step of laterally perform crystal growth is minor axis direction, said to perform the crystal growth in a direction substantially parallel to the substrate surface region of the band In a method of manufacturing a semiconductor device, a channel region of the thin film transistor is formed in the lateral direction.
The feature is that it is formed in a region where the crystal growth distance is constant.
A method for manufacturing a semiconductor device. 4. A step of forming an amorphous silicon film on a substrate, a step of selectively introducing a catalyst element that promotes crystallization into a linear shape before or after the step, and a step of heating the non-crystalline silicon film. The crystalline silicon film is crystallized, and in the peripheral portion of the linear region into which the catalytic element is selectively introduced, a direction substantially parallel to the substrate surface and extending from the linear region to the linear region.
A step of causing crystal growth in a lateral direction which is a short axis direction of the region, and a step of forming a thin film transistor with a crystalline silicon film in a region where crystal growth is performed in a direction substantially parallel to the substrate surface. In the method of manufacturing a semiconductor device, the channel region is formed from the end of the linear region to the linear region.
The lateral crystal growth distance becomes constant along the long axis of the region.
The distance (b) to the area
A method of manufacturing a semiconductor device, comprising: