JPH11251746A - Manufacture of thin-type multilayer printed wiring board - Google Patents

Manufacture of thin-type multilayer printed wiring board

Info

Publication number
JPH11251746A
JPH11251746A JP6762698A JP6762698A JPH11251746A JP H11251746 A JPH11251746 A JP H11251746A JP 6762698 A JP6762698 A JP 6762698A JP 6762698 A JP6762698 A JP 6762698A JP H11251746 A JPH11251746 A JP H11251746A
Authority
JP
Japan
Prior art keywords
hole
printed wiring
wiring board
multilayer printed
via holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6762698A
Other languages
Japanese (ja)
Inventor
Kazumitsu Ishikawa
和充 石川
Makoto Iwabori
誠 岩堀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lincstech Circuit Co Ltd
Original Assignee
Hitachi AIC Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi AIC Inc filed Critical Hitachi AIC Inc
Priority to JP6762698A priority Critical patent/JPH11251746A/en
Publication of JPH11251746A publication Critical patent/JPH11251746A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To reduce the space of each via hole in the most outer layer and thereby increase the density of via holes by using through hole lands of a shield board as pads for connecting the via holes which are formed on the surfaces of the most outer layers have a circular shape concentrical with a through hole and have a taper angle. SOLUTION: This shield board of two or more layers has through hole lands 14, 15, 16, 17, a conduction connection hole 12, inner layer conductors 4, 5, hole filling insulating resin 9 and the like. On the front and the rear face of the shield board, an epoxy resin-made interlayer adhesive 19A, 19B is applied for multilayer bonding. The through hole lands 14, 15, 16, 17 are used as pads for connecting via holes 31, 32 on the surfaces of the most outer layers, and via holes 31, 32 having a taper angle of 9-19 deg. and a circular shape concentrical with the conduction connection hole 12 are formed. By this method, a thin-type multilayer printed wiring board which is suitable for reduction in thickness and high-density mounting and has an excellent connection reliability can be manufactured.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、2層以上のプリン
ト配線板に関し、内層のシールド板のスルホールランド
を最外層のビアホール形成の接続用パッドに用い、テー
パ角を設ける薄物多層プリント配線板の製造方法に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board having two or more layers, and more particularly to a thin multilayer printed wiring board having a taper angle by using a through hole land of an inner shield plate as a connection pad for forming a via hole in an outermost layer. It relates to a manufacturing method.

【0002】[0002]

【従来の技術】近年の軽薄短小、かつ高機能機器の典型
ともいえるマルチメディア端末,多機能高精度情報通信
機器の急速な普及に伴ない、これらに用いられる電子部
品搭載用のプリント配線板に対する高密度実装化,薄形
化の要求は加速される一方である。また、プリント配線
板の製造方法としては、多数のビアホールによる電気的
な接続と回路を順に積み上げる製造方法により、高密度
実装化,薄形化及び低コスト化とを図ることが急速に進
展している現状である。以下、従来の技術により作製さ
れた製造方法において、図6(a)〜(c),図7
(d),図8とに基づき製造工程を説明する。
2. Description of the Related Art With the rapid spread of multimedia terminals and multifunctional, high-precision information communication devices which can be regarded as typical of light, thin, small and high-performance devices in recent years, printed wiring boards for mounting electronic components used in these devices have been developed. The demand for high-density packaging and thinning is accelerating. Also, as a method of manufacturing a printed wiring board, it is rapidly progressing to achieve high-density mounting, thinning, and cost reduction by a manufacturing method of sequentially stacking circuits by electrically connecting a large number of via holes. It is the present situation. 6 (a) to 6 (c) and FIG.
The manufacturing process will be described with reference to FIG.

【0003】まず、図6(a)に示すように、表裏銅箔
41・42,内層導体44・45,絶縁基板43とから
なる板厚さ0.8〜1.2mm程のガラス布エポキシ銅張
積層板43Aに選択的に0.4mmφドリルを用い、貫通
孔46を穿孔後、化学めっきと電気銅めっきとを併用
し、前記貫通孔46の内壁及び絶縁基板43Aの表裏全
面上に第1銅めっき層47・48を析出形成する。
First, as shown in FIG. 6A, a glass cloth epoxy copper having a thickness of about 0.8 to 1.2 mm including front and back copper foils 41 and 42, inner layer conductors 44 and 45, and an insulating substrate 43. After selectively drilling a through hole 46 in the laminated laminate 43A using a 0.4 mmφ drill, a chemical plating and an electrolytic copper plating are used together, and a first hole is formed on the inner wall of the through hole 46 and the entire front and back surfaces of the insulating substrate 43A. The copper plating layers 47 and 48 are deposited and formed.

【0004】次いで図6(b)に示すように、前記貫通
孔46の内壁に第1銅めっき層47・48を形成した導
通接続穴52の穴内にメタルマスクを用い、スクリーン
印刷法とにより穴埋めの絶縁樹脂49を円弧形状に塗布
・乾燥後、この表裏上を機械的な方法(ブラシ・バフ)
を用い、研摩後フォトエッチング法,剥離工程を経てス
ルホールランド54・55・56・57と配線層50・
51とを形成する。
[0006] Next, as shown in FIG. 6 (b), a hole is filled by a screen printing method using a metal mask in a hole of the conductive connection hole 52 in which first copper plating layers 47 and 48 are formed on the inner wall of the through hole 46. After applying and drying the insulating resin 49 in an arc shape, a mechanical method (brush buff)
After polishing, a through-etching method and a peeling step are performed, and throughhole lands 54, 55, 56, 57 and wiring layer 50
51 are formed.

【0005】次いで、図6(c)に示すように、前記図
6(b)に形成した表裏面上を酸化還元処理を行い、こ
の表裏面上に片面銅箔・接着剤付着のプリプレグ58A
・58Bを配設,多層化接着59する。しかる後に、内
層板の貫通孔46直径より大きい径のドリルやエンドミ
ルとを用い、ビア非貫通孔60・61を大きく、スルホ
ールランド54・55・56・57層に到達する深さ迄
穿孔するのが必須工程である。
Next, as shown in FIG. 6 (c), the front and back surfaces formed in FIG. 6 (b) are subjected to oxidation-reduction treatment, and a prepreg 58A having a single-sided copper foil and an adhesive adhered to the front and back surfaces.
-Arrange 58B and make a multilayer adhesive 59. Thereafter, using a drill or end mill having a diameter larger than the diameter of the through hole 46 of the inner layer plate, the via non-through holes 60 and 61 are drilled to a depth reaching the through hole lands 54, 55, 56 and 57 layers. Is an essential step.

【0006】次いで、図7(d)に示すように、前記ビ
ア非貫通孔60・61の穿孔時に孔内壁に付着している
炭化物46Aを除去するために過マンガン酸カリ処理等
を施し後、化学めっきと電気銅めっきとを併用し第2銅
めっき層47A・48Bを施す。しかる後にフォトエッ
チング,剥離工程を経て最外層のビアホール62・63
と配線層50・51とを形成し得、その後永久熱硬化型
レジスト64・65をフォト塗布・乾燥して、占有面積
の大きい従来の技術に係る薄物多層プリント配線板の製
造方法67が得られるものである。
[0007] Next, as shown in FIG. 7 (d), potassium permanganate treatment or the like is performed to remove carbides 46 A adhering to the inner walls of the via non-through holes 60 and 61 at the time of drilling. The second copper plating layers 47A and 48B are applied by using both chemical plating and electrolytic copper plating. Thereafter, the via holes 62 and 63 in the outermost layer are subjected to photoetching and peeling steps.
And the wiring layers 50 and 51 can be formed, and then the permanent thermosetting resists 64 and 65 are photo-coated and dried to obtain a thin multilayer printed wiring board manufacturing method 67 according to the prior art having a large occupied area. Things.

【0007】次いで、図8に示すように、前記ビア非貫
通孔60・61を穿孔する場合に、ビア非貫通孔60・
61壁面の孔の軸に対するテーパ角60A・61Aが0
度に穿孔されるため、このコーナー部において、第2銅
めっき47A・48B付き回り性不良個所66が起き、
リフロー工程においてクラック現象が発生するおそれが
あり、電気的な接続信頼性に欠けるという従来技術に係
る要部模式断面図である。
Next, as shown in FIG. 8, when the via non-through holes 60 and 61 are formed,
61 The taper angles 60A and 61A with respect to the axis of the hole in the wall are 0
In this corner portion, a turning defect portion 66 with second copper plating 47A / 48B occurs at this corner portion,
FIG. 4 is a schematic cross-sectional view of a main part according to a related art, in which a crack phenomenon may occur in a reflow process and electrical connection reliability is lacking.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、上述し
た従来の技術に係る薄物多層プリント配線板の製造方法
67では、まずその第1として、ビア非貫通孔60・6
1径(φ)を貫通孔46径(φ)よりも大きい径(φ)
にすることが必須加工条件のために、最外層のビアホー
ル62・63の小スペース化・高密度化を実現すること
が難しいという問題が起る恐れがある。
However, in the above-described method 67 for manufacturing a thin multilayer printed wiring board according to the prior art, first, the via non-through holes 60 and 6 are first used.
One diameter (φ) is larger than the diameter of the through hole 46 (φ) (φ)
Because of the essential processing conditions, it may be difficult to reduce the space and increase the density of the outermost via holes 62 and 63.

【0009】またビア非貫通孔60・61の穿孔にエン
ドミル・ドリルを用いることによりスルホールランド5
4・55・56・57の厚さを50〜60μm程厚く形
成する必要が生じ、薄形化,低コストとに難しいという
恐れがある。
Further, by using an end mill drill for drilling the via non-through holes 60 and 61, the through hole land 5 is formed.
It is necessary to make the thickness of 4.55.56.57 as thick as about 50 to 60 μm, and there is a possibility that it is difficult to reduce the thickness and cost.

【0010】次いで、その第2として、ビア非貫通孔6
0・61の穿孔にエンドミル,ドリルを用いるため、ビ
ア非貫通孔60・61壁面の孔の軸に対するテーパ角6
0A・61Aが0度に穿設されるために、このコーナー
部において第2銅めっき47A・48Bの付き回り性不
良個所66が起り、リフロー環境下において電気的な接
続信頼性に問題が起る恐れがある。
Next, as the second, a via non-through hole 6 is formed.
Since the end mill and the drill are used for drilling of 0.61 and 0.61, the taper angle 6 with respect to the axis of the hole of the wall of the non-via hole 60 and 61 is used.
Since 0A and 61A are drilled at 0 degrees, poor cornering portions 66 of the second copper platings 47A and 48B occur at these corners, causing a problem in electrical connection reliability under a reflow environment. There is fear.

【0011】依って、本発明では、上述の事情を鑑みて
なされたものであり、その目的とするところは、上記の
問題を解決し、より優れた薄物多層プリント配線板の製
造方法35を提供することにある。
Accordingly, the present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to solve the above-described problems and to provide a more excellent method 35 of manufacturing a thin multilayer printed wiring board. Is to do.

【0012】[0012]

【課題を解決するための手段】本発明では、2層以上の
シールド板18にて、配線層10・11,導通接続穴1
2及びスルホールランド14・15・16・17とをも
ち、前記シールド板18の表裏上に層間接着剤19A・
19Bを多層化接着20A・20B形成し、前記シール
ド板18と電気的に接続させる最外層のビアホール31
・32を形成して成る薄物多層プリント配線板を製造す
る方法にあって、前記シールド板18のスルホールラン
ド14・15・16・17を最外層の表裏上に前記スル
ホール12と同一軸上の同芯円形状でテーパ角27・2
8を有するビアホール31・32の接続用パッドに用い
る製造工程を設けようとするものである。
According to the present invention, wiring layers 10 and 11 and conductive connection holes 1 are formed by two or more shield plates 18.
2 and throughhole lands 14, 15, 16 and 17, and an interlayer adhesive 19 A
19B is formed as a multilayer adhesive 20A / 20B, and the outermost via hole 31 electrically connected to the shield plate 18 is formed.
32. A method for manufacturing a thin multilayer printed wiring board formed by forming the through holes 32, 15.16, 17 of the shield plate 18 on the front and back surfaces of the outermost layer on the same axis as the through holes 12. 27.2 taper angle with core circle shape
This is intended to provide a manufacturing process used for connecting pads of the via holes 31 and 32 having 8.

【0013】[0013]

【発明の実施の形態】本発明の2層以上のシールド板1
8においてスルホールランド14・15・16・17,
導通接続穴12,内層導体4・5,穴埋め絶縁樹脂9等
有し、この表裏にエポキシ樹脂からなる層間接着剤19
A・19Bを配設,多層化接着20A・20B形成し
て、前記スルホールランド14・15・16・17層を
最外層の表裏上にビアホール31・32を形成する接続
用パッドに用いるもので、9〜19度のテーパ角を有
し、前記導通接続穴12の同一軸上の同芯円形状にビア
ホール31・32を形成し、薄形化,高密度実装化,高
密度化及び電気的な接続信頼性に優れた薄物多層プリン
ト配線板を製造する方法35を実現しようとするもので
ある。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A shield plate 1 having two or more layers according to the present invention.
At 8, Surholeland 14, 15, 16, 17,
It has a conductive connection hole 12, inner layer conductors 4 and 5, filling insulating resin 9, etc., and an interlayer adhesive 19 made of epoxy resin on the front and back.
A, 19B are provided, and multi-layer adhesives 20A, 20B are formed, and the through hole lands 14, 15, 16, 17 layers are used as connection pads for forming via holes 31, 32 on the front and back surfaces of the outermost layer. The via holes 31 and 32 have a taper angle of 9 to 19 degrees and are formed in concentric circular shapes on the same axis of the conductive connection holes 12 so as to reduce the thickness, increase the mounting density, increase the electrical density, It is intended to realize a method 35 for producing a thin multilayer printed wiring board having excellent connection reliability.

【0014】[0014]

【実施例】以下、本発明の実施例の製造工程を示す、図
2(a)〜(b),図3(c)〜(d),図4(e),
図5,図1に基づいて具体的に説明する。
2 (a) to 2 (b), 3 (c) to 3 (d), 4 (e) and 4 (e) show the manufacturing steps of an embodiment of the present invention.
This will be specifically described with reference to FIGS.

【0015】(実施例1)まず、図2(a)に示すよう
に、表裏銅箔1・2,厚さ18μm,内層導体44・4
5,厚さ35μm(18μm),絶縁基板3等からなる
ガラスエポキシ銅張積層板(板厚さ0.4〜0.6mm・
FR−4)に選択的にマイクロドリル径0.2mmφを用
い自動数値制御穴明け機(日立精工製MARK・10
0)を使い、貫通孔6を穿孔後、前記貫通孔6の内壁及
び表裏全面に厚さ20〜25μmに化学めっきと電気銅
めっきを併用施し、第1銅めっき層7・8を形成し、導
通接続穴(スルホール)12を得る。
(Embodiment 1) First, as shown in FIG. 2A, front and back copper foils 1.2, thickness 18 μm, inner layer conductors 44.4
5, a glass epoxy copper clad laminate (thickness 0.4 to 0.6 mm) consisting of an insulating substrate 3 and a thickness of 35 μm (18 μm)
Automatic numerical control drilling machine (MARK-10, manufactured by Hitachi Seiko) using micro-drill diameter 0.2mmφ selectively for FR-4)
0), the first copper plating layers 7 and 8 are formed by performing chemical plating and electrolytic copper plating together to a thickness of 20 to 25 μm on the inner wall and the entire front and back surfaces of the through hole 6 after forming the through hole 6; A conductive connection hole (through hole) 12 is obtained.

【0016】次いで、図2(b)に示すように、前記導
通接続穴12の穴内に選択的にメタルマスクを用い、ス
クリーン印刷法により穴埋め絶縁樹脂9(エポキシ変性
樹脂等)を永久穴埋めし、乾燥(温度150〜160℃
・時間40〜50分間)硬化閉塞後、表裏導通接続穴1
2上に円弧突起形状に形成された永久穴埋め絶縁樹脂9
上を機械的手法(ブラシ・バフ)を用い、第1銅めっき
層7・8よりも5μm未満高くなるように研摩する。そ
の後、フォトエッチング法・剥離工程を経て配線層10
・11とスルホールランド14・15・16・17とを
含むシールド板18を形成する。
Next, as shown in FIG. 2 (b), a hole filling insulating resin 9 (epoxy modified resin or the like) is permanently filled in the conductive connection hole 12 by a screen printing method using a metal mask selectively. Drying (temperature 150-160 ° C
・ Time 40 to 50 minutes) After curing and closing, the front and back conductive connection holes 1
Permanent hole filling insulating resin 9 formed in the shape of an arc projection on 2
The upper side is polished using a mechanical method (brush buff) so as to be lower than the first copper plating layers 7.8 by less than 5 μm. Thereafter, the wiring layer 10 is subjected to a photo-etching method and a stripping process.
11 and the shield plate 18 including the throughhole lands 14, 15, 16, 17.

【0017】また、ビアホール31・32の接続用パッ
ドとになるスルホールランド14とスルホールランド1
6との間隔及びスルホールランド15とスルホールラン
ド17との間隔を110〜300μmの範囲が適してい
るがさらに好適は200〜250μmの範囲が好まし
い。
The through hole land 14 and the through hole land 1 serving as connection pads for the via holes 31 and 32 are provided.
6 and the distance between the throughhole land 15 and the throughhole land 17 are preferably in the range of 110 to 300 μm, more preferably in the range of 200 to 250 μm.

【0018】そうして、その第1として、上記スルホー
ルランド14と16,15と17との間隔が110μm
未満である場合には、前記貫通孔6の穿孔時、微小穴径
(0.15mmφ未満)のため、量産性に適さなく、さら
に300μmを超える場合には、接続用パッドになるス
ルホールランド14・15・16・17の間隔が大きく
なり小スペース化,高密度化とに適さない。
First, the distance between the throughhole lands 14 and 16, and between the throughhole lands 15 and 17 is 110 μm.
If it is less than 1, the through hole 6 is not suitable for mass production due to the minute hole diameter (less than 0.15 mmφ) when it is drilled, and if it exceeds 300 μm, the through hole land 14. The spacing between 15, 16, and 17 becomes large, which is not suitable for reducing the space and increasing the density.

【0019】その第2として、前記スルホールランド1
4・15・16・17の厚さを30〜60μmの範囲が
適しているがさらに好適は40〜50μmの範囲が好ま
しい。
Second, the through hole land 1
The thickness of 4.15.16.17 is preferably in the range of 30 to 60 μm, more preferably in the range of 40 to 50 μm.

【0020】また、前記スルホールランド14・15・
16・17の厚さが30μm未満である場合には、横励
起型大気圧型CO2レーザ加工を行う場合に、微薄ラン
ドの厚さのために、くぼみ変形やボイドとが起き適さな
く、さらに60μmを超える場合には、レーザ加工には
適しているが薄板化に適さなくいずれも適さない。
In addition, the above-mentioned throughhole lands 14, 15,.
When the thickness of 16.17 is less than 30 μm, when performing transverse excitation type atmospheric pressure type CO 2 laser processing, dent deformation and voids occur due to the thickness of the thin land, which is not suitable. If it exceeds 60 μm, it is suitable for laser processing but not suitable for thinning, and neither is suitable.

【0021】次いで、図3(c)に示すように、その第
1として、前記穴埋め絶縁樹脂9入りシールド板18の
全面上を化学的に親水化し、粗化(例えば、週マンガン
酸塩のアルカリ溶液と)を行いアンカー効果を出す場合
に、前記スルホールランド14・15・16・17上の
表面粗さRaを3〜30μmの範囲が適しているがさら
に好適は、10〜15μmの範囲が好ましい。
Next, as shown in FIG. 3 (c), firstly, the entire surface of the shield plate 18 containing the insulating resin 9 filled with holes is chemically hydrophilicized and roughened (for example, alkalinized manganate). In the case of performing an anchor effect by using a solution, the surface roughness Ra on the throughhole lands 14, 15, 16, 17 is preferably in the range of 3 to 30 μm, more preferably 10 to 15 μm. .

【0022】また、前記スルホールランド14・15・
16・17上の表面粗さRaを3μm未満である場合に
は、ビアホール31・32底面径部が平滑化すぎて、第
2銅めっき層7A・8Bの付着強度が不足する恐れがあ
り適さなく、さらに30μmを超える場合には、クボミ
部分に第2銅めっき層7A・8Bが厚さ3〜5μm程薄
く析出するため、はんだリフロー工程とにより電気的な
接続性不良が起る恐れがあり適さない。
Further, the above-mentioned throughhole lands 14.15.
If the surface roughness Ra on the surfaces 16 and 17 is less than 3 μm, the diameters of the bottom surfaces of the via holes 31 and 32 are too smooth, and the adhesion strength of the second copper plating layers 7A and 8B may be insufficient. When the thickness exceeds 30 μm, the second copper plating layers 7A and 8B are deposited to a thickness of about 3 to 5 μm thinly on the bubbling portion, which may cause poor electrical connectivity due to the solder reflow process. Absent.

【0023】次に、前記過マンガン酸塩としては、例え
ば過マンガン酸ナトリウム,過マンガン酸カリウムなど
の酸化剤がよく、アルカリ剤として、水酸化ナトリウ
ム,水酸化カリウム,炭酸カリウム,炭酸ナトリウムと
がよく、上記の過マンガン酸塩とアルカリ剤を一つ以上
づつ任意に組み合わせて混合し使用する。液温は、例え
ば45〜65℃程でよく、浸漬時間としては、例えば3
〜15分程でよい。
The permanganate is preferably an oxidizing agent such as sodium permanganate or potassium permanganate, and sodium hydroxide, potassium hydroxide, potassium carbonate or sodium carbonate as an alkaline agent. Frequently, one or more of the above permanganates and alkali agents are arbitrarily combined and mixed for use. The liquid temperature may be, for example, about 45 to 65 ° C., and the immersion time may be, for example, 3
It takes about 15 minutes.

【0024】次いで、前記シールド板18の表裏上に厚
さ50μm程のエポキシ接着フィルム(日立化成製商品
名AS3000)からなる層間接着剤19A・19Bを
配設後、多層化接着20A・20Bにより形成、しかる
後に前記シールド板18の導通接続穴12と同一軸上の
同芯円形状にビアホール31・32を形成かつマスクイ
メージング法を用い、横励起型大気圧型のCO2レーザ
加工する場合に、ビア非貫通孔21・23壁面の孔の軸
に対するテーパ角27・28が9〜19度の範囲が適し
ているがさらに、好適は、13〜16度の範囲が好まし
い。
Next, after the interlayer adhesives 19A and 19B made of an epoxy adhesive film (Hitachi Chemical Co., Ltd., AS3000) having a thickness of about 50 μm are provided on the front and back surfaces of the shield plate 18, they are formed by the multilayer adhesives 20A and 20B. Then, when the via holes 31 and 32 are formed concentrically on the same axis as the conductive connection holes 12 of the shield plate 18 and a masking method is used to process the transversely excited atmospheric pressure type CO 2 laser, The taper angle 27/28 with respect to the axis of the hole of the via non-through hole 21/23 is preferably in the range of 9 to 19 degrees, more preferably 13 to 16 degrees.

【0025】また、前記テーパ角27・28が9度未満
である場合には、前記ビア非貫通孔21・23の壁面の
孔の軸に対するテーパ角27・28が鋭角(0度に近づ
く)に穿孔加工されるため底部のコーナー部に銅めっき
付き回り性不良個所66が起きる恐れがあり電気的な接
続信頼性に問題があり適さなく、さらに19度を超える
場合には、ビア非貫通孔21・23の上径が大きく形成
され小スペース化にならず高密度実装化も実現出来ずら
くなり、いずれも適さない。
When the taper angles 27 and 28 are less than 9 degrees, the taper angles 27 and 28 with respect to the axis of the hole on the wall surface of the non-via holes 21 and 23 become acute angles (approaching 0 degrees). Since drilling is performed, there is a possibility that a turning failure portion 66 with copper plating may occur at the bottom corner portion, and there is a problem in electrical connection reliability. If it exceeds 19 degrees, the via non-through hole 21 -The upper diameter of 23 is large, so that it is difficult to realize high-density mounting without reducing the space, and neither is suitable.

【0026】次いで、前記ビア非貫通孔21・23を横
励起型大気圧型CO2レーザ加工法により穿設する場合
には、内壁面上、スルホールランド14・15・16・
17面上及び穴埋め絶縁樹脂9とに炭化物24が残渣と
して1μm未満程度付着する。この炭化物24を除去す
るために、例えばアルカリ性過マンガン酸カリ溶液,C
rO3-アルカリ溶液等を用い、液温40〜50℃で時間
1〜2分間程度がよく、処理法は例えば、スプレー吹
付,浸漬等でよい。
Next, when the via non-through holes 21 and 23 are formed by the lateral excitation type atmospheric pressure type CO 2 laser processing method, the through hole lands 14, 15, 16.
Carbide 24 adheres as a residue to the surface 17 and the insulating resin 9 to fill the hole with a thickness of less than about 1 μm. In order to remove the carbides 24, for example, an alkaline potassium permanganate solution, C
The temperature is preferably about 1 to 2 minutes at a liquid temperature of 40 to 50 ° C. using an rO 3 -alkali solution or the like.

【0027】次いで、図3(d)に示すように最外層の
表裏上にフォテック,ネガ型の感光性フィルム(レジス
ト)(日立化成製商品名、水系現像タイプ・SR−30
00)を用い、永久レジスト層29・30を形成後1.
5μm/Hrで20Hr程に無電解銅めっき(日立エー
アイシー製)を施し、テーパ角を有するビアホール31
・32を形成する。
Next, as shown in FIG. 3 (d), on the front and back of the outermost layer, a photosensitive film (resist) of Photek, negative type (trade name, manufactured by Hitachi Chemical Co., Ltd., aqueous developing type SR-30)
00), and after forming the permanent resist layers 29 and 30,
Electroless copper plating (manufactured by Hitachi AIC) is applied at about 5 μm / Hr for about 20 hours to form a via hole 31 having a taper angle.
Form 32.

【0028】次いで、図4(e)に示すように最外層に
メタルマスクを用い、スクリーン印刷法によりはんだ3
3・34厚さ70μm程度塗布後、温度340℃,時間
0.5分程度のフュージング工程を行ない高密度実装化
・薄形化との本発明の薄物多層プリント配線板の製造方
法35が得られる。
Next, as shown in FIG. 4E, a solder mask 3 is formed by screen printing using a metal mask as the outermost layer.
After applying a thickness of about 3.3 μm and a thickness of about 70 μm, a fusing step at a temperature of 340 ° C. for a time of about 0.5 minute is performed to obtain a method 35 for manufacturing a thin multilayer printed wiring board of the present invention, which realizes high-density mounting and thinning. .

【0029】図1に示すように、次いでシールド板18
のスルホールランド14・15・16・17を接続用パ
ッドに用い、テーパ角9〜19度程を有したビア非貫通
孔21・23を穿設し、上径100μmφ程のビアホー
ル31・32を形成し得たことにより従来より4〜5%
小スペース化,高密度実装化及び薄板化とが達成でき得
た本発明の薄物多層プリント配線板の製造方法35の実
施例を示す模式断面図である。
As shown in FIG. 1, the shield plate 18
Are used as connection pads, via non-through holes 21 and 23 having a taper angle of about 9 to 19 degrees are formed, and via holes 31 and 32 having an upper diameter of about 100 μm are formed. 4-5% than before
It is a schematic cross section which shows the Example of the manufacturing method 35 of the thin multi-layer printed wiring board of this invention which was able to achieve small space, high-density mounting, and thinning.

【0030】次いで、図5に示すように、前記CO2
ーザ加工によりビア非貫通孔21・23を設ける場合
に、前記シールド板18のスルーホール12とほぼ同一
軸上の同芯円形状に形成し、ビア非貫通孔21・23壁
面の孔の軸に対するテーパ角27・28を9〜19度の
範囲に形成する要部模式断面図である。
Next, as shown in FIG. 5, when the non-via holes 21 and 23 are provided by the CO 2 laser processing, the via holes 12 and 23 are formed in a concentric circle shape substantially coaxial with the through hole 12 of the shield plate 18. FIG. 9 is a schematic cross-sectional view of a main part in which taper angles 27 and 28 with respect to the axis of the hole of the wall surfaces of the via non-through holes 21 and 23 are formed in the range of 9 to 19 degrees.

【0031】次いで、上述の実施例のビアホール31・
32接続部の熱衝撃(MIL−107)による接続信頼
性の試験結果を表1に示す。この上記の結果よりスルホ
ールランド14・15・16・17を接続用パッドに用
いた場合にビア非貫通孔21・23壁面の孔の軸に対す
るテーパ角を13〜16度程度が銅めっき付き回り性も
含め最適条件になり得た(35)。 以下余白。
Next, the via holes 31.
Table 1 shows test results of connection reliability by thermal shock (MIL-107) of 32 connection parts. From the above results, when the through-hole lands 14, 15, 16, 17 are used as the connection pads, the taper angle with respect to the axis of the hole of the wall of the via non-through holes 21, 23 is about 13 to 16 degrees. Optimum conditions could be obtained (35). Margin below.

【0032】[0032]

【表1】 (1)接続信頼性(ホットオイル) 260℃,5秒間(油)→20℃(水)のサイクル5 (2)JIS,10サイクル以上で合格。 (3)試料ビアホール(穴)…100穴パターン。 (4)ビアホール上径100μm(横励起型大気圧型C
2レーザ加工) (5)従来技術…エンドミル,ドリル
[Table 1] (1) Connection reliability (hot oil) Cycle 5 from 260 ° C, 5 seconds (oil) → 20 ° C (water) 5 (2) JIS, passed 10 cycles or more. (3) Sample via hole (hole): 100 hole pattern. (4) Via hole upper diameter 100 μm (lateral excitation type atmospheric pressure type C
O 2 laser processing) (5) prior art ... end mills, drill

【0033】[0033]

【発明の効果】(1)本発明の薄物多層プリント配線板
の製造方法35によれば、シールド板18のスルホール
ランド14・15・16・17を最外層のビアホール3
1・32形成の接続用パッドに用い、テーパ角27・2
8を有する微小ビアホール31・32の形成によりコー
ナー部の銅めっき厚を解消し信頼性の向上とスルホール
の占有面積を従来より4〜5%小さくし、実装の高密度
化,配線長の短縮による信号の伝送高速化を図ることが
実現可能となり産業上寄与する効果は極めて大きい。
(1) According to the method 35 for manufacturing a thin multilayer printed wiring board of the present invention, the through-hole lands 14, 15, 16 and 17 of the shield plate 18 are connected to the via holes 3 of the outermost layer.
Used for connection pads for forming 1.32, taper angle 27.2
The formation of the micro via holes 31 and 32 having the thickness 8 eliminates the copper plating thickness at the corners, improves the reliability, reduces the area occupied by the through holes by 4 to 5%, increases the mounting density, and shortens the wiring length. It is feasible to increase the speed of signal transmission, and the effect of contributing to industry is extremely large.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例を示す模式断面図。FIG. 1 is a schematic sectional view showing an embodiment of the present invention.

【図2】(a)〜(b)は、本発明の実施例を示す断面
図。
FIGS. 2A and 2B are cross-sectional views showing an embodiment of the present invention.

【図3】(c)〜(d)は、本発明の実施例を示す断面
図。
3 (c) to 3 (d) are cross-sectional views showing an embodiment of the present invention.

【図4】(e)は、本発明の実施例を示す断面図。FIG. 4E is a sectional view showing an embodiment of the present invention.

【図5】本発明のレーザによる穴21・23加工を説明
する要部模式断面図。
FIG. 5 is a schematic cross-sectional view of a main part, illustrating the processing of holes 21 and 23 by the laser of the present invention.

【図6】(a)〜(c)は、従来技術の製造方法を示す
断面図。
FIGS. 6A to 6C are cross-sectional views showing a conventional manufacturing method.

【図7】(d)は、従来技術の製造方法を示す断面図。FIG. 7D is a cross-sectional view showing a conventional manufacturing method.

【図8】従来の技術に係るビアホール62・63コーナ
ー部の銅めっき付き回り不良個所66を説明する要部模
式断面図。
FIG. 8 is a schematic cross-sectional view of a main part illustrating a defective portion 66 with copper plating around corners of via holes 62 and 63 according to a conventional technique.

【符号の説明】[Explanation of symbols]

1・2…銅箔 3…絶縁基板 4・5…内層導体 6…
貫通孔 7・8…第1銅めっき層 7A・8B…第2銅めっき層
9…穴埋め絶縁樹脂 10・11…配線層 12…導通接続穴(スルホール) 13…スルホール上の表面粗さRa 14・15・16・17…スルホールランド 18…シールド板(内層回路入りガラス布エポキシ銅張
り積層板) 19A・19B…層間接着剤 20A・20B…多層化
接着 21・23…ビア非貫通孔 24…炭化物 27・28
…テーパ角(θ) 29・30…永久感光レジスト 31・32…ビアホー
ル 33・34…はんだ 35…本発明の薄物多層プリント
配線板の製造方法 41・42…銅箔 43…絶縁基板 43A…ガラス布
エポキシ銅張り積層板 44・45…内層導体 46…貫通孔 46A…炭化物 47・48…第1銅めっき層 47A・48B…第2銅
めっき層 49…穴埋め絶縁樹脂 50・51…配線層 52…導
通接続穴(スルホール) 54・55・56・57…スルホールランド 58A・58B…片面銅箔,接着剤付きプリプレグ 5
9…多層化接着 60・61…ビア非貫通孔 60A・61A…テーパ角
(θ) 62・63…ビアホール 64・65…熱硬型レジスト 66…銅めっき付き回り性不良個所 67…従来の技術に係る薄物多層プリント配線板の製造
方法
1.2 Copper foil 3 Insulating substrate 4.5 Inner layer conductor 6
Through hole 7.8 First copper plating layer 7A / 8B Second copper plating layer 9 Filling insulating resin 10.11 Wiring layer 12 Conductive connection hole (through hole) 13 Surface roughness Ra on through hole 14. 15.16.17 ... Surhole land 18 ... Shield plate (glass cloth epoxy copper clad laminate with inner layer circuit) 19A / 19B ... Interlayer adhesive 20A / 20B ... Multilayer bonding 21.23 ... Via non-through hole 24 ... Carbide 27・ 28
... Taper angle (.theta.) 29/30 Permanent photosensitive resist 31/32 Via hole 33/34 Solder 35 ... Method of manufacturing thin multilayer printed wiring board of the present invention 41/42 Copper foil 43 ... Insulating substrate 43A ... Glass cloth Epoxy copper-clad laminates 44/45 ... Inner layer conductor 46 ... Through hole 46A ... Carbide 47/48 ... First copper plating layer 47A / 48B ... Second copper plating layer 49 ... Filling insulating resin 50/51 ... Wiring layer 52 ... Conduction Connection hole (Sur hole) 54, 55, 56, 57: Sur hole land 58A, 58B: Single-sided copper foil, prepreg with adhesive 5
9 Multi-layer bonding 60 ・ 61 ・ ・ ・ Via non-through hole 60A ・ 61A ・ ・ ・ Taper angle (θ) 62 ・ 63 ・ ・ ・ Via hole 64 ・ 65 ・ ・ ・ Heat-hardening resist 66 ・ ・ ・ Poor turning defect with copper plating 67 ・ ・ ・ Conventional technology Method for manufacturing such a thin multilayer printed wiring board

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 2層以上の内層のシールド板(18)に
おいて、配線層(10)・(11),導通接続穴(1
2)及びスルホールランド(14)・(15)・(1
6)・(17)とをもち、前記内層のシールド板(1
8)の表裏上に層間接着剤(19A)・(19B)を多
層化接着(20A)・(20B)で形成し、前記シール
ド板(18)と電気的に接続させる最外層のビアホール
(31)・(32)をCO2レーザ加工にて形成して成
る薄物多層プリント配線板を製造する方法にあって、前
記内層のシールド板(18)のスルホールランド(1
4)・(15)・(16)・(17)を最外層の表裏上
に前記スルホール(12)と同一軸上の同芯円形状でテ
ーパ角(27)・(28)を設けるビアホール(31)
・(32)の接続用パッドに用い、高密度実装化及び高
速化対応ができることを特徴とする本発明の薄物多層プ
リント配線板の製造方法(35)。
In a shield plate (18) having two or more inner layers, wiring layers (10) and (11) and conductive connection holes (1) are provided.
2) and Sur Hall Land (14) ・ (15) ・ (1)
6) and (17), wherein the inner shield plate (1)
8) Interlayer adhesives (19A) and (19B) are formed on the front and back surfaces by multi-layer bonding (20A) and (20B), and the outermost via holes (31) are electrically connected to the shield plate (18). A method of manufacturing a thin multilayer printed wiring board formed by forming (32) by CO 2 laser processing, wherein the through hole land (1) of the inner layer shield plate (18) is provided;
4) A via hole (31) in which (15), (16), and (17) are formed on the front and back surfaces of the outermost layer in a concentric circular shape on the same axis as the through hole (12) and provided with taper angles (27) and (28). )
-The method (35) for manufacturing a thin multilayer printed wiring board according to the present invention, wherein the method is used for the connection pad of (32), and high-density mounting and high-speed operation can be performed.
【請求項2】 請求項1において、前記最外層に形成す
るビアホール(31)・(32)用接続用パッドに用い
る表スルホールランド(14)と表スルホールランド
(16)との間隔及び裏スルホールランド(15)と裏
スルホールランド(17)との間隔を110μm〜30
0μmの範囲またはシールド板(18)のスルホール
(12)と同一軸上の同芯円形状にビアホール(31)
・(32)を形成してビア非貫通孔(21)・(23)
壁面の孔の軸に対するテーパ角(27)・(28)が9
〜19度の範囲に形成することを特徴とする薄物多層プ
リント配線板の製造方法(35)。
2. The distance between the front through hole land (14) and the front through hole land (16) used for the connection pads for the via holes (31) and (32) formed in the outermost layer and the back through hole land according to claim 1. The distance between (15) and the back throughhole land (17) is 110 μm to 30 μm.
A via hole (31) having a diameter of 0 μm or a concentric circle on the same axis as the through hole (12) of the shield plate (18).
· Forming (32) to form non-via holes (21) and (23)
The taper angles (27) and (28) with respect to the axis of the hole in the wall surface are 9
A method for manufacturing a thin multilayer printed wiring board (35), wherein the thin-film multilayer printed wiring board is formed at a temperature in the range of about to 19 degrees.
【請求項3】 請求項1において、前記スルホールラン
ド(14)・(15)・(16)・(17)上の表面粗
さRa(13)を3〜30μmの範囲または、前記接続
用パッドに用いるスルホールランド(14)・(15)
・(16)・(17)の厚さを30〜60μmの範囲に
形成することを特徴とする薄物多層プリント配線板の製
造方法(35)。
3. The connection pad according to claim 1, wherein the surface roughness Ra (13) on the throughhole lands (14), (15), (16) and (17) is in a range of 3 to 30 μm or the connection pad. Surholeland used (14) ・ (15)
(16) A method for producing a thin multilayer printed wiring board (35), wherein the thickness of (16) or (17) is formed in the range of 30 to 60 μm.
JP6762698A 1998-03-04 1998-03-04 Manufacture of thin-type multilayer printed wiring board Pending JPH11251746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6762698A JPH11251746A (en) 1998-03-04 1998-03-04 Manufacture of thin-type multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6762698A JPH11251746A (en) 1998-03-04 1998-03-04 Manufacture of thin-type multilayer printed wiring board

Publications (1)

Publication Number Publication Date
JPH11251746A true JPH11251746A (en) 1999-09-17

Family

ID=13350391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6762698A Pending JPH11251746A (en) 1998-03-04 1998-03-04 Manufacture of thin-type multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JPH11251746A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002016331A (en) * 2000-06-28 2002-01-18 Ibiden Co Ltd Interlayer connection structure of wiring board and its manufacturing method, and apparatus for punching interlayer insulating layer
JP2013074262A (en) * 2011-09-29 2013-04-22 Hitachi Chemical Co Ltd Wiring board and manufacturing method of the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002016331A (en) * 2000-06-28 2002-01-18 Ibiden Co Ltd Interlayer connection structure of wiring board and its manufacturing method, and apparatus for punching interlayer insulating layer
JP4481442B2 (en) * 2000-06-28 2010-06-16 イビデン株式会社 Manufacturing method of wiring board having interlayer connection structure
JP2013074262A (en) * 2011-09-29 2013-04-22 Hitachi Chemical Co Ltd Wiring board and manufacturing method of the same

Similar Documents

Publication Publication Date Title
US7681310B2 (en) Method for fabricating double-sided wiring board
KR100701353B1 (en) Multi-layer printed circuit board and manufacturing method thereof
WO1998056219A1 (en) Multilayer printed wiring board and method for manufacturing the same
JPH1154934A (en) Multilayered printed wiring board and its manufacture
JP4043115B2 (en) Multi-layer printed wiring board
JPH1013028A (en) Single-sides circuit board for multilayered printed wiring board and multilayered printed wiring board and its manufacture
JP4857433B2 (en) Metal laminate, metal laminate manufacturing method and printed circuit board manufacturing method
KR100965341B1 (en) Method of Fabricating Printed Circuit Board
KR101170764B1 (en) Method for manufacturing Multi-layer circuit board
JPH1154926A (en) One-sided circuit board and its manufacture
JPH11251746A (en) Manufacture of thin-type multilayer printed wiring board
JP2007208229A (en) Manufacturing method of multilayer wiring board
JP2655447B2 (en) Multilayer printed wiring board for surface mounting and method of manufacturing the same
JP3304061B2 (en) Manufacturing method of printed wiring board
JP6303364B2 (en) Method for forming through hole in core substrate
JPS63137498A (en) Manufacture of through-hole printed board
JPH05327227A (en) Blind hole and its production
KR20060003847A (en) A multi-layer board provide with interconnect bump hole of the inner layer rcc and therefor method
KR100353355B1 (en) The manufacturing method for multi-layer pcb
JP3543348B2 (en) Manufacturing method of multilayer wiring board
JP4838977B2 (en) Circuit board and circuit board manufacturing method
KR200412591Y1 (en) A multi-layer board provide with interconnect bump hole of the inner layer RCC
JPH1168308A (en) Manufacture of wiring board
JPH1075064A (en) Multi-layer printed wiring board
JP2563815B2 (en) Printed wiring board with blind through holes