KR100353355B1 - The manufacturing method for multi-layer pcb - Google Patents

Abstract

PURPOSE: A method for manufacturing a multi-layer printed circuit board is provided to increase the wiring density and the mounting density by forming a metal thin film having a thin thickness to minimize erosion occurred when a circuit pattern is formed. CONSTITUTION: A printed circuit board(100) is comprised of a core layer(101), an upper build-up layer(130), and a lower build-up layer(130'). The core layer(101) is comprised of a plurality of resin layers(102) and a plurality of copper thin film layers(104). A through-hole(106) is provided on the core layer(101). The upper and lower build-up layers(130,130') are respectively formed on upper and lower surfaces of the core layer(101). An insulating resin layer(132) is formed on the upper surface of the core layer(101). A plated layer(134) is formed on a surface of the insulating resin layer(132). An insulating resin layer(132') is formed on the plated layer(134). First and second holes(136,137) are formed on the insulating resin layer(132,132').

Description

Manufacturing method of multilayer printed circuit board {THE MANUFACTURING METHOD FOR MULTI-LAYER PCB}

The present invention relates to a method for manufacturing a multilayer printed circuit board, and more particularly, to a multilayer printed circuit board having improved connection structure between a plurality of stacked layers to improve the mounting and wiring density of the printed circuit board and to minimize the wiring length. It relates to a manufacturing method of.

1 is a cross-sectional view of a multilayer printed circuit board according to the prior art. According to this, the printed circuit board 10 is formed by alternately stacking the copper thin film layer 14 on the insulating resin layer 12. In addition, the through hole 16 penetrating the printed circuit board 10 up and down for electrical connection between the alternately laminated copper thin film layers 14, and the through hole (using electroless plating and electroplating) The inner plating layer 16a and the outer plating layer 16b are formed on the top and bottom surfaces of the inner circuit layer 16a and the printed circuit board 10.

The inner plating layer 16a formed as described above performs electrical connection between the copper thin film layers 14 and the outer plating layer 16b. An insulating resin is filled in the through hole 16.

Meanwhile, as described above, the method of sequentially forming the resin layer 12 and the copper thin film layer 14 is a method of literally laminating the resin layer 12 and the copper thin film layer 14 and the copper thin film (copper thin film layer) is coated. There is a method of forming a prepreg between resin materials (resin layers).

However, the following problems have been pointed out in the multilayer printed circuit board shown in FIG. 1 having the configuration as described above.

That is, when the through hole 16 is formed to completely penetrate the top and bottom of the printed circuit board 10 as described above, the through hole 16 also passes through the copper thin film layer 14 which does not actually need to be connected. In addition, the through hole 16 is generally processed by a computer numerical control method. The minimum diameter of the through hole 16 that can be processed is about 250 μm so that a hole having a relatively large diameter forms a final circuit pattern. It is present in the surface layer to reduce the mounting density.

On the other hand, a land of about 100 μm is present around the through hole 16, which also reduces the mounting density and the wiring density of the printed circuit board 10, and the signal lines of the circuit pattern Since it is formed by bypassing the perforation hole 16, a lot of constraints are placed on the design of the circuit pattern. In addition, due to the bypass formation of the signal line, the wiring length of the circuit pattern becomes longer, resulting in a delay of the transmitted signal and increasing noise in the signal, thereby degrading the overall performance of the printed circuit board.

In order to solve such a problem, two substrates are manufactured separately, and each through hole is processed, and then plated, and then the two substrates are joined to reduce some unnecessary connection to the IVH as shown in FIG. 2. An interstitial via hole type printed circuit board 20 is provided.

That is, the first substrate 20 'and the second substrate 20ii, which are a kind of multilayer substrate, are respectively formed, and the printed circuit board 20 is bonded by interposing a core substrate 20' between the substrates 20 'and 20ii. To make.

First, the manufacturing of the first substrate 20 'will be described. The resin layer 22 and the copper thin film layer 24 are alternately laminated to form a plurality of layers, and the resin layer 22 and the copper thin film layer 24 are formed. The through hole 26 is drilled through. Then, the inner plating layer 26a and the outer plating layer 26b are formed on the inner wall of the through hole 26 and the upper and lower surfaces of the first substrate 20 'by electroless plating and electroplating, respectively. The inner plating layer 26a and the outer plating layer 26b are electrically connected.

The second substrate 20ii is also manufactured in the same manner as the first substrate 20 '.

One printed circuit board 20 is manufactured by interposing a core substrate 20 'between the first and second substrates 20' and 20ii manufactured as described above.

That is, the core substrate 20 'provided with the copper thin film layer 29 on the upper and lower surfaces of the resin layer 28 is placed between the first and second substrates 20' and 20ii, and the resin 28 'is placed between the substrates. When the substrate is pressed and the substrates are pressed, the resin 28 'is melted to fill the through hole 26 and the resin 28' is cured so that the first substrate and the second substrate 20b and 20ii are hardened. Is bonded with the core substrate 20 코어 therebetween.

Thereafter, the through holes 30 penetrating through the substrates 20 ', 20ii, and 20' are simultaneously drilled, and the inner walls of the through holes 30 and the upper and lower surfaces of the printed circuit board 20 are formed by electroless plating and electroplating. Each of the inner plating layer 30a and the outer plating layer 30b is formed to electrically connect the copper thin layers 24 and 29 of each substrate.

However, in the IVH type printed circuit board 20, the through-hole 26 penetrating only the first substrate 20 'or the second substrate 20ii can be drilled, so that the printed circuit board 10 of FIG. Although there is an advantage, there is still a problem that the through-hole 30 penetrates the first and second substrates 20 'and 20ii.

In addition, the copper thin film layer 30b finally exposed to the outside is formed on the copper thin film layer 24 and the outer plating layer 26b of the first and second substrates 20 ⅰ and 20 ii, so that the upper and lower surfaces of the printed circuit board 20 are formed. The thickness of the copper thin film formed on the thickening is disadvantageous to the formation of the microcircuit pattern, the process is complicated and there is a problem that the productivity is low.

Accordingly, the present invention is to solve the conventional problems as described above, to improve the connection structure between each layer of a printed circuit board composed of a multi-layer.

Another object of the present invention is to provide a miniaturized and lightweight printed circuit board by facilitating pattern formation by minimizing hole formation in a portion where a circuit pattern is formed.

Still another object of the present invention is to provide a circuit pattern refined by minimizing the thickness of the copper thin film layer on the surface of a printed circuit board.

1 is a cross-sectional view showing the configuration of a multilayer printed circuit board according to the prior art.

Figure 2 is a cross-sectional view showing the configuration of a conventional IVH multilayer printed circuit board.

Figure 3 is a cross-sectional view showing the configuration of one embodiment of a multilayer printed circuit board manufactured by the present invention.

4A to 4E are process drawings showing a process of manufacturing the printed circuit board of the embodiment of the present invention shown in FIG.

Figure 5 is a cross-sectional view showing the configuration of another embodiment of a multilayer printed circuit board according to the present invention.

Explanation of symbols on the main parts of the drawings

100: printed circuit board 101: core layer

102: resin layer 104: copper thin film layer

106: through hole 106a: inner plating layer

106b: outer plating layer 107: insulating resin

108: thin film layer 130,130 ': upper and lower build-up layer

132,132 ': Insulation resin layer 134,134': Plating layer

136: first hole 137: second hole

According to a feature of the present invention for achieving the above object, the present invention comprises the steps of stacking a plurality of first insulator and the first conductive thin film in order to produce a core layer; Forming a through hole through the insulator of the core layer and the conductive thin film, and forming a conductive layer electrically connecting the conductive thin film; Forming a connection thin film layer interconnecting the conductive layers of the through hole; Stacking at least one second insulator and a second conductive thin film successively on the first conductive thin film exposed on the surface of the core layer; A via layer penetrating the second insulator and the second conductive thin film is formed above the connection thin film layer corresponding to the upper portion of the through hole, and a conductive layer electrically connecting the connection thin film layer and the second conductive thin film to the via hole. It comprises a step of forming.

The via hole penetrating the second insulator and the second conductive thin film is formed by a photo via processing method, or the via hole penetrating the second insulator and the second conductive thin film is etched a circuit pattern on the second conductive thin film. The second conductive thin film at the position where the via hole is formed is formed by removing the diameter of the via hole by etching and removing the second insulator by using a CO ₂ laser processing method or a plasma processing method. A first via hole and a second via hole having a larger diameter than the first via hole are formed, and are formed by substantially coinciding the centers of the first via hole and the second via hole.

According to the present invention, the hole formation for electrically connecting the layers stacked in the multilayer printed circuit board is minimized, so that the design of the circuit pattern is easy and the signal lines are straightened, so that the signal transmission is made accurately, and the fine circuit pattern is formed. This is advantageous in that the wiring density and the mounting density can be increased.

Hereinafter, a preferred embodiment of a multilayer printed circuit board and a method of manufacturing the same according to the present invention having the configuration as described above will be described in detail with reference to the accompanying drawings.

3 shows a cross section of a preferred embodiment of a printed circuit board manufactured by the method according to the invention.

According to this, the printed circuit board 100 manufactured according to the present invention is largely divided into a core layer 101, an upper buildup layer 130, and a lower buildup layer 130 ′.

The core layer 101 is composed of a plurality of resin layers 102 and a copper thin film layer 104. That is, the resin layer 102 and the copper thin film layer 104 are sequentially stacked. The through hole 106 is drilled through the core layer 101 up and down. An inner plating layer 106a is formed on an inner wall of the through hole 106, and an outer plating layer 106b is formed on upper and lower surfaces of the core layer 101 continuously with the inner plating layer 106a. An insulating resin 107 is filled in the through hole 106.

In addition, the insulating resin 107 corresponding to the upper and lower surfaces of the through hole 106 is electrically connected to the outer plating layer 106b, and thereafter, for electrical connection with the upper and lower build-up layers 130 and 130 '. The connecting thin film layer 108 is formed. Here, the inside of the through hole 106 may be filled with a conductive paste. In this case, the connection thin film layer 108 may not be formed separately.

On the upper and lower surfaces of the core layer 101 having the above configuration, the upper and lower buildup layers 130 and 130 'are respectively formed.

The phase build-up layer 130 is formed on an upper surface of the core layer 101, and an insulating resin layer 132 is formed on an upper surface of the core layer 101. The plating layer 134 is formed on the surface of the insulating resin layer 132.

In addition, another insulating resin layer 132 ′ is formed on the plating layer 134. In addition, a separate plating layer may be further formed on the insulating resin layer 132 ′ as needed, and an insulating resin layer and a plating layer may be sequentially formed as necessary. In this embodiment, the phase-up layer 130 is composed of two layers.

First and second holes 136 and 137 are formed in the insulating layer 132 and 132 ′, respectively, in the phase-up layer 130. The first and second holes 136 and 137 are formed to have different diameters, but they may be formed identically according to design conditions. A metal thin film layer 138 is formed on the surface of the insulating resin layer 132 ′ and the inner surfaces of the first and second holes 136 and 137. The metal thin film layer 138 is electrically connected to and in contact with the connection thin film layer 108 of the core layer 101.

On the other hand, since the configuration is similar to that of the build-up layer 130 ′, the separate description is omitted and the same reference numerals as those of the phase-up layer 130. Shown using.

The manufacturing process of the multilayered printed circuit board 100 according to the present invention having such a configuration will be described in detail with reference to FIGS. 3 and 4.

In the manufacturing method of the present invention, first, the core layer 101 is formed. The core layer 101 may be formed by using the resin layer 102 coated with the copper thin film layer 104 alone, or after forming a circuit through an exposure, etching, and peeling process, and stacking a plurality of sheets with an insulating resin therebetween. Form. 3 shows a four-layer core layer 101.

As described above, after the plurality of copper thin film layers 104 are formed to form the core layer 101, the through holes 106 penetrating the core layer 101 are formed. At this time, the through hole 106 is drilled through drilling by a computer numerical control method. As described above, after drilling the through hole 106, smears generated by high heat during the drilling process in the drilling hole in the drilling process, which adversely affects the connection reliability during plating, are chemically removed. Done.

After removing the smear as described above, the upper and lower surfaces of the core layer 101 and the inside of the through hole 104 are plated to form the inner plating layer 106a and the outer plating layer 106b, respectively. At this time, the inner plating layer 106a and the outer plating layer 106b are in a state of being electrically connected to the copper thin film layer 104 inside the core layer 101.

After the inner and outer plating layers 106a and 106b are formed as described above, the inside of the through hole 106 is filled with the insulating resin 107. The reason why the inside of the through-hole 106 is filled with the insulating resin 107 is that when a space exists in the through-hole 106, cracks are minutely generated due to temperature change, which affects the reliability of the printed circuit board. Because.

Next, copper plating is performed on upper and lower surfaces of the core layer 101 to form a connection thin film layer 108. The connection thin film layer 108 may be electrically connected to the upper and lower build-up layers 130 and 130 ′. If necessary, the inside of the through hole 106 may be filled with a conductive paste. In this case, the connection thin film layer 108 may not be formed as described above.

Next, after the surface of the connection thin film layer 108 is even, a dry film is applied to the upper and lower surfaces of the substrate. Then, etching is performed through a normal exposure and development process. At this time, when the dry film is maintained at the portion where the circuit is to be formed, and the dry film is removed at the other portion in the developing process, the etched portion is in a state where the copper plating is removed and the resin material is exposed.

After the circuit pattern is formed on the connection thin film layer 108 as described above, the adhesion between the core layer 101 and the upper and lower build-up layers 130 and 130 'is improved before the upper and lower build-up layers 130 and 130' are formed. In order to oxidize the surface using black oxide (black oxide). Then, the upper and lower build-up layers 130 and 130 'are formed.

First, the insulating resin layer 132 is formed of a photosensitive insulating resin or a thermosetting insulating resin in a liquid or solid state. In this case, the insulating resin layer 132 is formed on the connection thin film layer 108 by using a lamination press method or by thermal laminating or printing. In this case, if a liquid insulating resin is used, a surface polishing process is performed to polish the surface in order to maintain a constant thickness after forming an insulating layer regardless of photosensitivity and thermosetting. And in the case of liquid insulating resin, the surface area should be increased before plating to improve the adhesive strength regardless of photosensitivity and thermosetting. Therefore, after the polishing process to make the thickness of the substrate constant, the surface is roughened to improve the adhesion of the subsequent plating layer.

Then, copper plating is performed on the insulating resin layer 132 to form a metal thin film layer 134. This state is shown in FIG. 4A.

After the operation of evening the plated surface of the metal thin film layer 134 is performed, conventional exposure, development, and etching are performed to form a circuit pattern. In this case, the plating layer 134 is removed at the position where the first hole 136 is formed to expose the insulating resin layer 132. This state is shown in FIG. 4B.

Meanwhile, in order to form two stages of the upper and lower build-up layers 130 and 130 ', an insulating resin layer 132' is formed on the plating layer 134 and a polishing process is performed. This state is shown in FIG. 4C.

Next, first and second holes 136 and 137 are formed through the insulating resin layers 132 and 132 'of the upper and lower build-up layers 130 and 130'. The holes 136 and 137 are formed through photo via processing. The first and second holes 136 and 137 are formed at the same time in one process. At this time, the center of the first and second holes (136, 137) is approximately the same as the center of the through hole 106 is the best wiring density. This state is shown in FIG. 4D. For reference, the diameters of the first and second holes 136 and 137 may be the same.

Then, a surface roughening process for increasing the surface area of the insulating resin layer 132 ′ and the first and second holes 136 and 136 ′ is performed, and copper plating is performed on the surface to form the metal thin film layer 138. The metal thin film layer 138 is electrically connected to the metal thin film layer 134 and the connection thin film layer 108. This state is shown in FIG. 4E. In addition, a circuit pattern is formed on the metal thin film layer 138 through exposure, development, and etching processes.

In addition, a solder resist is applied to the upper and lower surfaces of the substrate, dried, exposed, developed to form a PSR, and a part where a lead or a ball of a component mounted on the printed circuit board 100 is mounted. Gold plating, flux, hole, etc. prevents the circuit pattern from being oxidized and improves adhesion when mounting parts.

5 illustrates a case in which a raw material (RCC: Resin Coated Copper) having a state in which the metal thin film layer 134 'is previously attached to the insulating resin layer 132' is shown. In this case, after the core layer 101 is formed, the raw materials in the state in which the metal thin film layers 134 and 134 'are bonded are laminated, and a circuit pattern is formed in the metal thin film layers 134 and 134' by a conventional etching method. At the same time, the metal thin film layers 134 and 134 ′ of the portions where the first holes 136 and the second holes 137 are to be formed are removed. Thereafter, the first and second holes 136 and 137 are formed, and impurities are removed therein, and then the metal thin film layer 138 'is formed on the metal thin film layer 134' and the first and second holes 136 and 137. . The metal thin film layer 138 ′ is electrically connected to the connection thin film layer 108 and the metal thin film layers 134 and 134 ′. A circuit pattern is formed on the metal thin film layer 138 '. The first and second holes 136 and 137 may be formed by removing the metal thin film layers 134 and 134 'by their respective diameters, and removing the insulating resin layers 132 and 132' by carbon dioxide laser processing and plasma processing, respectively. Will remove impurities.

On the other hand, the diameter of the second hole 137 is larger than the first hole 136, when forming a plurality of the first and second holes, the first hole 136 after processing the second hole after processing these In order to correct the positional deviation between them, even if the position of a 1st hole and a 2nd hole shifts slightly, it is possible to substantially match the position of a 1st, 2nd hole.

In the present embodiment it has been used for the first and second holes (136 137) simultaneously removing the available port via (photo via) of the plate layer 134 and the insulating resin layer 132 to form a processing method, in addition to CO ₂ Laser processing, plasma processing, and yag laser processing. In the yag laser processing method, the plating layer 134 and the insulating resin layer 132 may be removed at the same time. However, when the CO ₂ laser processing method and the plasma processing method are used, the plating layer 134 should be removed in advance.

Therefore, when the CO ₂ laser processing method and the plasma processing method are used, when the circuit pattern is formed by etching, the plating layer 134 of the portion where the first hole 136 is located is simultaneously removed and the insulating resin layer 132 is exposed. In this state, when the build-up layer is multistage, the insulating resin layer 132 ′ is formed again. Therefore, the insulating resin layers 132 and 132 'are connected to each other at the portion of the insulating resin layer 132 exposed by removing the plating layer 134, that is, the portion where the first hole 136 is to be located. Subsequently, the outermost plating layer 134 'is formed on the insulating resin layer 132', and during the etching for forming the circuit pattern, the plating layer 134 'is removed by the diameter of the second hole 137 and the CO ₂ is removed. The first and second holes 136 and 137 are formed by using a laser processing method or a plasma processing method, and the metal thin film layer 138 is formed after removing impurities.

On the other hand, the upper, lower build-up layer (130, 130 ') is not necessarily both formed, either may be formed depending on the design conditions. In addition, the number of layers of each of the upper and lower build-up layers 130 and 130 'may be formed in several layers by repeating the above process as necessary.

According to the method of manufacturing a printed circuit board according to the present invention as described in detail above, in a multilayer printed circuit board in which electrical connection between layers is required, through-holes are formed in the core layer with a computer numerical control drill, and the upper and lower portions of the core layer. Since the upper and lower build-up layers are formed in the upper part, the through-hole penetrating the entire printed circuit board is not required, thereby reducing the unnecessary area of the component mounting part to a minimum, thereby increasing the mounting density.

In addition, according to the connection structure between the stacked layers, unnecessary holes and lands can be eliminated, so that the linear design of the circuit can be easily performed, thereby speeding up the signal, and reducing the size and weight of the substrate. The effect is much simpler.

In addition, when the photo via processing is performed, the thickness of the metal thin film layer on the surface of the insulating resin layer becomes thinner, and thus the overall thickness of the metal thin film layer on which the circuit pattern is formed becomes thinner than the case of two to three layers. There is also an effect that can minimize the erosion generated at the time to form a fine circuit pattern.

Claims (11)

delete delete delete delete delete delete delete Manufacturing a core layer by sequentially stacking a plurality of first insulators and a first conductive thin film, Forming a through hole through the insulator of the core layer and the conductive thin film, and forming a conductive layer electrically connecting the conductive thin film; Forming a connection thin film layer interconnecting the conductive layers of the through hole; Stacking at least one second insulator and a second conductive thin film successively on the first conductive thin film exposed on the surface of the core layer; A via layer penetrating the second insulator and the second conductive thin film is formed above the connection thin film layer corresponding to the upper portion of the through hole, and a conductive layer electrically connecting the connection thin film layer and the second conductive thin film to the via hole. Method of manufacturing a multilayer printed circuit board, characterized in that it comprises a step of forming. The method of claim 8, wherein the via hole penetrating the second insulator and the second conductive thin film is formed by a photo via processing method. 10. The via hole of claim 8, wherein the via hole penetrating the second insulator and the second conductive thin film is formed by etching a circuit pattern on the second conductive thin film, thereby forming the second conductive thin film at the position where the via hole is formed by the diameter of the via hole. And removing the second insulator by using a CO ₂ laser processing method or a plasma processing method. The multilayer printing of claim 8, wherein the via hole comprises a first via hole and a second via hole having a diameter larger than that of the first via hole, and is formed by substantially coinciding the centers of the first via hole and the second via hole. Method of manufacturing a circuit board.