JPH11261236A - Multi-layer printed wiring board and manufacture thereof - Google Patents
Multi-layer printed wiring board and manufacture thereofInfo
- Publication number
- JPH11261236A JPH11261236A JP7482098A JP7482098A JPH11261236A JP H11261236 A JPH11261236 A JP H11261236A JP 7482098 A JP7482098 A JP 7482098A JP 7482098 A JP7482098 A JP 7482098A JP H11261236 A JPH11261236 A JP H11261236A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- layer
- circuit pattern
- inner layer
- build
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【発明が属する産業分野】本発明は多層プリント配線板
およびその製造方法に関し、さらに詳しくはビルドアッ
プ法を用いた多層プリント配線板の層間の導通構造に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer printed wiring board and a method of manufacturing the same, and more particularly, to a conductive structure between layers of a multilayer printed wiring board using a build-up method.
【０００２】[0002]
【従来の技術】多層プリント配線板において内層材であ
るコア材に設けられたスル−ホ−ルを利用して複数層間
の接続を行う場合、例えば図４のような製造方法がとら
れている。すなわち、図４（ａ）および図４（ｂ）のよ
うに、銅箔３０ａを絶縁基材３０ｂの両面に形成した両
面銅張積層板をコア材３０に用い、このコア材３０に貫
通孔３１をドリルであけ、コア材３０の両面およびスル
−ホ−ル３１内に銅メッキ３２を施した後（図４
（ｃ））に写真法や印刷法などにより接続用ランド３３
ａを含む回路パターン３３を形成する。次に絶縁性のビ
ルドアップ層３４をコア材３０の表裏両面に形成した後
（図４（ｄ））、ビルドアップ層３４に回路パタ−ン３
３の接続用ランド３３ａに達するバイアホ−ル３５を設
け（図４（ｅ））、ビルドアップ層３４の表面およびバ
イアホ−ル３５内に銅メッキ３６を施し（図４
（ｆ））、その後銅メッキ３６をエッチングして回路パ
タ−ン３７を形成している（図４（ｇ））。2. Description of the Related Art In a multilayer printed wiring board, when a plurality of layers are connected using a through hole provided in a core material as an inner layer material, a manufacturing method as shown in FIG. 4 is employed. . That is, as shown in FIGS. 4A and 4B, a double-sided copper-clad laminate in which a copper foil 30a is formed on both sides of an insulating base material 30b is used as a core material 30, and a through hole 31 is formed in the core material 30. Is drilled, and copper plating 32 is applied to both surfaces of the core material 30 and the through-hole 31 (FIG. 4).
(C)) The connection land 33 is formed by a photographic method or a printing method.
A circuit pattern 33 including a is formed. Next, after an insulating build-up layer 34 is formed on both front and back surfaces of the core material 30 (FIG. 4D), a circuit pattern 3 is formed on the build-up layer 34.
A via hole 35 reaching the connection land 33a of No. 3 is provided (FIG. 4E), and a copper plating 36 is applied to the surface of the build-up layer 34 and the inside of the via hole 35 (FIG. 4).
(F)) Thereafter, the copper plating 36 is etched to form a circuit pattern 37 (FIG. 4 (g)).
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、この方
法では、内層材のスル−ホ−ル３１とビルドアップ層３
４のバイアホ−ル３５を同じ位置に設けることができな
いので、接続用ランド３３ａや接続用ランド３３ａまで
のラインなどの余分な回路を必要とする。そのためプリ
ント配線板の高密度化、小型化を図ることができないと
いう欠点があった。In this method, however, the through-hole 31 and the build-up layer 3 of the inner layer material are not provided.
Since the four via holes 35 cannot be provided at the same position, extra circuits such as connection lands 33a and lines to the connection lands 33a are required. For this reason, there is a drawback that the printed wiring board cannot be made dense and compact.
【０００４】本発明は、内層材のホ−ルとビルトアップ
層のホ−ルを同じ位置に設けることができ、高密度化、
小型化を図ることができるプリント配線板およびその製
造方法を提供することを目的としている。According to the present invention, the hole of the inner layer material and the hole of the built-up layer can be provided at the same position, so that the density can be increased.
It is an object of the present invention to provide a printed wiring board that can be downsized and a method for manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】本発明の多層プリント配
線板は、絶縁基材の両面に積層された金属箔に回路パタ
−ンが形成されている内層材と、この内層材の両面に形
成されたビルドアップ層とを具備し、内層材にはその一
方の面の回路パタ−ンから他方の面の回路パターンにま
で達するが貫通していない金属メッキされた第一の非貫
通孔が設けられ、さらに内層材の他方の面側のビルドア
ップ層には第一の非貫通孔と同じ位置に、ビルドアップ
層の表面から内層材の他方の面の回路パタ−ンにまで達
する金属メッキされた第二の非貫通孔が設けられている
ことを特徴とする。SUMMARY OF THE INVENTION A multilayer printed wiring board according to the present invention comprises an inner layer material in which a circuit pattern is formed on a metal foil laminated on both sides of an insulating base material, and an inner layer material formed on both sides of the inner layer material. And a metal-plated first non-through hole which extends from the circuit pattern on one side to the circuit pattern on the other side but does not penetrate the inner layer material. Further, the build-up layer on the other surface side of the inner layer material is metal-plated at the same position as the first non-through hole from the surface of the build-up layer to the circuit pattern on the other surface of the inner layer material. Characterized in that a second non-through hole is provided.
【０００６】なお、内層材の両面から互いに逆方向に、
一方の面の回路パタ−ンから他方の面の回路パターンに
それぞれ達するが貫通していない金属メッキされた第一
の非貫通孔が設けられ、さらに両ビルドアップ層には第
一の非貫通孔とそれぞれ同じ位置に、ビルドアップ層の
表面から内層材の他方の面の回路パタ−ンに達する金属
メッキされた第二の非貫通孔がそれぞれ設けられてもよ
い。In addition, from both sides of the inner layer material,
A first metal-plated non-penetrating hole is provided from the circuit pattern on one side to the circuit pattern on the other side but not penetrating, and the first non-penetrating hole is provided in both build-up layers. And metal-plated second non-through holes extending from the surface of the build-up layer to the circuit pattern on the other surface of the inner layer material may be provided at the same positions.
【０００７】また本発明の多層プリント配線板の製造方
法は、絶縁基材の両面に金属箔が積層されている内層材
の少なくとも片面の金属箔を化学的またはレ−ザーなど
により部分的に除去し、露出した絶縁基材に他方の面の
金属箔に達する第一の非貫通孔をレ−ザーなどにて設け
た後、内層材の両面および第一の非貫通孔内に金属メッ
キ層を形成し、内層材の金属箔および金属メッキ層に回
路パターンをそれぞれ形成した後、内層材の両面に絶縁
性のビルドアップ層を形成し、このビルドアップ層には
第一の非貫通孔と同じ位置に第一の非貫通孔と反対方向
から内層材の回路パターンにまで達する第二の非貫通孔
を設けた後、ビルドアップ層上および第二の非貫通孔内
に金属メッキ層を形成することを特徴とする。Further, according to the method of manufacturing a multilayer printed wiring board of the present invention, at least one side of the metal foil of the inner layer material in which the metal foil is laminated on both sides of the insulating base material is partially removed by chemical or laser. Then, after a first non-through hole reaching the metal foil on the other surface is provided by a laser or the like on the exposed insulating base material, a metal plating layer is formed on both surfaces of the inner layer material and in the first non-through hole. After forming and forming a circuit pattern on the metal foil and metal plating layer of the inner layer material, an insulating build-up layer is formed on both surfaces of the inner layer material, and this build-up layer has the same shape as the first non-through hole. After providing a second non-through hole at a position from the direction opposite to the first non-through hole to the circuit pattern of the inner layer material, a metal plating layer is formed on the build-up layer and in the second non-through hole. It is characterized by the following.
【０００８】[0008]
【発明の実施の形態】図１（ａ）において絶縁基材１の
両面に銅箔２ａ、２ｂ（厚さ例えば１２μｍ〜３５μ
ｍ）が積層されている内層材であるコア材（厚さ例えば
０．１ｍｍ〜０．３ｍｍ）３の銅箔２ｂをエッチングに
より部分的に除去して、絶縁基材１１を露出させ、すな
わち除去部分４ｂを形成する（図１（ｂ））。コア材２
としては例えばガラスエポキシ基板、ガラスポリイミド
基板、ガラスフッ素樹脂基板、ＢＴ（ビスマレ−トトリ
アジン）−レジン基板、紙フェノ−ル基板などが使用で
きる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In FIG. 1A, copper foils 2a and 2b (thickness of, for example,
m), the copper foil 2b of the core material (thickness of, for example, 0.1 mm to 0.3 mm) 3 as an inner layer material is partially removed by etching to expose the insulating base material 11, that is, removal. A portion 4b is formed (FIG. 1B). Core material 2
For example, a glass epoxy substrate, a glass polyimide substrate, a glass fluororesin substrate, a BT (bismaletotriazine) -resin substrate, a paper phenol substrate and the like can be used.
【０００９】次に除去部分４ｂにレ−ザ−を用いて他方
の面の銅箔２ａに達するが貫通していない非貫通孔（非
貫通スル−ホ−ル、第一の非貫通孔）５ｂを設ける（図
１（ｃ））。レ−ザ−の他、プラズマを使用したり、サ
ンドブラスト法によってもよい。レ−ザ−の場合、例え
ばエキシマレ−ザ−、ＣＯ2 レ−ザ−、ＹＡＧレ−ザ−
などを使用できる。非貫通孔５ｂの直径は例えば０．１
ｍｍ〜０．３ｍｍぐらいになされる。Next, a non-through hole (a non-through hole, a first non-through hole) 5b which reaches the copper foil 2a on the other surface but does not penetrate, using a laser for the removed portion 4b. Is provided (FIG. 1C). In addition to a laser, a plasma may be used or a sand blast method may be used. Les - The - if, for example excimer - The -, CO 2 Les - The -, YAG Les - The -
Etc. can be used. The diameter of the non-through hole 5b is, for example, 0.1.
mm to 0.3 mm.
【００１０】このようなコア材３の両面に銅メッキ層６
ａ、６ｂ（厚さ例えば１０μｍ〜３０μｍ）を形成し
（図１（ｄ））、この銅メッキ層６ａ、６ｂおよび銅箔
２ａ、２ｂをフォトレジスト法などを用いてエッチング
し、回路パターン７ａ、７ｂをそれぞれ形成する。その
後、コア材３の両面に絶縁性のビルドアップ層８ａ、８
ｂを形成する（図１（ｅ））。このビルドアップ層８
ａ、８ｂとしてはエポキシ樹脂、ＢＴ−レジン、熱硬化
ＰＰＥ（ポリフェニレンエ−テル）樹脂などを使用でき
る。ビルドアップ層８ａ、８ｂの形成は、樹脂コ−ティ
ング、積層プレス、ラミネ−ト法などにより行われる。The copper plating layers 6 are formed on both surfaces of the core material 3.
a, 6b (thickness, for example, 10 μm to 30 μm) are formed (FIG. 1D), and the copper plating layers 6a, 6b and the copper foils 2a, 2b are etched by using a photoresist method or the like to form a circuit pattern 7a, 7b are formed. Thereafter, insulating build-up layers 8a and 8
b is formed (FIG. 1E). This build-up layer 8
As a and 8b, an epoxy resin, BT-resin, thermosetting PPE (polyphenylene ether) resin or the like can be used. The build-up layers 8a and 8b are formed by a resin coating, a lamination press, a lamination method, or the like.
【００１１】ビルドアップ層８ａの上記非貫通孔５ｂと
同じ位置に非貫通孔５ｂと反対方向からコア材３の回路
パターン７ａにまで達する直径が例えば０．１〜０．３
ｍｍぐらいの非貫通孔（バイアホ−ル、第二の非貫通
孔）９ａを設ける（図１（ｆ））。この場合、上述した
レ−ザ−、プラズマ、サンドブラスト法などの他、感光
性樹脂を使用した写真法によって非貫通孔９ａを設けて
もよい。その後、ビルドアップ層８ａ、８ｂ上に銅メッ
キ層１０ａ、１０ｂ（厚さ例えば１０μｍ〜３０μｍ）
を形成し（図１（ｇ））さらに銅メッキ層１０ａ、１０
ｂをエッチングして回路パタ−ン１１ａ、１１ｂとする
（図２）。The diameter reaching the circuit pattern 7a of the core material 3 from the opposite direction to the non-through hole 5b at the same position as the non-through hole 5b in the build-up layer 8a is, for example, 0.1 to 0.3.
A non-through hole (via hole, second non-through hole) 9a of about mm is provided (FIG. 1 (f)). In this case, the non-through-hole 9a may be provided by a photographic method using a photosensitive resin, in addition to the above-described laser, plasma, and sand blast methods. Then, copper plating layers 10a and 10b (thickness, for example, 10 μm to 30 μm) are formed on the build-up layers 8a and 8b.
Is formed (FIG. 1 (g)).
b is etched to form circuit patterns 11a and 11b (FIG. 2).
【００１２】なお図１および図２では、非貫通孔５ｂを
内層材の片面側からのみ形成したが、図３のように非貫
通孔（第一の非貫通孔）５ａ、５ｂをコア材３の両面か
らそれぞれ設け、非貫通孔（第二の非貫通孔）９ａ、９
ｂをビルドアップ層８ａ、８ｂにそれぞれ設けてもよ
い。この場合、両方の非貫通孔５ａ、５ｂは同一位置に
ならないよう互いにずらして形成される。In FIGS. 1 and 2, the non-through holes 5b are formed only from one side of the inner layer material, but the non-through holes (first non-through holes) 5a and 5b are Non-through holes (second non-through holes) 9a, 9
b may be provided on each of the build-up layers 8a and 8b. In this case, both non-through holes 5a and 5b are formed shifted from each other so as not to be at the same position.
【００１３】[0013]
【発明の効果】本発明の多層プリント配線板およびその
製造方法では、内層材の非貫通孔（非貫通スル−ホ−
ル）とビルドアップ層の非貫通孔（バイアホ−ル）を同
じ位置に設けることができ、高密度化、小型化を図るこ
とができる。According to the multilayer printed wiring board and the method of manufacturing the same of the present invention, the non-through hole (non-through through hole) of the inner layer material is provided.
) And the non-through hole (via hole) of the build-up layer can be provided at the same position, and higher density and smaller size can be achieved.
【図１】本発明の多層プリント配線板の製造方法を説明
する図。FIG. 1 is a diagram illustrating a method for manufacturing a multilayer printed wiring board according to the present invention.
【図２】本発明の多層プリント配線板を示す図。FIG. 2 is a diagram showing a multilayer printed wiring board according to the present invention.
【図３】本発明による別の多層プリント配線板を示す
図。FIG. 3 is a diagram showing another multilayer printed wiring board according to the present invention.
【図４】従来の多層プリント配線板の製造方法を説明す
る図。FIG. 4 is a diagram illustrating a conventional method for manufacturing a multilayer printed wiring board.
１ 絶縁基材 ２ａ 金属箔層（銅箔） ２ｂ 金属箔層（銅箔） ３ コア材（内層材） ４ｂ 除去部分 ５ａ 非貫通孔（第一の非貫通孔） ５ｂ 非貫通孔（第一の非貫通孔） ６ａ 金属メッキ層（銅メッキ層） ６ｂ 金属メッキ層（銅メッキ層） ７ａ 回路パタ−ン ７ｂ 回路パタ−ン ８ａ ビルドアップ層 ８ｂ ビルドアップ層 ９ａ 非貫通孔（第二の非貫通孔） ９ｂ 非貫通孔（第二の非貫通孔） １０ａ 銅メッキ層 １０ｂ 銅メッキ層 １１ａ 回路パタ−ン １１ｂ 回路パタ−ン Reference Signs List 1 insulating base material 2a metal foil layer (copper foil) 2b metal foil layer (copper foil) 3 core material (inner layer material) 4b removed portion 5a non-through hole (first non-through hole) 5b non-through hole (first 6a Metal plating layer (copper plating layer) 6b Metal plating layer (copper plating layer) 7a Circuit pattern 7b Circuit pattern 8a Build-up layer 8b Build-up layer 9a Non-through hole (second non-through hole) Hole 9b Non-through hole (second non-through hole) 10a Copper plating layer 10b Copper plating layer 11a Circuit pattern 11b Circuit pattern
Claims (4)
パタ−ンが形成されている内層材と、この内層材の両面
に形成されたビルドアップ層とを具備し、内層材にはそ
の一方の面の回路パタ−ンから他方の面の回路パターン
にまで達するが貫通していない金属メッキされた第一の
非貫通孔が設けられ、さらに内層材の他方の面側のビル
ドアップ層には第一の非貫通孔と同じ位置に、ビルドア
ップ層の表面から内層材の他方の面の回路パタ−ンにま
で達する金属メッキされた第二の非貫通孔が設けられて
いることを特徴とする多層プリント配線板。1. An inner layer material having a circuit pattern formed on a metal foil laminated on both surfaces of an insulating base material, and a build-up layer formed on both surfaces of the inner layer material. Is provided with a first metal-plated non-through hole that extends from the circuit pattern on one side to the circuit pattern on the other side but does not penetrate, and further builds up on the other side of the inner layer material. The layer has a metal-plated second non-through hole extending from the surface of the build-up layer to the circuit pattern on the other surface of the inner layer material at the same position as the first non-through hole. A multilayer printed wiring board characterized by the following.
パタ−ンが形成されている内層材と、この内層材の両面
に形成されたビルドアップ層とを具備し、内層材にはそ
の両面から互いに逆方向に、一方の面の回路パタ−ンか
ら他方の面の回路パターンにそれぞれ達するが貫通して
いない金属メッキされた第一の非貫通孔が設けられ、さ
らに、両ビルドアップ層には第一の非貫通孔とそれぞれ
同じ位置に、ビルドアップ層の表面から内層材の他方の
面の回路パタ−ンに達する金属メッキされた第二の非貫
通孔がそれぞれ設けられていることを特徴とする多層プ
リント配線板。2. An inner layer material having a circuit pattern formed on a metal foil laminated on both surfaces of an insulating base material, and a build-up layer formed on both surfaces of the inner layer material. A metal-plated first non-penetrating hole, which extends from the circuit pattern on one side to the circuit pattern on the other side, but does not penetrate, is provided in opposite directions from both sides thereof. At the same position as the first non-through hole in the up layer, there are provided second metal-plated non-through holes that reach the circuit pattern on the other surface of the inner layer material from the surface of the build-up layer, respectively. A multilayer printed wiring board.
内層材の少なくとも片面の金属箔を部分的に除去し、露
出した絶縁基材に他方の面の金属箔に達する第一の非貫
通孔を設けた後、内層材の両面および第一の非貫通孔内
に金属メッキ層を形成し、内層材の金属箔および金属メ
ッキ層に回路パターンをそれぞれ形成した後、内層材の
両面に絶縁性のビルドアップ層を形成し、このビルドア
ップ層には第一の非貫通孔と同じ位置に第一の非貫通孔
と反対方向から内層材の回路パターンにまで達する第二
の非貫通孔を設けた後、ビルドアップ層上および第二の
非貫通孔内に金属メッキ層を形成することを特徴とする
多層プリント配線板の製造方法。3. A method according to claim 1, wherein the metal foil on at least one side of the inner layer material in which the metal foil is laminated on both surfaces of the insulating base is partially removed, and the exposed insulating base reaches the metal foil on the other side. After providing a non-through hole, a metal plating layer is formed on both surfaces of the inner layer material and in the first non-through hole, and a circuit pattern is formed on the metal foil and the metal plating layer of the inner layer material, respectively. An insulating build-up layer is formed on the second non-penetrating layer which reaches the circuit pattern of the inner layer material from the opposite direction to the first non-penetrating hole at the same position as the first non-penetrating hole. A method of manufacturing a multilayer printed wiring board, comprising: forming a metal plating layer on a build-up layer and in a second non-through hole after providing a hole.
内層材の少なくとも片面の金属箔を部分的に除去し、露
出した絶縁層にレ−ザ−にて他方の面の金属箔に達する
第一の非貫通孔を設けた後、内層材の両面および第一の
非貫通孔内に金属メッキ層を形成し、内層材の金属箔お
よび金属メッキ層に回路パターンをそれぞれ形成した
後、内層材の両面に絶縁性のビルドアップ層を形成し、
このビルドアップ層には第一の非貫通孔と同じ位置に第
一の非貫通孔と反対方向から内層材の回路パターンにま
で達する第二の非貫通孔を設けた後、ビルドアップ層上
および第二の非貫通孔内に金属メッキ層を形成すること
を特徴とする多層プリント配線板の製造方法。4. The metal foil on at least one side of the inner layer material in which the metal foil is laminated on both sides of the insulating base material is partially removed, and the exposed insulating layer is covered with a metal foil on the other side by a laser. After the first non-through hole is reached, a metal plating layer is formed on both surfaces of the inner layer material and in the first non-through hole, and a circuit pattern is formed on the metal foil and the metal plating layer of the inner layer material, respectively. , Forming an insulating build-up layer on both sides of the inner layer material,
After providing a second non-through hole reaching the circuit pattern of the inner layer material from the opposite direction to the first non-through hole in the build-up layer at the same position as the first non-through hole, on the build-up layer and A method for manufacturing a multilayer printed wiring board, comprising forming a metal plating layer in a second non-through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7482098A JPH11261236A (en) | 1998-03-09 | 1998-03-09 | Multi-layer printed wiring board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7482098A JPH11261236A (en) | 1998-03-09 | 1998-03-09 | Multi-layer printed wiring board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11261236A true JPH11261236A (en) | 1999-09-24 |
Family
ID=13558344
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7482098A Pending JPH11261236A (en) | 1998-03-09 | 1998-03-09 | Multi-layer printed wiring board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11261236A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001308529A (en) * | 2000-04-21 | 2001-11-02 | Ibiden Co Ltd | Laminated wiring board and its manufacturing method |
| WO2003009661A1 (en) * | 2001-07-12 | 2003-01-30 | Meiko Electronics Co., Ltd. | Core substrate, and multilayer circuit board using it |
| JP2003046249A (en) * | 2001-08-02 | 2003-02-14 | Ibiden Co Ltd | Lamination wiring board and its manufacturing method |
| JP2003218490A (en) * | 2002-01-24 | 2003-07-31 | Sharp Corp | Printed wiring board and its manufacturing method |
| WO2005036940A1 (en) * | 2003-10-09 | 2005-04-21 | Qualcomm Incorporated | Telescoping blind via in three-layer core |
| JP2006041378A (en) * | 2004-07-29 | 2006-02-09 | Toshiba Corp | Multilayer printed circuit board, manufacturing method thereof, and electronic device |
| CN111278217A (en) * | 2018-12-04 | 2020-06-12 | 三星电机株式会社 | Printed circuit board and method of manufacturing the same |
-
1998
- 1998-03-09 JP JP7482098A patent/JPH11261236A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001308529A (en) * | 2000-04-21 | 2001-11-02 | Ibiden Co Ltd | Laminated wiring board and its manufacturing method |
| WO2003009661A1 (en) * | 2001-07-12 | 2003-01-30 | Meiko Electronics Co., Ltd. | Core substrate, and multilayer circuit board using it |
| JP2003046249A (en) * | 2001-08-02 | 2003-02-14 | Ibiden Co Ltd | Lamination wiring board and its manufacturing method |
| JP2003218490A (en) * | 2002-01-24 | 2003-07-31 | Sharp Corp | Printed wiring board and its manufacturing method |
| WO2005036940A1 (en) * | 2003-10-09 | 2005-04-21 | Qualcomm Incorporated | Telescoping blind via in three-layer core |
| US7402758B2 (en) | 2003-10-09 | 2008-07-22 | Qualcomm Incorporated | Telescoping blind via in three-layer core |
| JP2006041378A (en) * | 2004-07-29 | 2006-02-09 | Toshiba Corp | Multilayer printed circuit board, manufacturing method thereof, and electronic device |
| CN111278217A (en) * | 2018-12-04 | 2020-06-12 | 三星电机株式会社 | Printed circuit board and method of manufacturing the same |
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