JPH11250408A - 遅延量校正回路及び方法 - Google Patents

遅延量校正回路及び方法

Info

Publication number
JPH11250408A
JPH11250408A JP10046610A JP4661098A JPH11250408A JP H11250408 A JPH11250408 A JP H11250408A JP 10046610 A JP10046610 A JP 10046610A JP 4661098 A JP4661098 A JP 4661098A JP H11250408 A JPH11250408 A JP H11250408A
Authority
JP
Japan
Prior art keywords
delay
signal
delay line
nlts
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10046610A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11250408A5 (enExample
Inventor
Hisakado Hirasaka
久門 平坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Japan Inc
Original Assignee
Hewlett Packard Japan Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Japan Inc filed Critical Hewlett Packard Japan Inc
Priority to JP10046610A priority Critical patent/JPH11250408A/ja
Priority to US09/258,253 priority patent/US6127869A/en
Publication of JPH11250408A publication Critical patent/JPH11250408A/ja
Publication of JPH11250408A5 publication Critical patent/JPH11250408A5/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10009—Improvement or modification of read or write signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/36—Monitoring, i.e. supervising the progress of recording or reproducing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B2005/0002—Special dispositions or recording techniques
    • G11B2005/0005—Arrangements, methods or circuits
    • G11B2005/001—Controlling recording characteristics of record carriers or transducing characteristics of transducers by means not being part of their structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B33/00—Constructional parts, details or accessories not provided for in the other groups of this subclass
    • G11B33/10—Indicating arrangements; Warning arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/012—Recording on, or reproducing or erasing from, magnetic disks
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
    • G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
    • G11B5/09—Digital recording

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Digital Magnetic Recording (AREA)
JP10046610A 1998-02-27 1998-02-27 遅延量校正回路及び方法 Withdrawn JPH11250408A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10046610A JPH11250408A (ja) 1998-02-27 1998-02-27 遅延量校正回路及び方法
US09/258,253 US6127869A (en) 1998-02-27 1999-02-25 Circuit for calibrating delay lines and method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10046610A JPH11250408A (ja) 1998-02-27 1998-02-27 遅延量校正回路及び方法

Publications (2)

Publication Number Publication Date
JPH11250408A true JPH11250408A (ja) 1999-09-17
JPH11250408A5 JPH11250408A5 (enExample) 2005-08-25

Family

ID=12752084

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10046610A Withdrawn JPH11250408A (ja) 1998-02-27 1998-02-27 遅延量校正回路及び方法

Country Status (2)

Country Link
US (1) US6127869A (enExample)
JP (1) JPH11250408A (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100317317B1 (ko) * 1998-12-31 2002-01-16 김영환 반도체입력장치의셋업/홀드타임제어회로
JP3870333B2 (ja) * 2000-11-30 2007-01-17 富士通株式会社 磁気記録再生装置および磁気記録再生用ｌｓｉ
DE10111439A1 (de) * 2001-03-09 2002-09-26 Infineon Technologies Ag Signalverzögerungsschaltung
TWI240919B (en) * 2003-07-04 2005-10-01 Mediatek Inc Write signals control circuit in a disk drive
DE10332008B4 (de) * 2003-07-14 2006-08-10 Infineon Technologies Ag Elektrische Schaltung sowie Verfahren zum Testen von elektronischen Bauteilen
US7157952B2 (en) * 2004-08-20 2007-01-02 L-3 Integrated Systems Company Systems and methods for implementing delay line circuitry
US20060176095A1 (en) * 2005-02-09 2006-08-10 International Business Machines Corporation Cycle staging latch with dual phase dynamic outputs for hit logic compare
US7332983B2 (en) * 2005-10-31 2008-02-19 Hewlett-Packard Development Company, L.P. Tunable delay line using selectively connected grounding means
US7378831B1 (en) * 2007-01-18 2008-05-27 International Business Machines Corporation System and method for determining a delay time interval of components
US8306796B2 (en) * 2007-08-15 2012-11-06 The Boeing Company Pyrotechnic shock simulation system and method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4684897A (en) * 1984-01-03 1987-08-04 Raytheon Company Frequency correction apparatus
US4780667A (en) * 1985-06-25 1988-10-25 Hewlett-Packard Company Magnetostatic wave delay line discriminator with automatic quadrature setting and automatic calibration
US5317219A (en) * 1991-09-30 1994-05-31 Data Delay Devices, Inc. Compensated digital delay circuit

Also Published As

Publication number Publication date
US6127869A (en) 2000-10-03

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