JPH11250407A5 - - Google Patents

Info

Publication number
JPH11250407A5
JPH11250407A5 JP1998046609A JP4660998A JPH11250407A5 JP H11250407 A5 JPH11250407 A5 JP H11250407A5 JP 1998046609 A JP1998046609 A JP 1998046609A JP 4660998 A JP4660998 A JP 4660998A JP H11250407 A5 JPH11250407 A5 JP H11250407A5
Authority
JP
Japan
Prior art keywords
data
delay
signal
transient pulse
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP1998046609A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11250407A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP10046609A priority Critical patent/JPH11250407A/ja
Priority claimed from JP10046609A external-priority patent/JPH11250407A/ja
Priority to US09/258,252 priority patent/US6134691A/en
Publication of JPH11250407A publication Critical patent/JPH11250407A/ja
Publication of JPH11250407A5 publication Critical patent/JPH11250407A5/ja
Withdrawn legal-status Critical Current

Links

JP10046609A 1998-02-27 1998-02-27 Ｎｌｔｓ補正回路 Withdrawn JPH11250407A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10046609A JPH11250407A (ja) 1998-02-27 1998-02-27 Ｎｌｔｓ補正回路
US09/258,252 US6134691A (en) 1998-02-27 1999-02-25 NLTS correction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10046609A JPH11250407A (ja) 1998-02-27 1998-02-27 Ｎｌｔｓ補正回路

Publications (2)

Publication Number Publication Date
JPH11250407A JPH11250407A (ja) 1999-09-17
JPH11250407A5 true JPH11250407A5 (enExample) 2005-08-25

Family

ID=12752057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10046609A Withdrawn JPH11250407A (ja) 1998-02-27 1998-02-27 Ｎｌｔｓ補正回路

Country Status (2)

Country Link
US (1) US6134691A (enExample)
JP (1) JPH11250407A (enExample)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3870333B2 (ja) * 2000-11-30 2007-01-17 富士通株式会社 磁気記録再生装置および磁気記録再生用ｌｓｉ
US6788481B2 (en) 2002-03-21 2004-09-07 International Business Machines Corporation Process for measuring nonlinear transition shift (NLTS) at high recording densities with a giant magetoresistive (GMR) head
US7301375B2 (en) * 2003-03-07 2007-11-27 Hynix Semiconductor Inc. Off-chip driver circuit and data output circuit using the same
JPWO2005013107A1 (ja) * 2003-07-31 2006-09-28 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の駆動方法
US7123429B2 (en) * 2004-02-26 2006-10-17 Hitachi Global Storage Technologies Netherlands B.V. Method and apparatus for providing write pre-compensation using a read timing path
US7002764B2 (en) 2004-02-26 2006-02-21 Hitachi Global Storage Technologies Netherlands B.V. Method and apparatus for providing generalized write pre-compensation
US7515372B2 (en) * 2006-04-03 2009-04-07 Seagate Technology Llc Compensating the effects of static head-media spacing variations and nonlinear transition shift in heat assisted magnetic recording
EP2198427A4 (en) * 2007-12-21 2013-11-06 Lsi Corp SYSTEMS AND METHODS FOR ADAPTIVE EQUALIZATION IN RECORDING CHANNELS
US7924523B2 (en) * 2007-12-21 2011-04-12 Lsi Corporation Frequency domain approach for efficient computation of fixed-point equalization targets
EP2136037A3 (de) * 2008-06-20 2011-01-05 Siemens Aktiengesellschaft Verfahren und Vorrichtung zum Betreiben einer Dampfkraftwerksanlage mit Dampfturbine und Prozessdampfverbraucher
US7924518B2 (en) * 2008-08-27 2011-04-12 Lsi Corporation Systems and methods for adaptive write pre-compensation
US9281908B2 (en) * 2008-10-08 2016-03-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for memory efficient signal and noise estimation
US8154815B2 (en) * 2008-12-18 2012-04-10 Lsi Corporation Systems and methods for generating equalization data using shift register architecture
US7948702B2 (en) * 2008-12-18 2011-05-24 Lsi Corporation Systems and methods for controlling data equalization
US7965467B2 (en) * 2008-12-18 2011-06-21 Lsi Corporation Systems and methods for generating equalization data
US7929240B2 (en) * 2008-12-18 2011-04-19 Lsi Corporation Systems and methods for adaptive MRA compensation
US7974030B2 (en) 2008-12-23 2011-07-05 Lsi Corporation Systems and methods for dibit correction
US7948699B2 (en) * 2009-01-02 2011-05-24 Lsi Corporation Systems and methods for equalizer optimization in a storage access retry
US7957251B2 (en) 2009-02-16 2011-06-07 Agere Systems Inc. Systems and methods for reduced latency loop recovery
US7969337B2 (en) * 2009-07-27 2011-06-28 Lsi Corporation Systems and methods for two tier sampling correction in a data processing circuit
US8139305B2 (en) * 2009-09-14 2012-03-20 Lsi Corporation Systems and methods for timing and gain acquisition
US8854752B2 (en) 2011-05-03 2014-10-07 Lsi Corporation Systems and methods for track width determination
US8762440B2 (en) 2011-07-11 2014-06-24 Lsi Corporation Systems and methods for area efficient noise predictive filter calibration
US9112538B2 (en) 2013-03-13 2015-08-18 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for loop feedback
US8848776B1 (en) 2013-03-25 2014-09-30 Lsi Corporation Systems and methods for multi-dimensional signal equalization
US8929010B1 (en) 2013-08-21 2015-01-06 Lsi Corporation Systems and methods for loop pulse estimation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5355261A (en) * 1993-12-20 1994-10-11 Guzik Technical Enterprises, Inc. Method and apparatus for measuring error rate of magnetic recording devices having a partial response maximum likelihood data detection channel
KR100269169B1 (ko) * 1995-08-25 2000-10-16 윤종용 하드 디스크 드라이브에서의 스큐 최적화 방법

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