JPH11233729A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device in which inverse narrow and narrow effects are controlled by the simplified and low cost method to eliminate the narrow effects in both P-channel and N- channel transistors. SOLUTION: This manufacturing method comprises a process to form the P-type and N-type wells on a P-type semiconductor substrate 1, a process to selectively form an oxidation proof film 5 on a semiconductor substrate 1, a first ion injecting process to inject the P-type impurity ion on the self- alignment basis using the oxidation proof film 5 as the mask, a process to selectively form a field oxide film 6 on one main surface of the semiconductor substrate and a second ion injecting process to inject P-type impurity ion from the upper part of the field oxide film 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device for improving a narrow effect in a P-channel (Pch) transistor and an N-channel (Nch) transistor.

[0002]

2. Description of the Related Art FIG. 2 is a cross-sectional view in the channel width (W) direction of a semiconductor device which is isolated by a conventional field oxide film (element isolation region). As shown in FIG. 2, for example, a well-known LOCOS is formed on a P-type silicon semiconductor substrate 20.
A field oxide film 21 is provided by a method, and a P-type channel stopper layer 22 is provided below the field oxide film 21. A gate electrode 24 made of polysilicon or the like is provided via a gate insulating film 23,
An N-type source-drain 25 is provided on the substrate 20.

By the way, as the pattern becomes finer, the width of the active region of the transistor decreases, and the problem of crowding of the channel stopper layer, that is, the threshold voltage (Vth) decreases as the channel width (W) decreases. The narrow effect, which is a phenomenon in which) rises, becomes a problem. Conventionally, as a method of suppressing the narrow effect of a transistor, it has been effective to suppress the seepage of impurities from a channel stopper region below a field oxide film.

For example, Japanese Unexamined Patent Publication (Kokai) No. 3-64946 discloses that the implantation energy of a channel stopper is increased, the implantation peak position of the channel stopper is lowered, and the impurity concentration on the surface of the field oxide film is reduced, so that the transistor channel region is reduced. A method for suppressing the seepage of the channel stopper is disclosed.

Japanese Patent Application Laid-Open No. 2-278747 discloses that after patterning a silicon nitride film, a sidewall spacer is formed to increase the distance to a subsequent channel region, and two types of diffusion stoppers having different diffusion constants are used as channel stoppers. A method is disclosed in which the ion concentration (for example, As and P) is used to keep the Vth of the transistor high, and to set the impurity concentration at the edge of the active region of the transistor to be thin with only the ion species having a large diffusion constant.

Further, in Japanese Patent Application Laid-Open No. 5-28351, ion implantation for a channel stopper is performed using the silicon nitride film after field oxidation as a mask. Thereby, a method can be provided in which the transistor active region and the offset can be provided, and oozing is suppressed.

[0007]

As described above, the method of lowering the injection peak position of the channel stopper, the provision of an offset (Offset) region at the time of injection, the provision of a lateral diffusion amount in advance, and the immersion into the active region are ensured. A method for suppressing protrusion has been proposed.

However, in these methods, as shown in FIG. 2, there is a possibility that a low-concentration region 26 of impurities may be generated by suppressing seepage. In such a case, FIG.
When the concentration of the low-concentration region 26 is lower than the impurity concentration of the channel region of the transistor, an inverse narrow effect is exhibited, in which Vth decreases as the channel width (W) decreases, contrary to the usual narrow effect. The broken line in FIG. 3 indicates the reverse narrow effect, and the solid line indicates the normal narrow effect.

In particular, in a circuit using a transistor (Tr) having a relatively small channel width (W), such as a memory, there is a problem of deterioration of cutoff characteristics such as an increase in standby current due to an inverse narrow effect. At the same time, since the concentration of the well in the transistor in the well is usually higher than that of the substrate side, the channel stopper is not implanted and a normal narrow effect is often exhibited. That is, the Vth balance of the Pch / Nch transistor is very poor due to the reverse narrow effect of the transistor on the substrate side, that is, one is high,
Since the other is low, it is a further concern that the problem may occur in the circuit configuration.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and provides a method of manufacturing a semiconductor device which suppresses reverse narrow and narrow effects by a method as simple and inexpensive as possible, and which has no narrow effect for both Pch and Nch transistors. The aim is to provide a method.

[0011]

According to the present invention, a step of forming a second conductivity type well on a first conductivity type semiconductor substrate and selectively forming an oxidation resistant film on the semiconductor substrate are provided. A first ion implantation step of self-aligningly implanting impurity ions of a first conductivity type using the oxidation resistant film as a mask; and selectively depositing a field oxide film on one main surface of the semiconductor substrate. And a second ion implantation step of implanting impurity ions of a first conductivity type from above the field oxide film.

In the first ion implantation step, the ion implantation is performed.
Dose of ions is 2E13cm ^-2Can be
preferable.

Further, according to the present invention, the first conductivity type is P
The mold and the second conductivity type are N-type, and the second ion implantation step is performed in a state where the well of the second conductivity type is covered.

According to the above structure, the ion implantation for suppressing the narrow effect is entirely implanted in a self-aligned manner before the field oxidation, and the ion implantation for the channel stop is performed after the field oxidation. Can reduce the narrow effect.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the present invention step by step. The figure shows a cross section of the transistor in the channel width (W) direction.

First, as shown in FIG. 1A, an N-well region 2 and a P-well region 3 are formed on a P-type silicon semiconductor substrate 1.
Is formed, a silicon oxide film 4 is formed. Here, as the P-type semiconductor substrate 1, for example, a substrate having a resistivity of 20 Ωcm and a P-type impurity concentration of 6E14 cm ⁻³ is used. Then, the impurity concentration of the N well region and the P well region is formed, for example, at a concentration of 1E17 cm ⁻³ .

Further, the P-well region 3 and the N-well region 2 can be formed of a retrograde well. In this case, since the concentration near the surface is lower than that of the conventional well, the reverse narrow effect is easily obtained. The effect of the present invention is great.

Subsequently, a silicon nitride film is formed on the silicon oxide film 4 as the oxidation resistant film 5,
Is patterned. Thereafter, P-type impurity ions, here, boron (B) are ion-implanted over the entire surface. The implantation conditions are, for example, an acceleration energy of 15 keV and a dose of 5E.
The implantation is 12 cm ^-2 , which is considerably thinner than the conventional method of batch implantation before field oxidation. This is because the purpose of the injection at this point is not channel stop but is limited only to the suppression of the narrow effect. Therefore, the dose is preferably about 2E13 cm ⁻² or less.

Thereafter, as shown in FIG. 1B, a field oxide film 6 is formed on one main surface of the semiconductor substrate 1 by a well-known method, and then the N well region 2 is covered with a resist 7 and boron is again formed. (B) is ion-implanted. This boron implantation is performed, for example, at an acceleration energy of 200 keV and a dose of 5E12 cm ⁻² . As a result, the boron implanted regions 8 formed before the field oxidation and the boron implanted regions 9 formed after the field oxidation are distributed as shown in the figure.

Subsequently, when a polysilicon film is deposited and patterned to form a gate electrode 10, three types of impurity concentration regions 11 and 1 are formed near the surface of the element isolation region.
A cross-sectional shape as shown in FIG. That is, in the P-well region 3, a deep P-type impurity region 11 for channel stopper and a relatively thin P-type impurity region 12 for suppressing the reverse narrow effect are formed. In the N-well region 2, a relatively thin N-type region 13 for suppressing a narrow effect is formed.

[0021]

As described above, in the method of manufacturing a semiconductor device, ion implantation for suppressing the narrow effect is entirely performed in a self-aligned manner before field oxidation, and ion implantation for channel stop is performed after field oxidation. Therefore, the narrow effect suppression or control of the Nch transistor and the Pch transistor can be performed easily and at low cost.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to the present invention step by step.

FIG. 2 is a cross-sectional view in a channel width (W) direction of a semiconductor device in which a device is isolated by a conventional field oxide film (element isolation region).

3 is a diagram showing a relationship between a channel width (W) and a threshold voltage (Vth) of the semiconductor device shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 N well region 3 P well region 6 Field oxide film

Claims (3)

[Claims] A step of forming a well of a second conductivity type on a semiconductor substrate of a first conductivity type; a step of selectively forming an oxidation-resistant film on the semiconductor substrate; A first ion implantation step of implanting impurity ions of a first conductivity type in a self-aligned manner using the film as a mask, and a step of selectively forming a field oxide film on one main surface of the semiconductor substrate;
A second ion implantation step of implanting impurity ions of a first conductivity type from above the field oxide film. 2. The method according to claim 1, wherein the dose of ions implanted in the first ion implantation step is 2E13 cm ⁻² or less. 3. The method according to claim 1, wherein the first conductivity type is P-type, the second conductivity type is N-type, and the second ion implantation step is performed in a state of covering a well of the second conductivity type. The method for manufacturing a semiconductor device according to claim 1, wherein: