KR940001399B1 - High ic and manufacturing method thereof - Google Patents

Abstract

The structure comprises a drain and a source of the second conduction which are separated apart by a semiconductor substrate of the first conduction and a channel area within the substrate, the first impurity doping area of the first conduction separated apart from the sides of the drain and the source within the channel area, and the second impurity doping area of the first conduction separated apart from the sides of the drain and the source and having the maximum concentration value of impurity in the bottom of the first impurity doping area.

Description

Structure and manufacturing method of highly integrated semiconductor transistor

1 is a cross-sectional view according to a conventional embodiment.

2 is a partial manufacturing process according to another conventional embodiment.

3 is a cross-sectional view according to the present invention.

4 is a manufacturing process diagram according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a structure and a manufacturing method of a highly integrated semiconductor transistor having an impurity doping region for adjusting the threshold voltage and an ion implantation region for suppressing punchthrough.

Metal-Oxide-Semiconductor Transistor, a semiconductor device whose current between the source and the drain is controlled by the voltage applied to the gate, is ion implanted to control the threshold voltage and to prevent punch-through. Is carried out.

1 is a cross-sectional view according to a conventional embodiment.

As shown in FIG. 1, the ion implantation region 12 for the threshold voltage regulation is performed by ion implanting impurities of the first conductive type by performing a first ion implantation process from the entire surface of the first conductive type semiconductor substrate 1. ).

Next, a gate 4 having the upper gate oxide film 2 of the upper surface of the substrate 1 as an intermediate layer is formed. Thereafter, a second ion implantation process using the gate 4 as a mask is performed to form a punchthrough suppression ion implantation region 10 of the first conductivity type. Next, an ELDD (Enhancement Lightly Doped Drain) structure is formed by a third ion implantation process using the gate 4 as a mask and a fourth ion implantation process using the oxide spacer 6 of the gate 4 and its sidewalls as a mask. A source and a drain 8 of the second conductive type having a is formed.

As shown in the figure, since the ion implantation for adjusting the threshold voltage is performed on the entire surface of the substrate, the doping concentrations of the source and drain having the conductivity type opposite to that of the ion implanted impurities are reduced.

In particular, when the dose is increased during the ion implantation process for adjusting the threshold voltage, the doping concentration of the drain becomes more prominent, and as a result, the drain current is reduced. Therefore, there is a problem that the driving capability of the transistor is lowered.

In addition, since the punch-through suppression ion implantation region 10 completely covers the source and drain 8, there is a problem in that the junction breakdown voltage between the source or drain and the substrate is lowered.

In addition, in the case of a lightly doped drain (LDD) transistor, the drain current is reduced by reducing the doping concentration of the low concentration drain in the punch-through suppression ion implantation region.

2 (a) to 2 (b) show a partial manufacturing process diagram according to another exemplary embodiment of the present invention, which shows another embodiment of the ion implantation process for adjusting the threshold voltage.

In FIG. 2A, the gate insulating film 22, the low temperature nitride 24 and the photoresist 2 are formed on the first conductive semiconductor substrate 16 having the field oxide film 20 formed thereon.

6) are sequentially stacked, and a pattern of the photoresist 26 is formed by a general photolithography process to etch the low temperature nitride film 24 in a predetermined region until the surface of the gate insulating film 22 is exposed. Thereafter, after removing the photoresist 26, an impurity doped region 28 for controlling a threshold voltage is formed in the lower portion of the opening by implanting impurities of the first conductivity type through the opening by the process.

In FIG. 2 (b), the opening is filled with polycrystalline silicon and then planarized to the height of the nitride film 24. The nitride film 24 is then removed to form a gate 30. Thereafter, the source and drains 31 and 32 are formed by ion implanting impurities of the second conductivity type using the gate 30 as a mask.

As shown in the drawing, when the ion implantation region for controlling the threshold voltage is formed to be limited to the channel region, the doping concentration of the adjacent drain is reduced due to the diffusion of impurities in the ion implantation region. As a result, there is a problem that the drain current is reduced.

Accordingly, an object of the present invention is to prevent the reduction of the drain doping concentration by overlapping the ion implantation region and drain for threshold voltage control, or the punch-through suppression ion implantation region and drain in the structure and manufacturing method of a highly integrated semiconductor transistor. It is to provide a structure and a manufacturing method of a highly integrated semiconductor transistor.

Another object of the present invention is to provide a structure and a manufacturing method of a highly integrated semiconductor transistor for preventing the reduction of the junction breakdown voltage by the punch-through suppression ion implantation region in the structure and manufacturing method of the highly integrated semiconductor transistor.

In order to achieve the object of the present invention as described above, the first impurity doping region and the lower portion of the first impurity doping region of the conductive type, such as a substrate formed in the channel region of the MOS transistor spaced a predetermined distance from the source and drain regions. And a second impurity doped region of a conductive type such as a substrate.

In order to achieve another object of the present invention, after forming a first insulating film made of an oxide film on the upper surface of the semiconductor substrate of the first conductive type, the first insulating film of a predetermined region is etched until the surface of the substrate is exposed to form an opening. Next, a second insulating film made of a nitride film is formed on the entire surface of the substrate, and a spacer made of an oxide film is formed on the sidewall of the opening, and then the first ion implantation process for adjusting the threshold voltage and the second ion for suppressing punchthrough. And a step of carrying out the injection process with the first and second energies and the first and second doses, respectively.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view of the first conductive semiconductor substrate 34, the source and drain 54, 60, 56 and 62 of the LDD structure spaced apart from each other by a channel region. A first impurity doping region 46 for adjusting the threshold voltage formed in the region and spaced apart from sidewalls of the source and drain, and a second impurity doping region for punchthrough suppression under the first impurity doping region 46. 48, a gate 52 having the gate oxide film 45 on the upper surface of the channel region as an intermediate layer, and an insulating film spacer 58 on the sidewall of the gate 52. As shown in FIG.

4 (a)-(g) are manufacturing process diagrams according to the present invention, and it should be noted that the same numbers are used for the same names as in FIG.

In FIG. 4 (a), the first oxide film 36 is formed on the upper surface of the first conductive semiconductor substrate 34 with a thickness of about 2000 to 2,500 Å. Then, the first oxide layer 36 is etched until the surface of the substrate is exposed by defining a predetermined region by a photolithography process to form an opening, and then a thin nitride film 40 of 100 Å-150 과 and 1000 Å-1500 Å The second oxide film 42 is formed sequentially.

In FIG. 4B, an oxide spacer 44 is formed on sidewalls of the openings by reactive ion etching. The width of the spacer must be equal to or greater than the sum of the side diffusion width of the source and drain and the side diffusion width of the impurity doped region for adjusting the threshold voltage. P-type impurities are then implanted with an ion of 1E12ions / cm 2 and energy of 30 KeV from the upper portion of the substrate 34 to form a first impurity doping region 46 for controlling the threshold voltage on the lower surface of the opening 34. In this case, the first oxide layer 36 and the oxide spacer 44 serve as a mask during the ion implantation process.

Subsequent to the process of FIG. 4 (b), P-type impurities are implanted with an ion of 1E13ions / cm 2 and energy of 100KeV-150KeV from the upper portion of the substrate 34 in FIG. 4 (c). Thus, a second impurity doping region 48 for suppressing punchthrough having the highest impurity concentration at a lower portion spaced from the first impurity doping region 46 by a predetermined distance is formed.

Although the first and second impurity doped regions 46 and 48 are spaced apart from each other by a predetermined distance in the drawing, predetermined regions may overlap with each other according to ion implantation energy. The first and second impurity doped regions 46 and 48 may be formed in reverse order.

After removing the nitride film 40 and the oxide spacer 44 from FIG. 4 (d), a third oxide film 45 having a thickness of 80 μm to 100 μm is formed on the surface of the substrate 34 as a gate oxide film.

Then, the polycrystalline silicon 50 is deposited on the upper surface of the substrate 34 to the thickness of the first oxide film 36 or more. Thereafter, the polycrystalline silicon is doped with POCl ₃ so that the resistance Rs is about 50 mA / square.

In FIG. 4E, the polycrystalline silicon is etched back or ground until the third oxide layer 45 is exposed. Thus, only polycrystalline silicon remains in the opening.

In FIG. 4F, the third oxide layer 45 and the first oxide layer 36 remaining on the upper surface of the substrate 34 are removed.

As a result, the gate oxide film 45 made of the third oxide film and the gate 52 made of polycrystalline silicon are formed on the upper surface of the substrate 34.

Then, the ion implantation process is performed by a self-alignment method, in which the ion implanted impurities are n-type and their dose and energy are about 4E13ions / cm 2 and 40KeV, respectively. As a result, the first source and drain 54 and 56 having low concentration are formed in the substrate region except for the lower portion of the gate.

Subsequently, even when diffusion of the first source and drain 54 and 56 and the impurity doped region 46 for adjusting the threshold voltage occurs in the heat treatment process, the side surfaces of the doped regions are spaced a predetermined distance apart. This is because the oxide spacer 44 is formed to a sufficient width in the process of FIG. 4 (b) in consideration of the diffusion of the impurity doped region by heat treatment.

In FIG. 4 (g), a second oxide film spacer 58 having a width of 1000 게이트 to 1300 Å is formed on the sidewall of the gate. Then, n-type impurities are implanted from the upper portion of the substrate 34 at a dose of 5E15ions / cm 2 and an energy of 40KeV. As a result, a high concentration of the second source and drain 60 and 62 is formed in the substrate region except for the lower portion of the gate 52 and the second spacer 58 by overlapping the first source and drain 54 and 56 with a predetermined region. do.

In the above-described embodiment of the present invention, a method and a structure of forming an impurity doping region for adjusting the threshold voltage of a MOS transistor having an LDD structure and an impurity doping region for punchthrough suppression have been described. However, it will be apparent to those skilled in the art that embodiments of semiconductor transistors having other structures are possible without departing from the technical spirit of the present invention.

As described above, in the structure of a highly integrated semiconductor transistor and a method of manufacturing the same, an opening is formed on the upper surface of the substrate to define a region where a gate is to be formed, and then a spacer having a predetermined width is formed on the sidewall of the opening. The first and second ion implantation processes were carried out by a self-aligning method with the energy and the energy.

The impurity doping region for adjusting the threshold voltage and the impurity doping region for punchthrough suppression are thus formed at a predetermined distance from the source and drain regions so that the doping concentration of the drain is not affected by the two impurity doping regions. It was. As a result, by maintaining the doping concentration of the drain as the concentration by the first process, there is an effect that can obtain the desired drain current and thereby the desired driving characteristics.

In addition, by forming a channel through the impurity doping region for punch-through suppression at the bottom, the punch-through can be suppressed and the reduction of the junction breakdown voltage between the source or drain and the substrate can be prevented. In addition, by forming the two impurity doped regions by a self-aligning method, it is possible to reduce the size of the transistor to facilitate the miniaturization and high integration of the device.

Claims (10)

The first conductive semiconductor substrate 34 and the second conductive source sources and drains 54, 60, 56 and 62 spaced apart from each other by the channel region in the substrate 34 and the upper surface of the channel region. A highly integrated semiconductor transistor having a gate 52 having an interlayer formed therein as a gate insulating film 45, and formed in the channel region spaced apart from the side surfaces of the source and drain 54, 60, 56, 62 by a predetermined distance. The first impurity doped region 46 of the first conductivity type and the highest impurity concentration at the bottom of the first impurity doped region 46 have the highest concentrations of the source and drains 54, 60, and 56, 62. And a second impurity doping region (48) of the first conductivity type formed at a predetermined distance from the side surface. 2. The highly integrated semiconductor transistor of claim 1, wherein the first impurity doped region is for adjusting the threshold voltage and the second impurity doped region is for suppressing punchthrough. 3. The highly integrated semiconductor transistor of claim 2, wherein the second impurity doped region (48) is higher in concentration than the first impurity doped region (46). In the manufacturing method of the highly integrated semiconductor transistor, after forming the first insulating film 36 on the upper surface of the first conductive semiconductor substrate 34, the channel region is limited to the first insulating film 36 corresponding to the upper surface of the channel region. Etching to form an opening by etching until the surface of the substrate 34 is exposed; a second process of sequentially forming the second insulating film 40 and the third insulating film 42 on the entire surface of the substrate 34; And etching the third insulating layer 42 by reactive ion etching to form a third insulating layer spacer 44 on the sidewall of the opening, and a first dose and energy on the entire surface of the substrate 34. And continuously performing the second ion implantation process to form the first and second impurity doping regions 46 and 48 on the lower surface of the substrate exposed from the first insulating layer 36 and the third insulating layer spacer 44 and the lower portion thereof. Highly integrated semiconductor characterized in that it comprises a fourth step of forming sequentially Method for manufacturing a transistor. 5. A method according to claim 4, wherein the first and third insulating films (36,42) are oxide films. The method of manufacturing a highly integrated semiconductor transistor according to claim 4, wherein said second insulating film (40) is a nitride film. 5. The method of claim 4, wherein the second impurity doped region 48 is formed by a higher energy, higher concentration impurity ion implantation process than the first impurity doped region 46. . 8. The method of claim 7, wherein the distance between the first impurity doped region (46) and the source and drain regions is controlled by the width of the third insulating film spacer (44). The semiconductor device of claim 8, wherein the width of the third insulating layer spacer 44 is greater than or equal to the sum of the side diffusion width of the first impurity doped region 46 and the side diffusion width of the source or drain. Method for manufacturing a transistor. 5. The gate insulating film 45 of claim 4, further comprising a fifth process of sequentially removing the third insulating film spacer 44 and the second insulating film 40 after the fourth process, and forming a gate insulating film 45 on the entire surface of the substrate 34. After that, the sixth step of forming the first insulating layer 50 into two or more of the first insulating layers 36 and the surface of the first conductive layer 50 have a gate insulating layer on the upper surface of the first insulating layers 36. A seventh step of performing a planarization process until the surface of (45) coincides with the surface of (45), and removing the exposed gate insulating film 45 and the first insulating film 36 on the lower surface thereof, and then performing one or more ion implantation processes And an eighth step of forming a source and a drain region of the second conductive type.

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