JPH11145179A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH11145179A JPH11145179A JP9308568A JP30856897A JPH11145179A JP H11145179 A JPH11145179 A JP H11145179A JP 9308568 A JP9308568 A JP 9308568A JP 30856897 A JP30856897 A JP 30856897A JP H11145179 A JPH11145179 A JP H11145179A
- Authority
- JP
- Japan
- Prior art keywords
- wire
- point
- semiconductor chip
- bending
- bending point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、プラスチックモー
ルド型パッケージされた半導体装置において、半導体チ
ップとリード部の結線の改良に関する。さらに詳しく
は、前記の結線におけるワイヤ変形や短絡を防止する半
導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in connection between a semiconductor chip and a lead portion in a semiconductor device packaged in a plastic mold. More specifically, the present invention relates to a semiconductor device for preventing wire deformation and short circuit in the connection.
【０００２】[0002]
【従来の技術】一般的に、プラスチックモールド型の半
導体装置において、半導体チップとリード部をワイヤで
結線する際、ループ形状を任意に形成して結線してい
る。図１は従来の半導体装置の一構成例を示す要部拡大
断面図である。半導体チップ１とチップ支持部２を接着
剤５を用いて一体化し、その半導体チップ上の図示して
いないパット（電極）部とリード３をワイヤ４で結線す
る。そして、前記半導体チップ１とチップ支持部２、ワ
イヤ４、リード３をモールド樹脂６により封止する。通
常、結線は自動ワイヤボンド装置を用いて行うが、設定
された設備条件によってワイヤ４のループ形状が任意に
形成される。そのため、ワイヤの結線長が長くなった
り、太さが細くなったりした時には製造を終了するまで
に、ワイヤが変形しやすくなる。2. Description of the Related Art Generally, in a semiconductor device of a plastic mold type, when a semiconductor chip and a lead portion are connected by wires, a loop shape is arbitrarily formed and connected. FIG. 1 is an enlarged cross-sectional view of a main part showing one configuration example of a conventional semiconductor device. The semiconductor chip 1 and the chip supporting portion 2 are integrated using an adhesive 5, and a pad (electrode) portion (not shown) on the semiconductor chip is connected to a lead 3 with a wire 4. Then, the semiconductor chip 1, the chip support 2, the wires 4, and the leads 3 are sealed with a mold resin 6. Usually, the connection is performed using an automatic wire bonding apparatus, but the loop shape of the wire 4 is arbitrarily formed according to the set equipment conditions. Therefore, when the connection length of the wire becomes longer or the thickness becomes thinner, the wire is more likely to be deformed before the manufacture is completed.
【０００３】[0003]
【発明が解決しようとする課題】上記従来の構成では、
結線されたワイヤの機械的強度が十分に確保できないた
め、製品搬送中には振動や衝撃などで変形を起こしやす
く、樹脂で封止する工程では、モールド樹脂の流動によ
って結線されたワイヤが流れて変形しやすく、またその
流動によって隣接するワイヤとの短絡が起きやすくなる
という問題があった。In the above-mentioned conventional configuration,
Since the mechanical strength of the connected wire cannot be secured sufficiently, it is easy to be deformed by vibration or impact during product transport, and in the process of sealing with resin, the connected wire flows due to the flow of mold resin. There is a problem that the wire is easily deformed, and the flow easily causes a short circuit with an adjacent wire.
【０００４】本発明は、上記従来の問題を解決するもの
で、結線されたワイヤの強度を保ち変形を起こしにくく
するワイヤのループ形状を持った半導体装置を提供する
ことを目的とする。An object of the present invention is to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device having a wire loop shape that maintains the strength of a connected wire and makes it difficult to cause deformation.
【０００５】[0005]
【課題を解決するための手段】この目的を達成するため
に、本発明の半導体装置は、チップ支持部と、前記チッ
プ支持部上に接着剤を介して接着された半導体チップ
と、前記半導体チップとリード部を電気的に接続したワ
イヤを封止して形成されたプラスチックモールド型半導
体装置において、前記ワイヤが前記半導体チップ上の屈
曲部の第１の屈曲点と、それよりリード部側にある第２
の屈曲点を持ち、前記第１の屈曲点と前記第２の屈曲点
を通る形状が、半導体チップ上平面に対して高低差が５
０μｍ以内であり、ほぼ直線的な平坦部を持ち、この平
坦部の長さが半導体チップ上方向から見たワイヤの結線
長の１０％以上６０％以下の長さの範囲であることを特
徴とする。In order to achieve this object, a semiconductor device according to the present invention comprises a chip support, a semiconductor chip adhered on the chip support via an adhesive, and a semiconductor chip. In a plastic molded semiconductor device formed by sealing a wire electrically connecting the lead and the lead portion, the wire is located at a first bending point of a bending portion on the semiconductor chip and on the lead portion side therefrom. Second
And the shape passing through the first bending point and the second bending point has a height difference of 5 with respect to the upper surface of the semiconductor chip.
0 μm or less, and has a substantially linear flat portion, and the length of the flat portion is in the range of 10% to 60% of the connection length of the wire viewed from above the semiconductor chip. I do.
【０００６】前記半導体装置においては、ワイヤのルー
プ形状が、前記平坦部が前記半導体チップ上平面に対し
て、高さが８０μm〜３００μm範囲内であることが好ま
しい。In the semiconductor device, it is preferable that the loop shape of the wire is such that the flat portion has a height within a range of 80 μm to 300 μm with respect to the upper surface of the semiconductor chip.
【０００７】この構成によって、結線したワイヤが振動
や樹脂流動に対する強度を強めることができるため、結
線されたワイヤの変形を少なくすることができる。[0007] According to this configuration, the strength of the connected wire against vibration and resin flow can be increased, so that deformation of the connected wire can be reduced.
【０００８】[0008]
【発明の実施の形態】以下、本発明の一実施の形態につ
いて、図面を参照しながら説明する。図２及び図３は、
本発明の一実施の形態におけるプラスチックモールド型
半導体装置の要部拡大断面図を示すものである。図２〜
図３において、１は半導体チップ、２は半導体チップを
支持するためのチップ支持部、３は半導体チップとの電
気信号を交信するためのリード部、４は半導体チップ１
とリード部３を結線するワイヤ、５は半導体チップ１と
チップ支持部２を一体化する接着剤で、６はモールド樹
脂である。An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 and FIG.
FIG. 1 is an enlarged sectional view of a main part of a plastic mold type semiconductor device according to an embodiment of the present invention. Figure 2
In FIG. 3, 1 is a semiconductor chip, 2 is a chip supporting portion for supporting the semiconductor chip, 3 is a lead portion for exchanging electric signals with the semiconductor chip, and 4 is a semiconductor chip 1.
Reference numeral 5 denotes an adhesive for connecting the semiconductor chip 1 and the chip supporting portion 2, and reference numeral 6 denotes a molding resin.
【０００９】本発明の実施の形態においては、半導体チ
ップ１とリード部３を結線するワイヤ４のループ形状
が、図２に示されるように半導体チップ１上のワイヤ４
の屈曲部の最も高い点をＡ点（第１の屈曲点）と、それ
よりリード部３側の大きな屈曲点（変曲点）であるＢ点
（第２の屈曲点）を含み、Ａ点とＢ点のワイヤ４が半導
体チップ１の上平面（パターン面）を含む平面に対して
高低差５０μmの範囲でほぼ直線的に近似している平坦
部を持つ形状にしたことである。これは図３に示すよう
に半導体チップ１の上平面を含む平面に対して鉛直方向
の距離において、もしＡ点の高さがＡ´ 点になった場
合Ａ´ 点とＢ点の高低差の絶対値が５０μm以内である
ことであり、Ｃで示されるように、Ａ点、Ｂ点を支点と
してワイヤが垂れ下がったり盛り上がったりする場合
に、Ａ点とＢ点の間の最も低い点がＡ点、Ｂ点それぞれ
の高さと高低差も５０μm以内となる。In the embodiment of the present invention, the loop shape of the wire 4 connecting the semiconductor chip 1 and the lead portion 3 is changed as shown in FIG.
The point A includes a point A (first bending point) which is the highest point of the bent portion, and a point B (second bending point) which is a larger bending point (inflection point) on the lead portion 3 side. And that the wire 4 at point B has a flat portion which is approximately linearly approximated to a plane including the upper plane (pattern plane) of the semiconductor chip 1 within a height difference of 50 μm. As shown in FIG. 3, if the height of the point A becomes the point A 'at a distance in the vertical direction with respect to the plane including the upper plane of the semiconductor chip 1 as shown in FIG. The absolute value is within 50 μm, and as shown by C, when the wire hangs or bulges around the points A and B, the lowest point between the points A and B is the point A. , And B, the height and the height difference are also within 50 μm.
【００１０】また図２において、前記ワイヤの第１の屈
曲点（Ａ点）と前記第２の屈曲点（Ｂ点）のほぼ直線的
な平坦部の長さ（Ｌ１）は、半導体チップ上方向から見
たワイヤの結線長（Ｌ）の１０％から６０％の長さの範
囲である。ワイヤの結線長（Ｌ）としてはいかなる長さ
であっても良いが、とくに、長さ：５ｍｍ〜７ｍｍのロ
ングワイヤ及び直径：１０μm〜２５μmのワイヤ径のも
のに有効である。In FIG. 2, the length (L1) of a substantially linear flat portion between the first bending point (point A) and the second bending point (point B) of the wire is determined in the upward direction of the semiconductor chip. From 10% to 60% of the connection length (L) of the wire as viewed from above. The connection length (L) of the wire may be any length, but is particularly effective for a long wire having a length of 5 mm to 7 mm and a wire diameter of 10 μm to 25 μm.
【００１１】また、図２、図３の前記Ａ点、Ｂ点は半導
体チップ１の上平面を含む平面に対して８０μmから３
００μmの高さＨ（図２）に位置するのが好ましい。こ
のようなループ形状を持ったワイヤ４を結線した後、モ
ールド樹脂によって封止を行い、本実施の形態の半導体
装置を製造する。The points A and B in FIGS. 2 and 3 are between 3 μm and 80 μm with respect to the plane including the upper plane of the semiconductor chip 1.
It is preferably located at a height H of 00 μm (FIG. 2). After connecting the wire 4 having such a loop shape, sealing is performed with a mold resin to manufacture the semiconductor device of the present embodiment.
【００１２】以上のように、本実施の形態によれば、ワ
イヤ４において図２のように屈曲点Ａ点、Ｂ点をそれぞ
れ作り、上記平坦部を図２に示された適切な高さである
８０μmから３００μmの高さＨに位置させることによ
り、ワイヤ４全体の機械的強度を向上させ、モールド樹
脂の流動抵抗を下げることができる。As described above, according to the present embodiment, the bending points A and B are respectively formed in the wire 4 as shown in FIG. 2, and the flat portion is formed at an appropriate height shown in FIG. By positioning the wire H at a certain height H of 80 μm to 300 μm, the mechanical strength of the entire wire 4 can be improved and the flow resistance of the mold resin can be reduced.
【００１３】[0013]
【発明の効果】以上のように、本発明は、ワイヤが半導
体チップ上の屈曲部の第１の屈曲点と、それよりリード
部側にある第２の屈曲点を持ち、前記第１の屈曲点と前
記第２の屈曲点を通る形状が、半導体チップ上平面に対
して高低差が５０μｍ以内であり、ほぼ直線的な平坦部
を持ち、この平坦部の長さが半導体チップ上方向から見
たワイヤの結線長の１０％以上６０％以下の長さの範囲
であることにより、ワイヤ全体の機械的強度を向上さ
せ、ワイヤ結線から封止するまでの振動や衝撃によるワ
イヤ変形や隣接するワイヤの短絡を防止できる。また、
ワイヤのループ形状において、前記平坦部が前記半導体
チップ上平面に対して、高さが８０μm〜３００μm範囲
内で設けることにより、さらにワイヤ全体の機械的強度
を向上させ、ワイヤ結線から封止するまでの振動や衝撃
によるワイヤ変形や隣接するワイヤの短絡を防止でき
る。As described above, according to the present invention, the wire has the first bending point of the bending portion on the semiconductor chip and the second bending point on the lead side with respect to the first bending point. The shape passing through the point and the second bending point has a height difference within 50 μm with respect to the plane above the semiconductor chip, has a substantially linear flat portion, and the length of this flat portion is viewed from above the semiconductor chip. In the range of 10% or more and 60% or less of the wire connection length of the wire, the mechanical strength of the entire wire is improved, and the wire is deformed due to vibration or impact from wire connection to sealing, and the adjacent wire is connected. Short circuit can be prevented. Also,
In the loop shape of the wire, the flat portion is provided with a height within the range of 80 μm to 300 μm with respect to the upper surface of the semiconductor chip, thereby further improving the mechanical strength of the entire wire, from the wire connection to sealing. Wire deformation and short circuit between adjacent wires due to vibration and impact of the wire.
【００１４】また、このループ形状によりモールド樹脂
での封止を行うときに、封止金型に注入されるモールド
樹脂の流動抵抗を下げることができ、かつ機械的強度も
向上することから、ワイヤ変形や隣接するワイヤとの短
絡を防止できる。In addition, when the sealing is performed with the molding resin by the loop shape, the flow resistance of the molding resin injected into the sealing mold can be reduced and the mechanical strength can be improved. Deformation and short-circuiting with adjacent wires can be prevented.
【００１５】本発明によれば、細いワイヤやワイヤ長が
長い結線を安定して結線することができ、とくに、長
さ：５ｍｍ〜７ｍｍのロングワイヤ及び直径：１０μm
〜２５μmのワイヤ径のものに有効であり、半導体装置
の高密度配線を可能とし、製造工程における歩留り向上
及び信頼性向上をさせることができる。According to the present invention, a thin wire or a long wire can be stably connected. Particularly, a long wire having a length of 5 mm to 7 mm and a diameter of 10 μm are provided.
It is effective for wires having a wire diameter of ２５25 μm, enables high-density wiring of semiconductor devices, and improves the yield and reliability in the manufacturing process.
【図１】 従来の半導体装置の内部構成図である。FIG. 1 is an internal configuration diagram of a conventional semiconductor device.
【図２】 本発明における一実施の形態の要部拡大断面
である。FIG. 2 is an enlarged sectional view of a main part of one embodiment of the present invention.
【図３】 本発明における一実施の形態の説明図であ
る。FIG. 3 is an explanatory diagram of one embodiment of the present invention.
１ 半導体チップ ２ チップ支持 ３ リード部 ４ ワイヤ ５ 接着剤 ６ モールド樹脂 Ａ，Ａ´ 第１の屈曲点 Ｂ 第２の屈曲点 Ｃ ワイヤの垂れ下がり曲線 Ｈ 半導体チップ上面から第１の屈曲点までの高さ Ｌ ワイヤの結線長 Ｌ１ ワイヤのほぼ直線的な平坦部の長さ DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Chip support 3 Lead part 4 Wire 5 Adhesive 6 Mold resin A, A '1st bending point B 2nd bending point C Wire sagging curve H High from semiconductor chip upper surface to 1st bending point Length L Wire connection length L1 Length of almost linear flat part of wire
Claims (2)
接着剤を介して接着された半導体チップと、前記半導体
チップとリード部を電気的に接続したワイヤを封止して
形成されたプラスチックモールド型半導体装置であっ
て、前記ワイヤが前記半導体チップ上の屈曲部の第１の
屈曲点と、それよりリード部側にある第２の屈曲点を持
ち、前記第１の屈曲点と前記第２の屈曲点を通る形状
が、半導体チップ上平面に対して高低差が５０μｍ以内
であり、ほぼ直線的な平坦部を持ち、この平坦部の長さ
が半導体チップ上方向から見たワイヤの結線長の１０％
以上６０％以下の長さの範囲であることを特徴とする半
導体装置。1. A plastic formed by sealing a chip support portion, a semiconductor chip adhered on the chip support portion via an adhesive, and a wire electrically connecting the semiconductor chip and a lead portion. A molded semiconductor device, wherein the wire has a first bending point of a bending portion on the semiconductor chip and a second bending point on a lead portion side thereof, and the wire has a first bending point and the second bending point. The shape passing through the bending point 2 has a height difference within 50 μm with respect to the plane on the semiconductor chip, has a substantially linear flat portion, and the length of the flat portion is a wire connection as viewed from above the semiconductor chip. 10% of length
A semiconductor device having a length in the range of not less than 60% and not more than 60%.
平坦部が前記半導体チップ上平面に対して、高さが８０
μm〜３００μm範囲内である請求項１に記載の半導体装
置。2. In the loop shape of the wire, the flat portion has a height of 80 with respect to the upper surface of the semiconductor chip.
The semiconductor device according to claim 1, wherein the thickness is in a range from μm to 300 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9308568A JPH11145179A (en) | 1997-11-11 | 1997-11-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9308568A JPH11145179A (en) | 1997-11-11 | 1997-11-11 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11145179A true JPH11145179A (en) | 1999-05-28 |
Family
ID=17982598
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9308568A Pending JPH11145179A (en) | 1997-11-11 | 1997-11-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11145179A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6787927B2 (en) | 2001-08-27 | 2004-09-07 | Renesas Technology Corp. | Semiconductor device and wire bonding apparatus |
| US6858697B2 (en) | 2001-12-21 | 2005-02-22 | Air Products And Chemicals, Inc. | Stabilizers to inhibit the polymerization of substituted cyclotetrasiloxane |
| WO2022080134A1 (en) * | 2020-10-16 | 2022-04-21 | ローム株式会社 | Semiconductor device |
-
1997
- 1997-11-11 JP JP9308568A patent/JPH11145179A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6787927B2 (en) | 2001-08-27 | 2004-09-07 | Renesas Technology Corp. | Semiconductor device and wire bonding apparatus |
| US6858697B2 (en) | 2001-12-21 | 2005-02-22 | Air Products And Chemicals, Inc. | Stabilizers to inhibit the polymerization of substituted cyclotetrasiloxane |
| WO2022080134A1 (en) * | 2020-10-16 | 2022-04-21 | ローム株式会社 | Semiconductor device |
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