JPH1058440A - Manufacture of semiconductor wafer - Google Patents

Manufacture of semiconductor wafer

Info

Publication number
JPH1058440A
JPH1058440A JP23717796A JP23717796A JPH1058440A JP H1058440 A JPH1058440 A JP H1058440A JP 23717796 A JP23717796 A JP 23717796A JP 23717796 A JP23717796 A JP 23717796A JP H1058440 A JPH1058440 A JP H1058440A
Authority
JP
Japan
Prior art keywords
wafers
wafer
thickness
wire
wire saw
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23717796A
Other languages
Japanese (ja)
Other versions
JP3839102B2 (en
Inventor
Shuichi Kanazawa
修一 金澤
Kenji Hamada
兼治 濱田
Kazuhiko Suzuki
一彦 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumco Techxiv Corp
Original Assignee
Sumco Techxiv Corp
Komatsu Electronic Metals Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumco Techxiv Corp, Komatsu Electronic Metals Co Ltd filed Critical Sumco Techxiv Corp
Priority to JP23717796A priority Critical patent/JP3839102B2/en
Publication of JPH1058440A publication Critical patent/JPH1058440A/en
Application granted granted Critical
Publication of JP3839102B2 publication Critical patent/JP3839102B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Processing Of Stones Or Stones Resemblance Materials (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress variation of the thicknesses of wafers after the division caused by variation of the thicknesses of the wafers under the specified limit when the semiconductor wafers forming the impurity diffused layers formed on both surfaces are divided into two parts in parallel with the surface with a multiple-wire saw. SOLUTION: Wafers 2 are aligned so that the respective surfaces are in contact. A spacer 4, whose size is adjusted so that the accumulated error of the thicknesses at every specified number is offset, is arranged between the wafers. Outer peripheral parts of the wafers 2 and the spacers 4 are stuck to slice stage 3. The slice stage 3 is fixed to a block 5 and attached to a multiple-wire saw. The position of the block 5 is adjusted so that the center of the thickness of the arbitrary wafer 2a agrees with the central line of the wire 6, and the wafers 2 are sliced. The wafers 2 are divided into the sets of every specified number. The respective sets are separated by the specified interval and attached to the multiple-wire saw. The interval can be adjusted so that the center of the thickness of the arbitrary wafer agrees with the central line of the wire 6 for every set.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体ウェーハの
製造方法に係り、特に詳しくは、両面に不純物拡散層を
形成した半導体ウェーハを2分割する方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor wafer, and more particularly to a method for dividing a semiconductor wafer having an impurity diffusion layer formed on both surfaces into two parts.

【0002】[0002]

【従来の技術】パワートランジスタ、パワーMOS・F
ETなどいわゆるパワーデバイスの製造には、シリコン
ウェーハの片面に高濃度のドーパントを拡散させたウェ
ーハが用いられている。前記拡散ウェーハ(以下ウェー
ハという)は、所定の厚さにスライスしたシリコンウェ
ーハ(以下素材ウェーハという)に面取り、ラッピン
グ、エッチングを施した後、不純物雰囲気によるプレ拡
散を行い、更にドライブ拡散を施して素材ウェーハの両
面に所定の厚さの高濃度拡散層を形成する。次いで、こ
れらのウェーハの表面にワックスを塗布して互いに貼り
合わせ、インゴット状にした後、内周刃、マルチワイヤ
ソー等を用いてウェーハをそれぞれの面と平行にスライ
スして2分割する。マルチワイヤソーによる場合は、図
6に示すように、ウェーハ2の外周の一部をスライス台
3に貼着し、スライス台3をブロック5に固定してマル
チワイヤソーに取り付ける。そして、インゴット状に貼
着した多数のウェーハ2のうちほぼ中央に位置するウェ
ーハ2aの厚さの中心線をワイヤー6の中心線と一致さ
せた上、スライスする。これにより、ウェーハ2はそれ
ぞれ2枚ずつに分割される。マルチワイヤソーを用いた
場合は、最大270枚程度の拡散ウェーハを同時に分割
することができるため、内周刃を用いる場合よりも生産
性に優れている。
2. Description of the Related Art Power transistors, power MOS F
In the manufacture of so-called power devices such as ET, a wafer in which a high-concentration dopant is diffused on one side of a silicon wafer is used. The diffusion wafer (hereinafter referred to as “wafer”) is prepared by chamfering a silicon wafer (hereinafter referred to as “material wafer”) sliced to a predetermined thickness, performing lapping and etching, performing pre-diffusion in an impurity atmosphere, and further performing drive diffusion. A high concentration diffusion layer having a predetermined thickness is formed on both surfaces of the material wafer. Next, the surfaces of these wafers are coated with wax and adhered to each other to form an ingot, and the wafer is sliced in parallel with each surface using an inner peripheral blade, a multi-wire saw or the like, and divided into two. In the case of using a multi-wire saw, as shown in FIG. 6, a part of the outer periphery of the wafer 2 is attached to the slice table 3, and the slice table 3 is fixed to the block 5 and attached to the multi-wire saw. Then, the center line of the thickness of the wafer 2 a positioned substantially at the center of the large number of wafers 2 adhered in an ingot shape is made coincident with the center line of the wire 6 and then sliced. Thus, the wafer 2 is divided into two wafers. When a multi-wire saw is used, up to about 270 diffusion wafers can be divided at the same time, so that the productivity is better than when an inner peripheral blade is used.

【0003】上記方法でウェーハを2分割した後、ワッ
クスを剥がすと、片面に高濃度拡散層を有するウェーハ
が得られる。これらのウェーハに、平面研削及び面取り
を施した後、鏡面仕上げのための研磨を行って拡散ウェ
ーハが完成する。
After the wafer is divided into two parts by the above method, the wax is peeled off to obtain a wafer having a high concentration diffusion layer on one side. After performing surface grinding and chamfering on these wafers, polishing for mirror finishing is performed to complete a diffusion wafer.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、素材ウ
ェーハの厚さには許容限度内とはいえバラツキがあるた
め、拡散済みのウェーハをマルチワイヤソーでスライス
すると、インゴット状に貼着した多数のウェーハの長手
方向中央から両端に向かうにつれて、分割位置がウェー
ハの板厚の中心からずれる。そして、一括スライスする
ウェーハの枚数が多ければ多い程2分割後のウェーハの
厚さのバラツキが大きくなる。厚さが限度を超えて薄く
なったウェーハは、平面研削及び鏡面仕上げ工程におい
て仕上げ代が不足し、不良品になる。このような不良発
生を防止するため、素材ウェーハの厚さを厚くしておく
必要があり、素材コストの上昇を招いている。また、素
材ウェーハを厚くすると、2分割後の仕上げ代不足によ
る不良品は発生しないが、仕上げ代の異常に多いウェー
ハが発生するため、平面研削及び鏡面仕上げ工程におけ
る研削コストが上昇することになる。
However, since the thicknesses of the material wafers vary within the allowable limits even though they are within the allowable limit, when a wafer that has been diffused is sliced with a multi-wire saw, a large number of wafers stuck in an ingot shape can be obtained. The division position shifts from the center of the thickness of the wafer as it goes from the center in the longitudinal direction to both ends. The greater the number of wafers to be sliced at a time, the greater the variation in the thickness of the wafer after division into two. A wafer whose thickness has become thinner than the limit becomes insufficient in the finishing allowance in the surface grinding and mirror finishing processes, and becomes a defective product. In order to prevent such defects from occurring, it is necessary to increase the thickness of the material wafer, which increases the material cost. In addition, when the material wafer is thickened, defective products due to insufficient finishing allowance after the division into two do not occur, but wafers with an abnormally large finishing allowance are generated, so that the grinding cost in the surface grinding and mirror finishing processes increases. .

【0005】本発明は上記従来の問題点に着目してなさ
れたもので、拡散処理したウェーハを一括してマルチワ
イヤソーで2分割する工程において、分割後のウェーハ
の厚さのバラツキを一定限度以下に抑え、素材コスト及
び研削コストの低減を可能とする半導体ウェーハの製造
方法を提供することを目的としている。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems. In a process of dividing a wafer subjected to diffusion processing into two at once by a multi-wire saw, a variation in thickness of the divided wafer is reduced to a certain limit or less. It is an object of the present invention to provide a method of manufacturing a semiconductor wafer that can reduce material costs and grinding costs.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するた
め、本発明に係る半導体ウェーハの製造方法は、両面に
不純物の拡散層を形成した半導体ウェーハを表面に平行
にスライスする拡散ウェーハの2分割工程において、ウ
ェーハ相互の面を当接させて多数個並べ、ワイヤソーに
より一括してスライスする構成とした。
In order to achieve the above object, a method of manufacturing a semiconductor wafer according to the present invention is directed to a method of dividing a semiconductor wafer having an impurity diffusion layer formed on both surfaces into two parts by slicing the semiconductor wafer in parallel with the surface. In the process, a large number of wafers are arranged in contact with each other, and sliced collectively by a wire saw.

【0007】上記構成による拡散ウェーハのスライスに
当たり、多数個並べた拡散ウェーハの間に、前記ウェー
ハの厚さの誤差を調整するスペーサを配置することを特
徴としている。
In slicing the diffusion wafer having the above structure, a spacer for adjusting an error in the thickness of the wafer is arranged between a plurality of diffusion wafers.

【0008】また、拡散ウェーハのスライスに当たり、
所定個数の拡散ウェーハの相互の面を当接させて1組と
し、各組を所定間隔離間して配置してもよい。
Further, in slicing a diffusion wafer,
A predetermined number of diffusion wafers may be brought into contact with each other to form a set, and the sets may be arranged at predetermined intervals.

【0009】[0009]

【発明の実施の形態及び実施例】上記構成によれば、両
面に不純物拡散層を有する半導体ウェーハをワイヤソー
で一括スライスする際に、前記ウェーハ相互の面を当接
させて並べることにしたので、従来のようにウェーハ相
互の面を貼り合わせる必要がない。
According to the above construction, when a semiconductor wafer having impurity diffusion layers on both surfaces is sliced at once by a wire saw, the surfaces of the wafers are arranged in contact with each other. There is no need to bond the surfaces of the wafers as in the conventional case.

【0010】スライスすべきウェーハを多数個当接させ
て並べると、ウェーハの厚さの誤差が累積されて分割位
置のずれが次第に大きくなる。そこで、任意の個数ごと
にスペーサを配置し、前記個数におけるウェーハの厚さ
の累積誤差の影響を他のウェーハに及ぼさないようにス
ペーサの厚さを調整すれば、2分割後のウェーハの厚さ
のバラツキは全体的に小さくなる。ただし、この方法の
場合、各種の厚さのスペーサを取り揃えておくか、その
つど製作する必要がある。
When a large number of wafers to be sliced are arranged in contact with each other, errors in the thicknesses of the wafers are accumulated, and the deviation of the division position gradually increases. Therefore, by arranging spacers for each arbitrary number, and adjusting the thickness of the spacers so as not to affect the influence of the accumulated error of the thickness of the wafer on the number of wafers to other wafers, the thickness of the wafer after the division into two is obtained. The variation of the overall becomes small. However, in the case of this method, it is necessary to prepare spacers of various thicknesses or to manufacture them each time.

【0011】2分割後のウェーハの厚さのバラツキを低
減させる他の手段として、スライスすべきウェーハを所
定個数ごとに組分けし、各組を所定間隔だけ離間して配
置する方法がある。各組の基準となる位置、たとえば各
組の中央に位置するウェーハの厚さ中心がワイヤソーの
ワークローラに巻線されたワイヤー6中心線に一致する
ように各組の位置を調整すれば、2分割後のウェーハの
厚さのバラツキは更に小さくなる。
As another means for reducing the variation in the thickness of the wafer after the division into two, there is a method in which wafers to be sliced are grouped by a predetermined number, and the groups are arranged at predetermined intervals. If the position of each set is adjusted so that the reference position of each set, for example, the center of the thickness of the wafer positioned at the center of each set matches the center line of the wire 6 wound on the work roller of the wire saw, the position of each set is adjusted to 2 The variation in the thickness of the wafer after the division is further reduced.

【0012】次に、本発明に係る半導体ウェーハの製造
方法の実施例について図面を参照して説明する。図1は
ウェーハ貼り付け治具の側面図、図2はスライス台に貼
着されたウェーハの正面図、図3はマルチワイヤソーに
よるスライス方法を示す模式図で、いずれも第1実施例
を示す。
Next, an embodiment of a method of manufacturing a semiconductor wafer according to the present invention will be described with reference to the drawings. FIG. 1 is a side view of a wafer sticking jig, FIG. 2 is a front view of a wafer stuck on a slice table, and FIG. 3 is a schematic view showing a slicing method using a multi-wire saw, each showing a first embodiment.

【0013】マルチワイヤソーによるウェーハのスライ
ス手順は下記の通りである。 (1)ウェーハを、たとえば25枚を1組として複数の
組に分ける。1バッチが250枚からなる場合は、10
組に分けられる。 (2)各組ごとにウェーハの合計厚さTt を測定し、基
準値T0 との差δを求める。ウェーハの基準厚さをt0
、各ウェーハの実際の厚さをt1 ,t2 ,t3 ,・・
・,t25とすると、 Tt =t1 +t2 +t3 +・・・+t25 T0 =t0 ×25 δ =Tt −T0 (3)ウェーハをマルチワイヤソーでスライスする際
に、各組の間に挟み込むスペーサの厚さを決定する。ス
ペーサは、1組のウェーハの合計厚さの実測値Ttと基
準値T0 との差δ、つまり1組のウェーハにおける厚さ
の誤差の影響を次の組以降に及ぼさないようにするため
に使用するもので、ウェーハと同径の円板である。ま
た、スペーサの厚さは前記δ及びマルチワイヤソーのワ
イヤピッチに基づいて決定する。スペーサの厚さはδが
正の値ならばその分だけ薄くし、δが負の値ならばその
分だけ厚くする。このように、δの正負に対応する各種
厚さのスペーサを前もって製作しておき、これらの中か
ら適合する厚さのスペーサを選択して使用する。 (4)図1に示すウェーハ貼り付け治具1の基板1a上
に、ウェーハ2の外周に密接する円弧状の凹部を備えた
スライス台3を載置する。そして、各ウェーハ2及びス
ペーサ4の外周面をスライス台3の凹部にワックスで貼
着する。このとき、ウェーハ2及びスペーサ4の各面を
互いに当接させるため、ウェーハ貼り付け治具1のクラ
ンプ1bを締め付けて縦板1cと押さえ板1dとの間に
ウェーハ2及びスペーサ4を保持する。 (5)図2に示すように、ウェーハ2及びスペーサを貼
着したスライス台3をブロック5に固定し、ブロック5
をマルチワイヤソーに取り付ける。 (6)ワイヤソーのワークローラに巻線されたワイヤー
6、1本が任意の組の中央の位置に組み込まれたウェー
ハを正確に2分割する位置に来るように、ブロックの位
置を調整する。たとえば図3に示すように、第1組の1
3枚目のウェーハ2aの厚さの1/2の位置と13本目
のワイヤー6の中心線とが一致するように、ブロック5
の位置を調整する。前記ウェーハ2とワイヤー6との位
置調整は、顕微鏡を用いて行う。 (7)以上の手順を経た後、すべてのウェーハを同時に
スライスする。 (8)スライス完了後、ブロック5からスライス台3を
取り外し、ワックスを溶融してスライス台3からウェー
ハ2を分離する。これにより、片面に拡散層を有する5
00枚のウェーハが得られる。これらのウェーハを従来
方法と同様に平面研削と面取り及び鏡面加工する。
The procedure for slicing a wafer using a multi-wire saw is as follows. (1) Divide the wafers into a plurality of sets, for example, 25 wafers as one set. If one batch consists of 250 sheets, 10
Divided into pairs. (2) The total thickness Tt of the wafer is measured for each set, and the difference δ from the reference value T0 is determined. Set the reference thickness of the wafer to t0
, T1, t2, t3,...
.., T25, Tt = t1 + t2 + t3 +... + T25 T0 = t0.times.25.delta. = Tt-T0 (3) When slicing a wafer with a multi-wire saw, the thickness of the spacer sandwiched between each pair is set as follows. decide. The spacer is used to prevent the difference δ between the actual measured value Tt of the total thickness of one set of wafers and the reference value T0, that is, the influence of a thickness error in one set of wafers, from the next set onward. This is a disk having the same diameter as the wafer. The thickness of the spacer is determined based on the above-mentioned δ and the wire pitch of the multi-wire saw. If δ is a positive value, the thickness of the spacer is reduced by that amount, and if δ is a negative value, the thickness of the spacer is increased by that amount. In this way, spacers of various thicknesses corresponding to the positive and negative of δ are manufactured in advance, and a spacer having a suitable thickness is selected from these and used. (4) On the substrate 1a of the wafer bonding jig 1 shown in FIG. 1, a slice table 3 having an arc-shaped concave portion closely contacting the outer periphery of the wafer 2 is placed. Then, the outer peripheral surfaces of the respective wafers 2 and the spacers 4 are attached to the concave portions of the slice table 3 with wax. At this time, in order to bring the respective surfaces of the wafer 2 and the spacer 4 into contact with each other, the clamp 1b of the wafer bonding jig 1 is tightened to hold the wafer 2 and the spacer 4 between the vertical plate 1c and the holding plate 1d. (5) As shown in FIG. 2, the slice table 3 to which the wafer 2 and the spacer are adhered is fixed to the block 5,
To the multi-wire saw. (6) The position of the block is adjusted so that one wire 6, which is wound on the work roller of the wire saw, is located at a position where the wafer incorporated in the center position of an arbitrary set is exactly divided into two. For example, as shown in FIG.
The block 5 is moved so that the position of the thickness of the third wafer 2 a is 1 / and the center line of the thirteenth wire 6 is coincident.
Adjust the position of. The position adjustment between the wafer 2 and the wire 6 is performed using a microscope. (7) After the above procedure, all wafers are sliced simultaneously. (8) After slicing is completed, the slice table 3 is removed from the block 5, and the wax is melted to separate the wafer 2 from the slice table 3. Thereby, 5 having a diffusion layer on one side is obtained.
00 wafers are obtained. These wafers are subjected to surface grinding, chamfering, and mirror finishing as in the conventional method.

【0014】上記方法を用いて2分割したウェーハの中
心部における厚さのバラツキは、62μmであった。従
来の方法を用いた場合のウェーハ中心部の厚さのバラツ
キは140μmであるから、厚さのバラツキが44%に
低減したことになる。
The thickness variation at the center of the wafer divided into two using the above method was 62 μm. The variation in thickness at the center of the wafer when the conventional method is used is 140 μm, which means that the variation in thickness has been reduced to 44%.

【0015】図4、図5は本発明の第2実施例を示し、
図4はウェーハ貼り付け治具の側面図、図5はマルチワ
イヤソーによるスライス方法を示す模式図である。拡散
ウェーハのスライス手順は下記の通りである。 (1)ウェーハを、たとえば25枚を1組として複数の
組に分ける。1バッチが250枚からなる場合は、10
組に分けられる。 (2)図4に示すウェーハ貼り付け治具1の基板1a上
に、ウェーハ2の外周に密接する円弧状の凹部を備えた
スライス台7を載置する。このスライス台7は、ウェー
ハを25枚だけ貼着できる長さに製作されている。次
に、1組25枚のウェーハ2の外周面をスライス台7の
凹部にワックスで貼着する。このとき、1組のウェーハ
2の各面を互いに当接させるため、ウェーハ貼り付け治
具1のクランプ1bを締め付けて縦板1cと押さえ板1
dとの間に1組のウェーハ2を保持する。前記貼り付け
作業をすべての組について行う。なお、ウェーハ表面の
損傷を防止するため、各組のウェーハの両端にダミーウ
ェーハを取り付けてもよい。 (3)1組25枚のウェーハを貼着したスライス台をそ
れぞれ独立したブロックに固定した後、各ブロックをマ
ルチワイヤソーに直列に取り付ける。このとき、各組の
ウェーハ相互の間に所定の間隔を設ける。 (4)図5に示すように、ワイヤー6の中心線が各組の
中央の位置に組み込まれたウェーハ2aを正確に2分割
する位置に来るように、各ブロック8の位置を調整す
る。前記ウェーハ2とワイヤー6との位置調整は、顕微
鏡を用いて行う。 (5)以上の手順を経た後、すべてのウェーハを同時に
スライスする。 (6)スライス完了後、ブロック8からスライス台7を
取り外し、ワックスを溶融してスライス台7からウェー
ハ2を分離する。これにより、片面に拡散層を有する5
00枚のウェーハが得られる。これらのウェーハを従来
方法と同様に平面研削と面取り及び鏡面加工する。
FIGS. 4 and 5 show a second embodiment of the present invention.
FIG. 4 is a side view of a wafer bonding jig, and FIG. 5 is a schematic view showing a slicing method using a multi-wire saw. The procedure for slicing a diffusion wafer is as follows. (1) Divide the wafers into a plurality of sets, for example, 25 wafers as one set. If one batch consists of 250 sheets, 10
Divided into pairs. (2) On the substrate 1a of the wafer bonding jig 1 shown in FIG. 4, a slice table 7 having an arc-shaped concave portion closely contacting the outer periphery of the wafer 2 is placed. The slicing table 7 is manufactured to have a length capable of adhering only 25 wafers. Next, the outer peripheral surface of one set of 25 wafers 2 is attached to the concave portion of the slice table 7 with wax. At this time, in order to bring the respective surfaces of the set of wafers 2 into contact with each other, the clamp 1b of the wafer bonding jig 1 is tightened, and the vertical plate 1c and the holding plate 1
d, a set of wafers 2 is held. The pasting operation is performed for all the sets. In order to prevent damage to the wafer surface, dummy wafers may be attached to both ends of each set of wafers. (3) After fixing a slice table to which a set of 25 wafers are adhered to independent blocks, each block is attached to a multi-wire saw in series. At this time, a predetermined interval is provided between each set of wafers. (4) As shown in FIG. 5, the position of each block 8 is adjusted such that the center line of the wire 6 comes to a position where the wafer 2a assembled at the center position of each set is accurately divided into two. The position adjustment between the wafer 2 and the wire 6 is performed using a microscope. (5) After the above procedure, all wafers are sliced simultaneously. (6) After slicing is completed, the slice table 7 is removed from the block 8, and the wax is melted to separate the wafer 2 from the slice table 7. Thereby, 5 having a diffusion layer on one side is obtained.
00 wafers are obtained. These wafers are subjected to surface grinding, chamfering, and mirror finishing as in the conventional method.

【0016】上記方法を用いて2分割したウェーハの中
心部における厚さのバラツキは、53μmであった。従
来の方法を用いた場合のウェーハ中心部の厚さのバラツ
キは140μmであるから、厚さのバラツキが38%に
低減したことになる。
The thickness variation at the center of the wafer divided into two using the above method was 53 μm. When the conventional method is used, the thickness variation at the central portion of the wafer is 140 μm, which means that the thickness variation has been reduced to 38%.

【0017】第2実施例の場合、スペーサの選択や挟み
込みは不要となるが、ワイヤー6に対するウェーハの位
置合わせ(ブロック固定位置の調整)を各組ごとに行う
必要がある。2分割したウェーハの厚さのバラツキは第
1実施例より小さくなる。
In the case of the second embodiment, it is not necessary to select or pinch the spacer, but it is necessary to adjust the position of the wafer with respect to the wire 6 (adjustment of the block fixing position) for each set. The variation in the thickness of the divided wafer is smaller than that in the first embodiment.

【0018】[0018]

【発明の効果】以上説明したように本発明によれば、両
面に拡散層を形成した半導体ウェーハを一括して2分割
するに当たり、ウェーハを複数の組に分け、各組にスペ
ーサを配置または間隔をあけることによって、ウェーハ
の厚さのバラツキによる分割位置のずれを最小限に抑え
ることにしたので、分割後の厚さのバラツキは著しく低
減する。従って、素材ウェーハの厚さを従来より薄くし
ても、平面研削及び鏡面仕上げ代不足による不良品が発
生せず、素材コスト及び研削コストが低減する。
As described above, according to the present invention, when a semiconductor wafer having a diffusion layer formed on both surfaces is divided into two at a time, the wafer is divided into a plurality of sets, and spacers are arranged or spaced in each set. In this case, the deviation of the dividing position due to the variation in the thickness of the wafer is minimized, so that the variation in the thickness after the division is significantly reduced. Therefore, even if the thickness of the material wafer is made thinner than before, defective products due to insufficient surface grinding and mirror finishing allowance do not occur, and material cost and grinding cost are reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】第1実施例による貼り付け作業の説明図であ
る。
FIG. 1 is an explanatory diagram of a sticking operation according to a first embodiment.

【図2】スライス台に貼着されたウェーハの正面図であ
る。
FIG. 2 is a front view of a wafer attached to a slice table.

【図3】第1実施例によるスライス方法を示す模式図で
ある。
FIG. 3 is a schematic diagram showing a slicing method according to the first embodiment.

【図4】第2実施例による貼り付け作業の説明図であ
る。
FIG. 4 is an explanatory diagram of a sticking operation according to a second embodiment.

【図5】第2実施例によるスライス方法を示す模式図で
ある。
FIG. 5 is a schematic diagram showing a slicing method according to a second embodiment.

【図6】従来の技術によるスライス方法を示す模式図で
ある。
FIG. 6 is a schematic view showing a slicing method according to a conventional technique.

【符号の説明】[Explanation of symbols]

1 ウェーハ貼り付け治具 2,2a ウェーハ 3,7 スライス台 4 スペーサ 5,8 ブロック 6 ワイヤー DESCRIPTION OF SYMBOLS 1 Wafer bonding jig 2, 2a Wafer 3, 7 Slice table 4 Spacer 5, 8 Block 6 Wire

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 両面に不純物の拡散層を形成した半導体
ウェーハを表面に平行にスライスする拡散ウェーハの2
分割工程において、ウェーハ相互の面を当接させて多数
個並べ、ワイヤソーにより一括してスライスすることを
特徴とする半導体ウェーハの製造方法。
1. A diffusion wafer for slicing a semiconductor wafer having an impurity diffusion layer formed on both sides thereof in parallel with the surface.
A method for manufacturing a semiconductor wafer, comprising: in a dividing step, arranging a plurality of wafers in contact with each other and slicing them collectively by a wire saw.
【請求項2】 多数個並べた拡散ウェーハの間に、前記
ウェーハの厚さの誤差を調整するスペーサを配置するこ
とを特徴とする請求項1記載の半導体ウェーハの製造方
法。
2. The method of manufacturing a semiconductor wafer according to claim 1, wherein a spacer for adjusting a thickness error of the wafer is arranged between a plurality of diffusion wafers.
【請求項3】 所定個数の拡散ウェーハの相互の面を当
接させて1組とし、各組を所定間隔離間して配置するこ
とを特徴とする請求項1記載の半導体ウェーハの製造方
法。
3. The method for manufacturing a semiconductor wafer according to claim 1, wherein a predetermined number of diffusion wafers are brought into contact with each other to form a set, and the sets are arranged at predetermined intervals.
JP23717796A 1996-08-20 1996-08-20 Manufacturing method of semiconductor wafer Expired - Lifetime JP3839102B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23717796A JP3839102B2 (en) 1996-08-20 1996-08-20 Manufacturing method of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23717796A JP3839102B2 (en) 1996-08-20 1996-08-20 Manufacturing method of semiconductor wafer

Publications (2)

Publication Number Publication Date
JPH1058440A true JPH1058440A (en) 1998-03-03
JP3839102B2 JP3839102B2 (en) 2006-11-01

Family

ID=17011523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23717796A Expired - Lifetime JP3839102B2 (en) 1996-08-20 1996-08-20 Manufacturing method of semiconductor wafer

Country Status (1)

Country Link
JP (1) JP3839102B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118025A (en) * 2000-10-05 2002-04-19 Tdk Corp Cutting method using wire saw
KR100885006B1 (en) 2006-10-25 2009-02-20 실트로닉 아게 Method for simultaneously slicing at least two cylindrical workpieces into a multiplicity of wafers
CN102756432A (en) * 2012-08-07 2012-10-31 浙江富春江光电科技股份有限公司 Programmable logic controller (PLC) wafer cutting method
CN102941628A (en) * 2012-07-31 2013-02-27 南通皋鑫电子股份有限公司 Diode silicon stack cutting process and special tool thereof
JP2020192771A (en) * 2019-05-29 2020-12-03 住友金属鉱山株式会社 Method for producing thin sheet, multi-wire saw device, and method for cutting workpiece

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002118025A (en) * 2000-10-05 2002-04-19 Tdk Corp Cutting method using wire saw
JP4604330B2 (en) * 2000-10-05 2011-01-05 Tdk株式会社 Cutting method with wire saw
KR100885006B1 (en) 2006-10-25 2009-02-20 실트로닉 아게 Method for simultaneously slicing at least two cylindrical workpieces into a multiplicity of wafers
CN102941628A (en) * 2012-07-31 2013-02-27 南通皋鑫电子股份有限公司 Diode silicon stack cutting process and special tool thereof
CN102756432A (en) * 2012-08-07 2012-10-31 浙江富春江光电科技股份有限公司 Programmable logic controller (PLC) wafer cutting method
JP2020192771A (en) * 2019-05-29 2020-12-03 住友金属鉱山株式会社 Method for producing thin sheet, multi-wire saw device, and method for cutting workpiece

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