JPH1028052A - Clock generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for a voltage controlled oscillator for oscillating a high frequency even in the case of obtaining the frequency of a multiple including a decimal point by frequencydividing the output of the voltage controlled oscillator while switching plural frequency division values and feeding it back to a phase comparator. SOLUTION: The phase comparator 10, a filter and differential amplifier 11, the voltage controlled oscillator 12 and the frequency division counter 14 constitute a PLL, circuit. Then, the output Fdev for which the output Fout of the voltage controlled oscillator 12 is frequency-divided into 1/N is fed back to the phase comparator 10. Thus, the frequency of the output Fout becomes the N folds of the frequency of input Fin and is synchronized. By performing 1/N frequency division during the continuous clock number A of the output Fdev and performing 1/M frequency division during the next clock number B, the output Fout of the frequency for which the multiplying factor of (A.N +B.M)/(A+B) on average is multiplied with the input Fin is obtaind during the clock number A+B. It is sufficient that the voltage controlled oscillator is provided with the multiple which is the N folds and M folds of the input Fin and the multiplying factor larger than that is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock generator for generating a clock synchronized with an input phase signal.

[0002]

2. Description of the Related Art In an image recording apparatus or the like, when an image signal subjected to image processing is recorded on a film wound on the surface of a drum, it is necessary to record the image signal in synchronization with the rotation of the drum. FIG. 3 is a diagram showing an example of such an image recording apparatus. A drum 1 for recording an image signal in accordance with a rotational phase position, an encoder 2 for outputting a rotational phase signal of the drum, and an encoder 2 PLL (Phase Locked Loo) that outputs a clock synchronized with the input phase signal from
p) A circuit 3 and an image signal processing circuit 4 for performing image processing using this clock and outputting an image signal to the drum 1.

The encoder 2 outputs a phase signal Fin corresponding to the rotation of the drum 1, the PLL circuit 3 outputs a clock Fout synchronized with the signal Fin, and the image signal processing circuit 4 processes the image signal using the clock Fout. And output. By recording this image signal on the drum 1, an image signal synchronized with the rotation of the drum 1 is recorded. In this case, the signal Fin
The frequency of the signal Fout is usually different from that of the signal Fout, and the frequency obtained by dividing Fout by 1 / N by the dividing value N (integer) becomes the frequency of Fin (that is, the frequency N times Fin is the frequency of Fout). Then, a clock is generated by the PLL circuit 3.

FIG. 4 is a block diagram showing a configuration of the PLL circuit 3, and FIG. 5 is a timing chart of the PLL circuit 3. In FIG. 4, a PLL circuit 3 includes a phase comparator 5 that outputs a phase difference between two input clocks Fin and Fdev.
And a filter and a differential amplifier 6 for outputting a difference voltage corresponding to the phase difference, and a voltage controlled oscillator (VCO: Voltage Confrolled O) for outputting a clock Fout according to the input voltage.
scillator) 7 and the input clock Fou from this VCO 7
A frequency dividing counter 8 divides t by a set value N to generate a signal Fdev and outputs it to the phase comparator 5.

[0005] The VCO 7 is controlled so as to output a signal Fout having such a frequency that no phase difference occurs in the phase comparator 5. That is, the signal Fdev obtained by dividing the frequency of the output Fout by 1 / N is synchronized with the input signal Fin and has the same frequency. This synchronizes with the input signal Fin,
In order to obtain an output Fout having a frequency N times this Fin, the output Fde of the frequency divider obtained by dividing the frequency of Fout by 1 / N is used.
What is necessary is just to constitute the feedback loop which inputs v to the phase comparator 5.

In the timing chart of FIG. 5, the frequency of the output Fdev of the frequency dividing counter 8 is equal to the output Fou of the VCO 7.
The frequency of t is divided by 1 / N, and this Fde
v is synchronized with the input Fin and has the same frequency.

However, in such a device, since the set value N to the frequency dividing counter 8 is an integer, when it is desired to obtain a frequency of a magnification including a decimal point without deteriorating the precision, for example, the input frequency 12. When trying to get three times the frequency,
A 123-fold frequency was once obtained by using a VCO that outputs a 10-fold frequency, and this was divided into 1/10 to obtain a target 12.3-fold frequency.

FIG. 6 shows a configuration example of a PLL circuit for obtaining a frequency having a magnification including a decimal point. FIG. 7 is a timing chart of the apparatus shown in FIG. FIG. 6 shows VC
Output Fout obtained by dividing the frequency of output Fvco of O7 by 1 / n
Is provided as an output value. The frequency division counter 8 sets the output Fvco of the VCO 7 to 1 / N at the set value N1.
The frequency-divided signal Fdev is output. That is, the VCO 7 outputs a signal Fvco having a frequency that is N1 times the input signal Fin.
In FIG. 7, Fin and Fdev are synchronous signals having the same frequency, and both are frequencies obtained by dividing the frequency of Fvco by 1 / N1. Fout is a frequency obtained by dividing the frequency of Fvco by 1 / n. Here, in order to obtain an output Fout having a frequency 12.3 times the input Fin, the set value N1 of the frequency dividing counter 8 is set to 123 and the set value n of the frequency dividing counter 9 is set to n.
= 10.

[0009]

However, since a VCO having a frequency much larger than the desired magnification is required as described above, if the VCO is purchased as a product in the market, it becomes expensive, In addition, there is a problem that it often does not exist.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above-described problems, and has as its object to provide a clock generation device that does not require a VCO that oscillates a large frequency even when obtaining a multiple frequency including a decimal point. I do.

[0011]

A clock generating apparatus according to the present invention divides the output of a voltage controlled oscillator of a PLL circuit while switching between two divided values N and M (both are integers) and feeds back the divided output to a phase comparator. It is something to do. According to the present invention, it is possible to obtain an output signal similar to a signal obtained by multiplying an input signal by a magnification including a decimal point.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, an input signal F
in and Fdev a phase comparator that outputs a phase difference, a filter and a differential amplifier that output a difference voltage according to the phase difference,
A voltage controlled oscillator for generating a signal Fout corresponding to the difference voltage; a frequency dividing counter for dividing the signal Fout to output the input signal Fdev;
A frequency dividing selector for setting whether to divide by an (integer) or dividing by a dividing value M (integer), and counting the output clock of the frequency dividing counter, and setting a value A (integer) or B (integer) And a number counter for switching the frequency dividing values N and M of the frequency dividing selector according to the select signal, and a number of times for alternately setting the set value A and B to the frequency counter according to the select signal. And a selector.

A phase comparator, a filter, a differential amplifier, a voltage controlled oscillator, and a frequency dividing counter constitute a PLL circuit, and the output Fout of the voltage controlled oscillator is divided by 1 / N into Fde.
By feeding back v to the phase comparator, the frequency of the output Fout becomes N times the frequency of the input Fin and is synchronized. The frequency is divided by 1 / N during the continuous clock number A of the output Fdev and is divided by 1 / M during the next clock number B, so that the average is (A · A) during the clock number A + B.
An output Fout having a frequency obtained by multiplying Fin by a magnification of (N + BM) / (A + B) is obtained. The voltage controlled oscillator receives the input signal F
The magnification may be N times and M times as large as in. Since a larger magnification is not required, a commercially available product can be used. Further, by selecting the values of A, B, N, and M, the magnification including the decimal point can be obtained.

According to the second aspect of the present invention, the input signal Fin is a signal generated by a K (integer) clock every time one phenomenon occurs, M = N + 1, α is a decimal number less than 1, and K = A and B are set so that A + B and A: B ≒ (1-α) :( α).

As one phenomenon, for example, the number of clocks generated by the encoder connected to the drum for each rotation of the drum is K, M = N + 1, α is a decimal number less than 1, and K =
A such that A: B ≒ (1−α) :( α) in A + B,
When B is selected, the average magnification between clock numbers A + B (A · N
+ B · M) / (A + B) is N + α, which is a magnification including a decimal point.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the present embodiment, and FIG. 2 is a timing chart of the apparatus of the present embodiment. FIG. 1 shows the PLL circuit 3 shown in FIG. 3, and is configured as follows. A phase comparator 10 that outputs a phase difference between two input clocks of an input signal Fin from the encoder 2 and a signal Fdev that is fed back; a filter and a differential amplifier 11 that output a difference voltage between the two input signals; And a voltage-controlled oscillator (VC) that outputs a clock Fout according to the differential voltage of the differential amplifier 11.
O) 12 are provided. Fig. 4
Is similar to the conventional PLL circuit shown in FIG.

According to the selection signal, two division setting values N and M
(Both integers) are set and output by the frequency dividing selector 13;
A frequency dividing counter 14 for feeding back a value Fdev obtained by dividing the output Fout of the VCO 12 by 1 / N or 1 / M by the frequency dividing set values N and M set by the frequency dividing selector 13 to the phase comparator 10 and a selection signal. Two count setting values A and B
(Both integers) are selected and output, and the number of clocks of the signal Fdev output from the frequency division counter 14 is counted. Each time the counted value becomes A or B set by the number selector 15, the output is output. A frequency counter 16 that outputs a selection signal to be inverted to the frequency division selector 13 and the frequency selector 15 is provided.

Next, the operation will be described with reference to the timing chart of FIG. The phase comparator 10 outputs a phase difference between the input signal Fin from the encoder 2 and the signal Fdev from the frequency division counter 14, and the filter and the differential amplifier 11 output a difference voltage of the phase difference. Output an output signal Fout having such a frequency that no phase difference occurs. This output signal Fout is frequency-divided by the frequency dividing counter 14 by the set value M or N by 1 / M or 1 / N, and the signal Fout
dev, and eventually Fdev is controlled so as to synchronize with Fin and have the same frequency. Thus, Fout is output as a synchronized signal of M times or N times Fin.

When the logic of the selection signal SEL is "1", the frequency dividing selector 13 outputs the frequency dividing set value N, the frequency dividing counter 14 divides the signal Fout by 1 / N by the set value N, and outputs the signal Fde.
Print v. When the selection signal SEL is “1”, the number selector 15 sets the number setting value A in the number counter 16, and the number counter 16 counts the number of clocks of the output Fdev of the frequency dividing counter 14, and the setting value A , The logic of the selection signal SEL is inverted to “0”.

When the logic of the selection signal SEL is "0", the frequency division selector 13 outputs a frequency division set value M, and the frequency division counter 1
4 is a signal Fdev obtained by dividing the signal Fout by 1 / M by the set value M.
Is output. When the selection signal is "0", the frequency selector 15 sets the frequency setting value B in the frequency counter 16, and the frequency counter 16 outputs the output Fde of the frequency dividing counter 14.
When v is counted and reaches the set value B, the selection signal SEL is inverted to logic "1". This is repeated below.

As described above, the clock signal Fdev having the frequency obtained by dividing the output signal Fout of the VCO 12 by 1 / N is A times, and then the clock signal Fdev having the frequency obtained by dividing Fout by 1 / M.
Continues B times. In other words, the frequency of Fout is N times the frequency of Fin while the number of clocks of Fin is A, and the frequency of M is M times of Fin during B times. As a result, when the number of clocks generated by the encoder 2 per rotation of the drum 1 is A + B, the average frequency of the output Fout of the VCO 12 generated per rotation of the drum is β times the frequency of the output Fin of the encoder 2. . β is expressed by the following equation (1). β = (NA + MB) / (A + B) (1)

Specific examples of A, B, N, and M will be described. Assuming that the number of clocks generated by the encoder 2 for one rotation of the drum 1 in FIG. 3 is 1024, Fin is a signal for generating 1024 clocks for one rotation of the drum 1. Output Fou
t is divided by 1 / 12.3 so that it has the same frequency as Fin (that is, the frequency obtained by multiplying Fin by 12.3 is Fou).
t). At this time, the division setting value N = 12,
The frequency division set value M is set to 13, and the number-of-times set value A and the number-of-times set value B are determined by the following equations (2) and (3). A: B ≒ (1-0.3): 0.3 (2) 1024 = A + B (3)

According to the above equations (2) and (3), A and B are set to the integers A = 713 and B = 307 which are the closest to the ratio of 7: 3. By substituting A, B, and N, M into equation (1), a magnification β = 12.3 is obtained.

As described above, the present embodiment employs an interpolation method in which the two frequency division setting values of the frequency division counter of the PLL circuit are switched and used at the respective frequency setting values.
An error between the frequency of the desired clock and the frequency of the output clock is diffused within one rotation of the drum, and the error can be reduced.

[0025]

As is apparent from the above description, according to the present invention, two division setting values N,
M, which is switched and frequency-divided each time the number of clocks output from the frequency division counter reaches the set value A or B, thereby synchronizing with the input Fin and the average magnification β shown in the equation (1). Is obtained, the VCO to be used does not need to output a high frequency, and an effect similar to that of improving the resolution of the PLL circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a timing chart of the embodiment.

FIG. 3 is a diagram illustrating a configuration example of an image processing apparatus.

FIG. 4 is a diagram showing a configuration of a PLL circuit of the device shown in FIG. 3;

FIG. 5 is a timing chart of the PLL circuit of FIG. 4;

FIG. 6 shows a conventional PLL for obtaining a frequency having a magnification including a decimal point.
circuit diagram

FIG. 7 is a timing chart of the PLL circuit in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Drum 2 Encoder 3 PLL circuit 4 Image signal processing circuit 10 Phase comparator 11 Filter and differential amplifier 12 VCO 13 Divider selector 14 Divider counter 15 Number selector 16 Number counter

Claims (2)

[Claims] 1. A phase comparator for outputting a phase difference between input signals Fin and Fdev, a filter and a differential amplifier for outputting a difference voltage corresponding to the phase difference, and a signal F corresponding to the difference voltage.
out, a frequency-controlled oscillator that divides this signal Fout and outputs the input signal Fdev,
A frequency division selector for setting whether the frequency division counter performs frequency division with a frequency division value N (integer) or frequency division value M (integer);
The output clock of the frequency division counter is counted, and a set value A
(Integer) or B (integer), a select signal is generated, and the select signal is used to switch the frequency dividing values N and M of the frequency dividing selector. And a number selector for alternately setting B and B. 2. The input signal Fin is a signal generated by a K (integer) clock every time one phenomenon occurs, and M =
2. The clock according to claim 1, wherein N + 1, α is a decimal number less than 1, and A and B are set so that K = A + B and A: B ≒ (1−α) :( α). Generator.