JPH10198597A5 - - Google Patents

Info

Publication number
JPH10198597A5
JPH10198597A5 JP1997338054A JP33805497A JPH10198597A5 JP H10198597 A5 JPH10198597 A5 JP H10198597A5 JP 1997338054 A JP1997338054 A JP 1997338054A JP 33805497 A JP33805497 A JP 33805497A JP H10198597 A5 JPH10198597 A5 JP H10198597A5
Authority
JP
Japan
Prior art keywords
register
registers
data stream
providing
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997338054A
Other languages
English (en)
Japanese (ja)
Other versions
JP3896204B2 (ja
JPH10198597A (ja
Filing date
Publication date
Priority claimed from US08/757,606 external-priority patent/US5941974A/en
Application filed filed Critical
Publication of JPH10198597A publication Critical patent/JPH10198597A/ja
Publication of JPH10198597A5 publication Critical patent/JPH10198597A5/ja
Application granted granted Critical
Publication of JP3896204B2 publication Critical patent/JP3896204B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP33805497A 1996-11-29 1997-11-21 直列的に提供されるデータストリームのためのレジスタ格納先を選択する方法 Expired - Fee Related JP3896204B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/757,606 1996-11-29
US08/757,606 US5941974A (en) 1996-11-29 1996-11-29 Serial interface with register selection which uses clock counting, chip select pulsing, and no address bits

Publications (3)

Publication Number Publication Date
JPH10198597A JPH10198597A (ja) 1998-07-31
JPH10198597A5 true JPH10198597A5 (enExample) 2005-07-14
JP3896204B2 JP3896204B2 (ja) 2007-03-22

Family

ID=25048498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33805497A Expired - Fee Related JP3896204B2 (ja) 1996-11-29 1997-11-21 直列的に提供されるデータストリームのためのレジスタ格納先を選択する方法

Country Status (3)

Country Link
US (1) US5941974A (enExample)
JP (1) JP3896204B2 (enExample)
KR (1) KR100484330B1 (enExample)

Families Citing this family (56)

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US6351139B1 (en) * 2000-04-01 2002-02-26 Cypress Semiconductor Corp. Configuration bit read/write data shift register
JP2002140030A (ja) * 2000-10-31 2002-05-17 Seiko Epson Corp カラー表示方法及びそれを用いる半導体集積回路
US20030154221A1 (en) * 2002-02-13 2003-08-14 Sun Microsystems, Inc. System and method for accessing file system entities
DE102004025899B4 (de) * 2004-05-27 2010-06-10 Qimonda Ag Verfahren zum Aktivieren und Deaktivieren von elektronischen Schaltungseinheiten und Schaltungsanordnung zur Durchführung des Verfahrens
US7514964B2 (en) * 2005-03-18 2009-04-07 California Institute Of Technology Universal programmable logic gate and routing method
US20070076502A1 (en) * 2005-09-30 2007-04-05 Pyeon Hong B Daisy chain cascading devices
US7652922B2 (en) * 2005-09-30 2010-01-26 Mosaid Technologies Incorporated Multiple independent serial link memory
US11948629B2 (en) 2005-09-30 2024-04-02 Mosaid Technologies Incorporated Non-volatile memory device with concurrent bank operations
US7747833B2 (en) * 2005-09-30 2010-06-29 Mosaid Technologies Incorporated Independent link and bank selection
KR101293365B1 (ko) 2005-09-30 2013-08-05 모사이드 테크놀로지스 인코퍼레이티드 출력 제어 메모리
US20070165457A1 (en) * 2005-09-30 2007-07-19 Jin-Ki Kim Nonvolatile memory system
JP5073935B2 (ja) * 2005-10-06 2012-11-14 オンセミコンダクター・トレーディング・リミテッド シリアルデータ入力システム
US8364861B2 (en) * 2006-03-28 2013-01-29 Mosaid Technologies Incorporated Asynchronous ID generation
US8069328B2 (en) * 2006-03-28 2011-11-29 Mosaid Technologies Incorporated Daisy chain cascade configuration recognition technique
US8335868B2 (en) * 2006-03-28 2012-12-18 Mosaid Technologies Incorporated Apparatus and method for establishing device identifiers for serially interconnected devices
US7551492B2 (en) * 2006-03-29 2009-06-23 Mosaid Technologies, Inc. Non-volatile semiconductor memory with page erase
JP5214587B2 (ja) * 2006-03-31 2013-06-19 モスエイド テクノロジーズ インコーポレイテッド フラッシュメモリシステムコントロールスキーム
KR100800383B1 (ko) * 2006-08-18 2008-02-01 삼성전자주식회사 시프트 레지스터 및 시프트 레지스터에 전기적 퓨즈를적용하는 방법
US7904639B2 (en) * 2006-08-22 2011-03-08 Mosaid Technologies Incorporated Modular command structure for memory and memory system
EP2487794A3 (en) * 2006-08-22 2013-02-13 Mosaid Technologies Incorporated Modular command structure for memory and memory system
US8700818B2 (en) * 2006-09-29 2014-04-15 Mosaid Technologies Incorporated Packet based ID generation for serially interconnected devices
US7817470B2 (en) 2006-11-27 2010-10-19 Mosaid Technologies Incorporated Non-volatile memory serial core architecture
US8010709B2 (en) * 2006-12-06 2011-08-30 Mosaid Technologies Incorporated Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
US7853727B2 (en) * 2006-12-06 2010-12-14 Mosaid Technologies Incorporated Apparatus and method for producing identifiers regardless of mixed device type in a serial interconnection
US8271758B2 (en) 2006-12-06 2012-09-18 Mosaid Technologies Incorporated Apparatus and method for producing IDS for interconnected devices of mixed type
US7818464B2 (en) * 2006-12-06 2010-10-19 Mosaid Technologies Incorporated Apparatus and method for capturing serial input data
US8331361B2 (en) * 2006-12-06 2012-12-11 Mosaid Technologies Incorporated Apparatus and method for producing device identifiers for serially interconnected devices of mixed type
US7529149B2 (en) * 2006-12-12 2009-05-05 Mosaid Technologies Incorporated Memory system and method with serial and parallel modes
US8984249B2 (en) * 2006-12-20 2015-03-17 Novachips Canada Inc. ID generation apparatus and method for serially interconnected devices
US8010710B2 (en) * 2007-02-13 2011-08-30 Mosaid Technologies Incorporated Apparatus and method for identifying device type of serially interconnected devices
US20080201588A1 (en) * 2007-02-16 2008-08-21 Mosaid Technologies Incorporated Semiconductor device and method for reducing power consumption in a system having interconnected devices
US8122202B2 (en) 2007-02-16 2012-02-21 Peter Gillingham Reduced pin count interface
US8086785B2 (en) 2007-02-22 2011-12-27 Mosaid Technologies Incorporated System and method of page buffer operation for memory devices
US7796462B2 (en) 2007-02-22 2010-09-14 Mosaid Technologies Incorporated Data flow control in multiple independent port
US8046527B2 (en) * 2007-02-22 2011-10-25 Mosaid Technologies Incorporated Apparatus and method for using a page buffer of a memory device as a temporary cache
US7913128B2 (en) * 2007-11-23 2011-03-22 Mosaid Technologies Incorporated Data channel test apparatus and method thereof
US8825939B2 (en) * 2007-12-12 2014-09-02 Conversant Intellectual Property Management Inc. Semiconductor memory device suitable for interconnection in a ring topology
US7983099B2 (en) 2007-12-20 2011-07-19 Mosaid Technologies Incorporated Dual function compatible non-volatile memory device
US7940572B2 (en) * 2008-01-07 2011-05-10 Mosaid Technologies Incorporated NAND flash memory having multiple cell substrates
US8594110B2 (en) * 2008-01-11 2013-11-26 Mosaid Technologies Incorporated Ring-of-clusters network topologies
US8139390B2 (en) * 2008-07-08 2012-03-20 Mosaid Technologies Incorporated Mixed data rates in memory devices and systems
US7957173B2 (en) * 2008-10-14 2011-06-07 Mosaid Technologies Incorporated Composite memory having a bridging device for connecting discrete memory devices to a system
US8134852B2 (en) 2008-10-14 2012-03-13 Mosaid Technologies Incorporated Bridge device architecture for connecting discrete memory devices to a system
US8549209B2 (en) * 2008-11-04 2013-10-01 Mosaid Technologies Incorporated Bridging device having a configurable virtual page size
US20100115172A1 (en) * 2008-11-04 2010-05-06 Mosaid Technologies Incorporated Bridge device having a virtual page buffer
JP2010271091A (ja) 2009-05-20 2010-12-02 Seiko Epson Corp 周波数測定装置
JP5517033B2 (ja) 2009-05-22 2014-06-11 セイコーエプソン株式会社 周波数測定装置
JP5440999B2 (ja) 2009-05-22 2014-03-12 セイコーエプソン株式会社 周波数測定装置
US8521980B2 (en) * 2009-07-16 2013-08-27 Mosaid Technologies Incorporated Simultaneous read and write data transfer
JP5582447B2 (ja) * 2009-08-27 2014-09-03 セイコーエプソン株式会社 電気回路、同電気回路を備えたセンサーシステム、及び同電気回路を備えたセンサーデバイス
JP5815918B2 (ja) 2009-10-06 2015-11-17 セイコーエプソン株式会社 周波数測定方法、周波数測定装置及び周波数測定装置を備えた装置
JP5876975B2 (ja) 2009-10-08 2016-03-02 セイコーエプソン株式会社 周波数測定装置及び周波数測定装置における変速分周信号の生成方法
US8582382B2 (en) * 2010-03-23 2013-11-12 Mosaid Technologies Incorporated Memory system having a plurality of serially connected devices
JP5883558B2 (ja) 2010-08-31 2016-03-15 セイコーエプソン株式会社 周波数測定装置及び電子機器
US8825967B2 (en) 2011-12-08 2014-09-02 Conversant Intellectual Property Management Inc. Independent write and read control in serially-connected devices
KR102225314B1 (ko) * 2014-11-17 2021-03-10 에스케이하이닉스 주식회사 반도체 장치 및 동작 방법

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR930007185B1 (ko) * 1989-01-13 1993-07-31 가부시키가이샤 도시바 레지스터뱅크회로
JPH0454652A (ja) * 1990-06-25 1992-02-21 Nec Corp マイクロコンピュータ
US5157342A (en) * 1991-08-30 1992-10-20 The United States Of America As Represented By The Secretary Of The Navy Precision digital phase lock loop circuit
US5530911A (en) * 1994-07-15 1996-06-25 Motorola, Inc. Method and apparatus for battery drain reduction by adjusting for dynamic changes of receiver warm-up time

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