JPH10143461A5 - - Google Patents

Info

Publication number
JPH10143461A5
JPH10143461A5 JP1997295410A JP29541097A JPH10143461A5 JP H10143461 A5 JPH10143461 A5 JP H10143461A5 JP 1997295410 A JP1997295410 A JP 1997295410A JP 29541097 A JP29541097 A JP 29541097A JP H10143461 A5 JPH10143461 A5 JP H10143461A5
Authority
JP
Japan
Prior art keywords
peripheral
memory
card
normal operation
during normal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1997295410A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10143461A (ja
Filing date
Publication date
Priority claimed from US08/743,618 external-priority patent/US6038621A/en
Application filed filed Critical
Publication of JPH10143461A publication Critical patent/JPH10143461A/ja
Publication of JPH10143461A5 publication Critical patent/JPH10143461A5/ja
Pending legal-status Critical Current

Links

JP9295410A 1996-11-04 1997-10-28 周辺装置システム Pending JPH10143461A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US743,618 1996-11-04
US08/743,618 US6038621A (en) 1996-11-04 1996-11-04 Dynamic peripheral control of I/O buffers in peripherals with modular I/O

Publications (2)

Publication Number Publication Date
JPH10143461A JPH10143461A (ja) 1998-05-29
JPH10143461A5 true JPH10143461A5 (https=) 2005-02-17

Family

ID=24989478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9295410A Pending JPH10143461A (ja) 1996-11-04 1997-10-28 周辺装置システム

Country Status (4)

Country Link
US (1) US6038621A (https=)
EP (1) EP0840202B1 (https=)
JP (1) JPH10143461A (https=)
DE (1) DE69719669T2 (https=)

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US6654861B2 (en) * 2001-07-18 2003-11-25 Smart Matic Corp. Method to manage multiple communication queues in an 8-bit microcontroller
US7581026B2 (en) * 2001-12-28 2009-08-25 Intel Corporation Communicating transaction types between agents in a computer system using packet headers including format and type fields
US20040006633A1 (en) * 2002-07-03 2004-01-08 Intel Corporation High-speed multi-processor, multi-thread queue implementation
US7089282B2 (en) * 2002-07-31 2006-08-08 International Business Machines Corporation Distributed protocol processing in a data processing system
US7200844B2 (en) * 2002-08-08 2007-04-03 Hewlett-Packard Development Company, Lp. User installation of imaging device control system
US7757232B2 (en) * 2003-08-14 2010-07-13 Hewlett-Packard Development Company, L.P. Method and apparatus for implementing work request lists
US7617376B2 (en) * 2003-08-14 2009-11-10 Hewlett-Packard Development Company, L.P. Method and apparatus for accessing a memory
US8959171B2 (en) 2003-09-18 2015-02-17 Hewlett-Packard Development Company, L.P. Method and apparatus for acknowledging a request for data transfer
US7404190B2 (en) * 2003-09-18 2008-07-22 Hewlett-Packard Development Company, L.P. Method and apparatus for providing notification via multiple completion queue handlers
US8150996B2 (en) * 2003-12-16 2012-04-03 Hewlett-Packard Development Company, L.P. Method and apparatus for handling flow control for a data transfer
WO2007139426A1 (en) * 2006-05-31 2007-12-06 Intel Corporation Multiple phase buffer enlargement for rdma data transfer
US20080147896A1 (en) * 2006-10-10 2008-06-19 Nokia Corporation Method, electronic device, computer program product and circuit assembly for memory allocation
US7990724B2 (en) 2006-12-19 2011-08-02 Juhasz Paul R Mobile motherboard
US8671153B1 (en) 2010-08-20 2014-03-11 Acqis Llc Low cost, high performance and high data throughput server blade
US9965323B2 (en) 2015-03-11 2018-05-08 Western Digital Technologies, Inc. Task queues
US10108518B2 (en) * 2016-04-07 2018-10-23 International Business Machines Corporation Device interference detection and remediation

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US4688166A (en) * 1984-08-03 1987-08-18 Motorola Computer Systems, Inc. Direct memory access controller supporting multiple input/output controllers and memory units
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