JPH10135386A - Manufacturing methd of semiconductor bare chip - Google Patents

Manufacturing methd of semiconductor bare chip

Info

Publication number
JPH10135386A
JPH10135386A JP28714896A JP28714896A JPH10135386A JP H10135386 A JPH10135386 A JP H10135386A JP 28714896 A JP28714896 A JP 28714896A JP 28714896 A JP28714896 A JP 28714896A JP H10135386 A JPH10135386 A JP H10135386A
Authority
JP
Japan
Prior art keywords
wafer
bonding material
semiconductor bare
bare chip
radiation plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP28714896A
Other languages
Japanese (ja)
Inventor
Yoshiki Suzuki
芳規 鈴木
Michio Muraida
道夫 村井田
Yoshishige Nakada
圭成 中田
Kazutaka Suzuki
一高 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP28714896A priority Critical patent/JPH10135386A/en
Publication of JPH10135386A publication Critical patent/JPH10135386A/en
Withdrawn legal-status Critical Current

Links

Landscapes

  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain semiconductor bare chips having radiation plates integrated therewith, by such a simple procedure that after sticking one radiation plate on a wafer, the resultant product is merely divided into the bare chips. SOLUTION: On a wafer 1, electronic circuits are formed in a predetermined array. Then, to the rear surface of the wafer 1, a bonding material 2 is applied with a uniform thickness. As the bonding material 2, there is used a silicon bonding material having both an elasticity capable of absorbing a stressed strain caused by the difference between thermal expansion coefficients and an excellent thermal conductivity. Then, on the coated surface of the wafer 1 with the bonding material 2, a radiation plate 3 having the same outer diameter as the wafer 1 and made of a thermally conductive metal is so stuck that no bubble is included between them. Then, pressing relatively the radiation plate 3 against the wafer 1, the excess bonding material 2 is extruded from between the wafer 1 and the radiation plate 3 to make the thickness of the bonding material 2 as small as possible. Then, dividing the wafer 1 with the stuck radiation plate 3 thereon into individual chips by lines L laid along the boundaries among the formed circuits, semiconductor bare chips 4 are obtained.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、フリップチップボ
ンディング法によって回路基板等に接続される半導体ベ
アチップの製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor bare chip connected to a circuit board or the like by a flip chip bonding method.

【0002】[0002]

【従来の技術】この種の半導体ベアチップは、ウエファ
の状態で拡散,開孔,配線,電極形成,保護膜形成,電
気特性検査等の工程を実施した後、該ウエファをダイシ
ング法やスクライバ法によって個々のチップに分離する
ことにより製造されている。
2. Description of the Related Art A semiconductor bare chip of this kind is subjected to processes such as diffusion, opening, wiring, electrode formation, formation of a protective film, and inspection of electrical characteristics in a wafer state, and then the wafer is subjected to a dicing method or a scriber method. It is manufactured by separating into individual chips.

【0003】この半導体ベアチップの放熱対策として
は、半導体ベアチップを回路基板に搭載した後これに放
熱グリス等を介して放熱板を取り付ける方式が一般に採
用されている。
As a measure for radiating the heat of the semiconductor bare chip, a method of mounting the semiconductor bare chip on a circuit board and then attaching a heat radiating plate thereto through a heat radiating grease or the like is generally adopted.

【0004】[0004]

【発明が解決しようとする課題】上記従来の放熱対策
は、半導体ベアチップに個別に放熱板を後付けする方式
であるため、半導体ベアチップの種類毎に大きさや厚み
の異なる放熱板を用意する必要があると共に、接着剤や
放熱グリスの塗布作業に加え、放熱板の搭載作業を別途
要する面倒があり、後付けに係るコスト増加を否めない
不具合がある。
Since the above-mentioned conventional heat dissipation measures are of a type in which a heat radiating plate is separately attached to a semiconductor bare chip, it is necessary to prepare heat radiating plates having different sizes and thicknesses for each type of semiconductor bare chip. At the same time, in addition to the work of applying the adhesive and the heat radiation grease, the work of mounting the heat radiating plate is troublesome, and there is a problem that the increase in the cost of retrofitting cannot be denied.

【0005】本発明は上記事情に鑑みてなされたもの
で、その目的とするところは、放熱板の後付けを不要と
した半導体ベアチップの製造方法を提供することにあ
る。
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor bare chip which does not require a retrofit of a heat sink.

【0006】[0006]

【課題を解決するための手段】上記目的を達成するた
め、本発明に係る半導体ベアチップの製造方法は、電子
回路が所定配列で形成されたウエファの裏面に接着材を
介して放熱板を張り合わせた後、放熱板が張り合わされ
たウエファを個々のチップに分離する、ことをその主た
る特徴としている。
In order to achieve the above-mentioned object, a method of manufacturing a semiconductor bare chip according to the present invention comprises bonding a heat sink through a bonding material to the back surface of a wafer having electronic circuits formed in a predetermined arrangement. Thereafter, the main feature is that the wafer to which the heat sink is attached is separated into individual chips.

【0007】本発明に係る半導体ベアチップの製造方法
によれば、ウエファに放熱板を張り付けてからこれを分
離するだけの簡単な手順にて、放熱部を一体に備えた半
導体ベアチップを得ることができる。
According to the method of manufacturing a semiconductor bare chip according to the present invention, a semiconductor bare chip integrally provided with a heat radiating portion can be obtained by a simple procedure in which a heat radiating plate is attached to a wafer and then separated. .

【0008】[0008]

【発明の実施の形態】図1は本発明の一実施形態を示す
もので、図中の1はウエファ、2は接着材、3は放熱
板、Lは分離ライン、4は半導体ベアチップである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention, in which 1 is a wafer, 2 is an adhesive, 3 is a heat sink, L is a separation line, and 4 is a semiconductor bare chip.

【0009】半導体ベアチップの製造に際しては、ま
ず、図1(a)に示すように、シリコン,GaAs等か
ら成るウエファ1に、拡散,開孔,配線,電極形成,保
護膜形成,電気特性検査等の工程を実施してIC,LS
I等の電子回路を所定配列で形成する。ウエファ1への
回路形成手順は周知のものと同じであるためここでの説
明を省略する。
In manufacturing a semiconductor bare chip, first, as shown in FIG. 1A, a wafer 1 made of silicon, GaAs or the like is diffused, opened, formed with wiring, formed electrodes, formed with a protective film, inspected for electrical characteristics, and the like. IC, LS
Electronic circuits such as I are formed in a predetermined arrangement. The procedure for forming a circuit on the wafer 1 is the same as a well-known procedure, and a description thereof will be omitted.

【0010】次に、同図(b)に示すように、ウエファ
1の裏面(回路形成面とは反対側の面)に接着材2を均
一な厚みで塗布する。この接着材2には周知の接着材を
種々用いることが可能であるが、半田やろう材等を用い
るとウエファ1と放熱板3とが強固に結合され、両者の
熱膨張係数の差による応力歪みを原因としてクラックが
発生する恐れがあるので、好ましくは、この応力歪みを
吸収可能な弾力性を持ち且つ熱伝導性に優れたシリコン
系接着材を使用する。
Next, as shown in FIG. 1B, an adhesive 2 is applied to the back surface (surface opposite to the circuit forming surface) of the wafer 1 with a uniform thickness. Various known adhesives can be used for the adhesive 2, but if solder or brazing material is used, the wafer 1 and the radiator plate 3 are firmly joined, and the stress due to the difference in the coefficient of thermal expansion between the two. Since cracks may be generated due to distortion, it is preferable to use a silicon-based adhesive having elasticity capable of absorbing the stress distortion and having excellent thermal conductivity.

【0011】次に、同図(c)に示すように、ウエファ
1の接着材塗布面に、ウエファ1と同一外径を有する放
熱板、例えば熱伝導性の良い金,銀,アルミニウム等の
金属から成る放熱板3を気泡が入らぬようにして張り付
ける。勿論、放熱板3の一面に上記接着材2を塗布して
から、これをウエファ1の回路形成面とは反対側の面に
張り合わせるようにしてもよい。放熱板3の厚みはウェ
ファ1に形成された電子回路の発熱量に応じて適宜選定
される。
Next, as shown in FIG. 1C, a heat radiating plate having the same outer diameter as the wafer 1, for example, a metal such as gold, silver, or aluminum having good heat conductivity is provided on the surface of the wafer 1 on which the adhesive is applied. Is attached so that air bubbles do not enter. Of course, the adhesive 2 may be applied to one surface of the heat sink 3 and then bonded to the surface of the wafer 1 on the side opposite to the circuit forming surface. The thickness of the heat radiating plate 3 is appropriately selected according to the heat value of the electronic circuit formed on the wafer 1.

【0012】そして、接着材硬化前に放熱板3をウエフ
ァ1に相対的に押し付け、ウエファ1と放熱板3の間か
ら余分な接着材2を押し出してその厚みを極力薄くす
る。押し出された接着材は硬化後に取り除く。
Then, before the adhesive is hardened, the heat radiating plate 3 is pressed relatively to the wafer 1, and the excess adhesive 2 is pushed out from between the wafer 1 and the heat radiating plate 3 to reduce its thickness as much as possible. The extruded adhesive is removed after curing.

【0013】次に、同図(d)に示すように、放熱板3
が張り合わされたウエファ1を、周知のダイシング法や
スクライバ法によって形成回路の境界に沿ったラインL
で個々のチップに分離し、同図(e)に示すような半導
体ベアチップ4を得る。
Next, as shown in FIG.
Is bonded to a wafer 1 along a boundary of a formed circuit by a known dicing method or a scriber method.
To separate the individual chips to obtain a semiconductor bare chip 4 as shown in FIG.

【0014】この半導体ベアチップ4は、矩形状のチッ
プ部4aと放熱部4bとが接着材層4cを介して上下に
結合した構造を有しており、放熱部4bが外側に向くよ
うにしてフリップチップボンディング法により回路基板
等に接続される。
The semiconductor bare chip 4 has a structure in which a rectangular chip portion 4a and a heat radiating portion 4b are vertically coupled via an adhesive layer 4c, and the flip is performed such that the heat radiating portion 4b faces outward. It is connected to a circuit board or the like by a chip bonding method.

【0015】上述の実施形態によれば、ウエファ1に放
熱板3を張り付けてからこれを分離するだけの簡単な手
順にて、放熱部4bを一体に備えた半導体ベアチップ4
を得ることができるので、従来のように半導体ベアチッ
プに個別に放熱板を後付けする面倒がなく、後付けに係
るコスト増加を回避できる利点がある。
According to the above-described embodiment, the semiconductor bare chip 4 integrally provided with the heat radiating portion 4b can be formed by a simple procedure in which the heat radiating plate 3 is attached to the wafer 1 and then separated.
Therefore, there is no need to separately attach a heat sink to the semiconductor bare chip as in the related art, and there is an advantage that an increase in cost associated with the attachment can be avoided.

【0016】また、接着材2として、弾力性を持ち且つ
熱伝導性に優れたシリコン系接着材を用いれば、ウエフ
ァ1と放熱板3との熱膨張係数の差による応力歪みを吸
収してクラック発生を未然に防止できる利点がある。
If a silicon-based adhesive having elasticity and excellent thermal conductivity is used as the adhesive 2, stress distortion due to a difference in thermal expansion coefficient between the wafer 1 and the heat radiating plate 3 is absorbed and cracks are generated. There is an advantage that occurrence can be prevented beforehand.

【0017】[0017]

【発明の効果】以上詳述したように、本発明によれば、
ウエファに放熱板を張り付けてからこれを分離するだけ
の簡単な手順にて、放熱部を一体に備えた半導体ベアチ
ップを得ることができるので、従来のように半導体ベア
チップに個別に放熱板を後付けする面倒がなく、後付け
に係るコスト増加を回避できる利点がある。
As described in detail above, according to the present invention,
With a simple procedure of simply attaching a heat sink to a wafer and then separating the heat sink, a semiconductor bare chip having an integrated heat sink can be obtained. There is an advantage that there is no trouble and an increase in cost associated with retrofitting can be avoided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態を示す図FIG. 1 shows an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…ウエファ、2…接着材、3…放熱板、L…分離ライ
ン、4…半導体ベアチップ、4a…チップ部、4b…放
熱部、4c…接着材層。
DESCRIPTION OF SYMBOLS 1 ... Wafer, 2 ... Adhesive material, 3 ... Heat sink, L ... Separation line, 4 ... Semiconductor bare chip, 4a ... Chip part, 4b ... Heat radiating part, 4c ... Adhesive material layer.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 鈴木 一高 東京都台東区上野6丁目16番20号 太陽誘 電株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ichitaka Suzuki 6-16-20 Ueno, Taito-ku, Tokyo Taiyo Denki Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 電子回路が所定配列で形成されたウエフ
ァの裏面に接着材を介して放熱板を張り合わせた後、放
熱板が張り合わされたウエファを個々のチップに分離す
る、 ことを特徴とする半導体ベアチップの製造方法。
An electronic circuit, comprising: bonding a heat radiating plate to the back surface of a wafer formed in a predetermined arrangement via an adhesive; and separating the wafer bonded with the heat radiating plate into individual chips. A method for manufacturing a semiconductor bare chip.
【請求項2】 接着材硬化前に放熱板をウエファに相対
的に押し付けて余分な接着材を押し出す、 ことを特徴とする請求項1記載の半導体ベアチップの製
造方法。
2. The method for manufacturing a semiconductor bare chip according to claim 1, wherein a heat radiating plate is pressed relatively to the wafer before the adhesive is hardened to push out an excess adhesive.
【請求項3】 接着材としてシリコン系接着材を用い
た、 ことを特徴とする請求項1または2記載の半導体ベアチ
ップの製造方法。
3. The method for manufacturing a semiconductor bare chip according to claim 1, wherein a silicon-based adhesive is used as the adhesive.
JP28714896A 1996-10-29 1996-10-29 Manufacturing methd of semiconductor bare chip Withdrawn JPH10135386A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28714896A JPH10135386A (en) 1996-10-29 1996-10-29 Manufacturing methd of semiconductor bare chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28714896A JPH10135386A (en) 1996-10-29 1996-10-29 Manufacturing methd of semiconductor bare chip

Publications (1)

Publication Number Publication Date
JPH10135386A true JPH10135386A (en) 1998-05-22

Family

ID=17713701

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28714896A Withdrawn JPH10135386A (en) 1996-10-29 1996-10-29 Manufacturing methd of semiconductor bare chip

Country Status (1)

Country Link
JP (1) JPH10135386A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1246243A2 (en) * 2001-03-29 2002-10-02 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
JP2003045912A (en) * 2001-08-02 2003-02-14 Matsushita Electric Ind Co Ltd Display panel and method for manufacturing display panel
EP1085570A3 (en) * 1999-09-13 2003-04-23 Vishay Intertechnology, Inc. Chip scale surface mount package for semiconductor device and process of fabricating the same
US6797544B2 (en) 2000-10-20 2004-09-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device, method of manufacturing the device and method of mounting the device
US7071577B2 (en) 2002-10-25 2006-07-04 Matshushita Electric Industrial Co., Ltd. Semiconductor device and resin binder for assembling semiconductor device
US7446423B2 (en) 2002-04-17 2008-11-04 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for assembling the same
US7589396B2 (en) 1999-09-13 2009-09-15 Vishay-Siliconix Chip scale surface mount package for semiconductor device and process of fabricating the same
US7981718B2 (en) 2008-02-22 2011-07-19 Sony Corporation Method of manufacturing solid-state image pickup element, and solid-state image pickup element
JP2014116602A (en) * 2012-12-11 2014-06-26 Samsung Electro-Mechanics Co Ltd Chip-embedded printed circuit board, semiconductor package using the same, and manufacturing method of chip-embedded printed circuit board

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1085570A3 (en) * 1999-09-13 2003-04-23 Vishay Intertechnology, Inc. Chip scale surface mount package for semiconductor device and process of fabricating the same
US7589396B2 (en) 1999-09-13 2009-09-15 Vishay-Siliconix Chip scale surface mount package for semiconductor device and process of fabricating the same
US6797544B2 (en) 2000-10-20 2004-09-28 Matsushita Electric Industrial Co., Ltd. Semiconductor device, method of manufacturing the device and method of mounting the device
KR100762208B1 (en) * 2000-10-20 2007-10-01 마쯔시다덴기산교 가부시키가이샤 Semiconductor device and its manufacturing method and mounting method of semiconductor device
EP1246243A2 (en) * 2001-03-29 2002-10-02 Kabushiki Kaisha Toshiba Semiconductor package and manufacturing method thereof
JP2003045912A (en) * 2001-08-02 2003-02-14 Matsushita Electric Ind Co Ltd Display panel and method for manufacturing display panel
US7446423B2 (en) 2002-04-17 2008-11-04 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for assembling the same
US7071577B2 (en) 2002-10-25 2006-07-04 Matshushita Electric Industrial Co., Ltd. Semiconductor device and resin binder for assembling semiconductor device
US7981718B2 (en) 2008-02-22 2011-07-19 Sony Corporation Method of manufacturing solid-state image pickup element, and solid-state image pickup element
JP2014116602A (en) * 2012-12-11 2014-06-26 Samsung Electro-Mechanics Co Ltd Chip-embedded printed circuit board, semiconductor package using the same, and manufacturing method of chip-embedded printed circuit board

Similar Documents

Publication Publication Date Title
JPH10135386A (en) Manufacturing methd of semiconductor bare chip
US6339875B1 (en) Method for removing heat from an integrated circuit
WO2005091363A1 (en) Heat sink board and manufacturing method thereof
KR940027146A (en) Semiconductor chip module
JP7067114B2 (en) Insulated circuit board and its manufacturing method
JP2004158739A (en) Resin sealed semiconductor device and manufacturing method therefor
JPS6159660B2 (en)
JPH08222670A (en) Package for mounting semiconductor element
JP3134860B2 (en) Hybrid integrated circuit device
JP3022738B2 (en) Multi-chip module
JPH0778903A (en) Method of bias voltage application in hybrid integrated circuit
JP2504465B2 (en) Semiconductor device
JPH0558569B2 (en)
JPH08264910A (en) Manufacture of printed wiring board with heat sink and method for mounting high-power component on the board
JP2619155B2 (en) Hybrid integrated circuit device
JP3263554B2 (en) Chip component and method of manufacturing the same
JPH05251602A (en) Manufacture of hybrid ic
JPS6184043A (en) Plug-in package
TW582102B (en) Package and manufacturing method thereof
JP2583507B2 (en) Semiconductor mounting circuit device
JPS61272956A (en) Hybrid type semiconductor device
JPH03276788A (en) Ceramic substrate for integrated circuit mounting use
JPH06291217A (en) Heat dissipation type lead frame
JPH06196614A (en) Lead frame
JPH05275570A (en) Semiconductor device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20040106