TW582102B - Package and manufacturing method thereof - Google Patents

Package and manufacturing method thereof Download PDF

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Publication number
TW582102B
TW582102B TW092108285A TW92108285A TW582102B TW 582102 B TW582102 B TW 582102B TW 092108285 A TW092108285 A TW 092108285A TW 92108285 A TW92108285 A TW 92108285A TW 582102 B TW582102 B TW 582102B
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TW
Taiwan
Prior art keywords
heat sink
wafer
metal heat
substrate
opening
Prior art date
Application number
TW092108285A
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Chinese (zh)
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TW200421575A (en
Inventor
Yu-Fang Tsai
Chin-Hsien Lin
Tsung-Yueh Tsai
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Advanced Semiconductor Eng
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Priority to TW092108285A priority Critical patent/TW582102B/en
Application granted granted Critical
Publication of TW582102B publication Critical patent/TW582102B/en
Publication of TW200421575A publication Critical patent/TW200421575A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A package and manufacturing method thereof is provided. In the method, at first, a substrate having an opening is provided. A membrane is adhered to the bottom surface of the substrate to cover the opening. A die and a metal heat slug, positioned under the die, are disposed on the membrane at the opening. A number of bond wires, leading from the top of the die to the top of the substrate, are formed to electrically connect the die and the substrate. An encapsulating mold compound is formed to cover the die, the bond wires and a part of the top surface of the substrate. The membrane is removed to expose the metal heat slug. A number of solder balls are formed on the exposed bond pads disposing on the bottom surface of the substrate.

Description

582102 五、發明說明（1) 【發明所屬之技術領域】 本發明是有關於一種封裝件及製造方法，且特別是有 關於一種固定晶片及金屬散熱片於基板之開口中且固定金 屬散熱片於晶片之底面上之封裝件及製造方法。 【先前技術】582102 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a package and a manufacturing method, and more particularly to a method for fixing a chip and a metal heat sink in an opening of a substrate and fixing the metal heat sink to Package on the bottom surface of a chip and manufacturing method. [Prior art]

由於電子產品越來越輕薄短小，使得用以保護半導體 晶片以及提供外部電路連接的封裝件也同樣需要趨向輕薄 短小之設計。當然’封裝件的散熱設計也是重要的一環。 請參照第1圖，其繪示乃傳統之具有散熱片之球格陣 列（heat slug ball grid array，HSBGA)封裝件的剖面 圖。在第1圖中，封裴件1〇()包括基板102、黏著劑1〇“及 1 0 4b、晶片1 06、數條銲線1 〇8、金屬散熱片i工〇、封膠 112、數個銲墊114及數個錫球116。藉由黏晶動作（die attach ing )’使得晶片1〇6經由黏著劑i〇4a固定於基板 102之正面上。再藉由打線動作（wire b〇nding )，使得 銲線1 0 8形成於晶片1 0 6的正面及晶片i 〇 6外之基板i 〇 4的正 面之間’以電性連接晶片i 〇 6及基板！ 〇 4。金屬散熱片π 〇As electronic products become thinner and thinner, packages that protect semiconductor chips and provide external circuit connections also need to be thinner and shorter. Of course, the heat dissipation design of the package is also an important part. Please refer to FIG. 1, which shows a cross-sectional view of a conventional heat slug ball grid array (HSBGA) package with a heat sink. In FIG. 1, the sealing member 10 () includes a substrate 102, an adhesive agent 10 "and 104b, a wafer 106, a plurality of bonding wires 10, a metal heat sink, a sealing member 112, A plurality of solder pads 114 and a plurality of solder balls 116. By die attaching, the wafer 106 is fixed on the front surface of the substrate 102 through the adhesive agent i04a. Then, the wire b 〇nding), so that the bonding wire 108 is formed between the front surface of the wafer 106 and the front surface of the substrate i 〇4 outside the wafer 〇6 to electrically connect the wafer 〇6 and the substrate! 〇4. Metal heat dissipation Slice π 〇

之兩下垂端係藉由黏著劑l〇4b固定於銲線1〇8外之基板102 的正面上，使得金屬散熱片11 〇之中間水平結構位於晶片 106之上方。此外’藉由灌膠動作（encapSUiaung)，使 得封膠11 2覆蓋部分之金屬散熱片11 〇、晶片j 〇 6、銲線1 〇 8 及部分之基板102的正面，並露出金屬散熱片11〇之中間水 平結構。另外，銲墊11 4係配置於基板1 〇 2之底面上，用以The two drooping ends are fixed on the front surface of the substrate 102 outside the bonding wire 108 by an adhesive 104b, so that the intermediate horizontal structure of the metal heat sink 110 is located above the wafer 106. In addition, the encapsulation action (encapSUiaung) causes the sealant 11 2 to cover a portion of the metal heat sink 11 〇, the wafer j 〇6, the bonding wire 108, and a part of the front surface of the substrate 102, and expose the metal heat sink 11 〇 Middle horizontal structure. In addition, the pads 11 4 are arranged on the bottom surface of the substrate 102 for

TW1029F(日月光）.ptd 第5頁 582102 五、發明說明（2) 經由基板102之内部線路與銲線丨10電性連接。藉由植球 (ball mounting)，使得錫球116形成於銲墊114上，封 裝件1 0 0將藉由錫球11 6與外圍電路電性連接。其中，封裝 件100的厚度為錫球116之底端與封膠U2之頂端之間的距 離。TW1029F (sun and moonlight) .ptd page 5 582102 V. Description of the invention (2) Electrical connection with the bonding wire 丨 10 through the internal circuit of the substrate 102. By ball mounting, the solder ball 116 is formed on the bonding pad 114, and the package 100 will be electrically connected to the peripheral circuit through the solder ball 116. The thickness of the package 100 is the distance between the bottom end of the solder ball 116 and the top end of the sealant U2.

▲封裝件1 0 0運作時’雖然晶片1 〇 6所產生的熱量可以 經由金屬散熱片110逸散至外界中。但由於基板導熱性 不佳，且其正面具有低導熱性的防銲層（s〇lder mask )，導致晶片1 〇6所產生之熱量不易散出，影響封裝 件1 0 0的運作甚鉅。此外，配置金屬散熱片i i 〇於晶片i 〇 6 之正面上方的設計，一方面會增加封裝件1〇〇的厚度；另 一方面，基於銲線108設置的考量，金屬散熱片11()之兩下 垂端必須固定於銲線丨〇8外之基板1〇2的正面上，將會增加 基板102之正面的面積。因此，整個封裝件丨〇〇的體積將會 變大，生產成本將增加許多。 【發明内容】 有鑑於此，本發明的目的就是在提供一種封裝件及製 造方法。其固定晶片及金屬散熱片於基板之開口中且固定 金屬散熱片於晶片之底面上的設計，一方面使得晶片所產 生之熱篁將經由晶片之底面上之高熱傳導性的金屬散熱片 逸散至外界中，可以省去基板之低熱傳導性之問題，並提 高封裝件之散熱效果。另一方面可以縮小封裝件的厚度， 並減少生產成本。▲ When the package 100 is in operation ', although the heat generated by the chip 106 can be dissipated to the outside via the metal heat sink 110. However, due to the poor thermal conductivity of the substrate and the solder mask on the front surface with a low thermal conductivity, the heat generated by the wafer 106 is not easily dissipated, which affects the operation of the package 100 greatly. In addition, the design of disposing the metal heat sink ii 〇 above the front side of the wafer i 〇 6 will increase the thickness of the package 100 on the one hand; on the other hand, based on the consideration of the bonding wire 108 setting, the metal heat sink 11 () The two drooping ends must be fixed on the front surface of the substrate 102 outside the bonding wire 08, which will increase the area of the front surface of the substrate 102. Therefore, the volume of the entire package will become larger, and the production cost will increase a lot. SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a package and a manufacturing method. The design of fixing the wafer and the metal heat sink in the opening of the substrate and fixing the metal heat sink on the bottom surface of the wafer, on the one hand, allows the heat generated by the wafer to be dissipated through the high thermal conductivity metal heat sink on the bottom surface of the wafer To the outside world, the problem of low thermal conductivity of the substrate can be eliminated, and the heat dissipation effect of the package can be improved. On the other hand, the thickness of the package can be reduced, and the production cost can be reduced.

582102 五、發明說明（3) 根據本發明的目的，提 屬散熱片、晶片、數條銲線 定於基板之開口中，金屬散 位於開口中，用以將晶片所 中’晶片及開口之口壁之間 使得晶片及金屬散熱片固定 晶片之正面及基板之正面之 板。封膠係覆蓋晶片、此些 些錫球係形成於基板之底面 根據本發明的再一目的 法。在此方法中，首先，提 接著，黏貼一薄膜於基板之 口端。然後，置放一晶片及 上’晶片係位於金屬散熱片 片之正面及基板之正面之間 後’形成一封膠以覆蓋晶片 面。然後’去除薄膜，以暴 個錫球於基板之底面之數個 為讓本發明之上述目的 懂，下文特舉一較佳實施例 明如下： 出一種封裝件，包括基板、金 、封膠及數個錫球。晶片係固 熱片係固定於晶片之底面上並 產生之熱量逸散至外界。其 的空隙係藉由一黏著劑填滿， 於開口中。此些銲線係形成於 間，用以電性連接晶片及基 銲線及部分之基板的正面，此 之數個銲墊上。 ’提出一種封裝件之製造方 供一基板，基板具有一開口。 底面上’薄膜係封住開口之下 一金屬散熱片於開口中之薄膜 上。接著，形成數條銲線於晶 以電性連接晶片及基板。然 、此些銲線及部分之基板的^ 露金屬散熱片。接著，形成數 銲塾上，封裝件終告完成。 、特徵、和優點能更明顯易 ，並配合所附圖式，作詳細說582102 V. Description of the invention (3) According to the purpose of the present invention, the heat sink, wafer, and several bonding wires are fixed in the opening of the substrate, and the metal is scattered in the opening, which is used to place the wafer and the opening in the wafer. Between the walls, the wafer and the metal heat sink fix the plate on the front side of the wafer and on the front side of the substrate. The sealing compound covers the wafer, and these solder balls are formed on the bottom surface of the substrate according to still another object method of the present invention. In this method, first, a thin film is pasted onto the mouth of the substrate. Then, a wafer and an upper wafer are placed between the front surface of the metal heat sink sheet and the front surface of the substrate to form an adhesive to cover the wafer surface. Then 'remove the film, and take a few solder balls on the bottom surface of the substrate to understand the above purpose of the present invention. A preferred embodiment is described below as follows: A package including a substrate, gold, sealant, and Several solder balls. Wafer system fixing The heat plate is fixed on the bottom surface of the wafer and the heat generated is released to the outside. The voids are filled with an adhesive in the openings. These bonding wires are formed in between for electrically connecting the wafer and the base bonding wires and a part of the front surface of the substrate, and these bonding pads. A method for manufacturing a package is provided. A substrate is provided, and the substrate has an opening. The film on the bottom surface seals a metal heat sink under the opening on the film in the opening. Next, a plurality of bonding wires are formed on the wafer to electrically connect the wafer and the substrate. However, these bonding wires and parts of the substrate have exposed metal heat sinks. Next, the solder joint is formed, and the package is finally completed. , Features, and advantages can be more obvious and easy, and in conjunction with the attached drawings, make a detailed description

【實施方式】[Embodiment]

TW1029F(日月光）.ptd 第7頁 582102 五 發明說明（4) 政熱片於基板之開口中且固定金屬散熱片於晶片之底 面上的設計， . I 一方面使得晶片所產生之熱量將經由晶片之 2面上之同熱傳導性的金屬散熱片逸散至外界中，可以省 基板之低熱傳導性之防銲層的隔絕，並提高封裝件之散 埶效要 ο Η 一 + 7 力一方面可以縮小封裝件的厚度，並減少生產成 〇 清參照第2 Α〜2Ε圖，其繪示乃依照本發明之較佳實施 例之1裝件之製造方法的流程剖面圖。首先，在第2A圖 中’提供一具有開口 203之基板202，並黏貼一薄膜205於 ，板20 2之底面上，薄膜2〇5係封住開口 2〇3的下口端及覆 蓋基板202之底面之數個銲墊214。薄膜2〇5係藉由黏著劑 貼於基板202之底面上，或者是薄膜205之上表面具有黏 性’直接可以和基板2〇2之底面及銲墊214相黏。此外，薄 膜205之頂面積只要稍微大於開口 2〇3之大小即可，也不需 要覆蓋到全部的銲墊2 1 4。 接著’置放一晶片206及一金屬散熱片210於開口203 中之薄膜210上，晶片206係位於金屬散熱片210上，且金 屬散熱片210係位於薄膜205上。例如，先固定金屬散熱片 210於晶片206之底面上，再將晶片206及金屬散熱片210以 金屬散熱片210之底面朝向薄膜205之方式置放於開口 203 中之薄膜205上；或者是，先置放金屬散熱片21〇於開口 203中之薄膜2 0 5上，再將晶片20 6以晶片206之底面朝向金 屬散熱片210之方式固定於開口 203中之金屬散熱片210 上，如第2B圖所示。在第2B圖中，金屬散熱片21〇係藉由TW1029F (Sun and Moonlight) .ptd Page 7 582102 Five invention descriptions (4) The design of the political heat plate in the opening of the substrate and the metal heat sink fixed on the bottom surface of the wafer. On the one hand, the heat generated by the wafer will pass through the wafer Metal heat sinks with the same thermal conductivity on both sides escape to the outside, which can save the isolation of the solder mask of the low thermal conductivity of the substrate, and improve the dispersion effect of the package. Η One + 7 force can The thickness of the package is reduced, and the production volume is reduced. Refer to Figures 2A to 2E, which are cross-sectional views showing the flow of the method for manufacturing a component according to a preferred embodiment of the present invention. First, in FIG. 2A, a substrate 202 having an opening 203 is provided, and a thin film 205 is adhered to the bottom surface of the plate 202. The thin film 20 seals the lower end of the opening 203 and covers the substrate 202. Number of solder pads 214 on the bottom surface. The thin film 205 is adhered to the bottom surface of the substrate 202 by an adhesive, or the upper surface of the thin film 205 is tacky, and can be directly adhered to the bottom surface of the substrate 202 and the bonding pad 214. In addition, the top area of the thin film 205 need only be slightly larger than the size of the opening 203, and it is not necessary to cover all the pads 2 1 4. Next, a wafer 206 and a metal heat sink 210 are placed on the film 210 in the opening 203. The wafer 206 is located on the metal heat sink 210, and the metal heat sink 210 is located on the film 205. For example, first fix the metal heat sink 210 on the bottom surface of the wafer 206, and then place the wafer 206 and the metal heat sink 210 on the film 205 in the opening 203 with the bottom surface of the metal heat sink 210 facing the film 205; or, First place the metal heat sink 21 on the film 2 05 in the opening 203, and then fix the wafer 20 6 on the metal heat sink 210 in the opening 203 with the bottom surface of the wafer 206 facing the metal heat sink 210, as described in the first section. Figure 2B. In FIG. 2B, the metal heat sink 21o is

TW1029F(日月光）.ptd 第8頁 582102 五、發明說明（5) 黏著劑204a固定於晶片2 0 6之底面上。由於晶片2 0 6之底面 積及金屬散熱片2 1 0之底面積皆小於開口 2 0 3之大小，使得 位於開口 2 0 3中之晶片2 0 6及金屬散熱片2 1 0和開口 2 0 3之口 壁之間具有空隙。此空隙係可以黏著劑2 0 4b填滿，使得晶 片2 0 6及金屬散熱片210可以藉由黏著劑204b固定於開口 20 3 中。 然後’依序進行打線動作（wire bonding )及灌膠動 作（encapsulating)，形成數條銲線20 8及封膠212，如 第2 C圖所示。在第2 C圖中，銲線2 0 8係形成於晶片2 0 6之正 面及基板2 0 2之正面之間，使得晶片2 0 6經由銲線2 0 8與基 板2 0 2電性連接。此外，封膠212係覆蓋晶片2 0 6、銲線208 及部分之基板202的正面。若晶片206及金屬散熱片210和 開口 2 0 3之口壁之間的空隙若不先以黏著劑2 〇4b填滿，則 此空隙會由封膠21 2填滿。 接著，去除薄膜205，以暴露銲墊214及金屬散熱片 210，使得金屬散熱片210直接暴露於外界空氣中，並作為 晶片206之散熱媒介，如第2D圖所示。在第2D圖中，當薄 膜2 0 5被去除後，晶片2 0 6及金屬散熱片2 1 0仍然可以藉由 黏著劑204b及封膠212固定於開口 2 0 3中。然後，進行植球 (ball mounting)，形成數個錫球216於銲墊214上，使 得封裝件20 0終告完成，如第2E圖所示。 ^封裝件2 0 0運作時，晶片2 〇 6所產生之熱量將經由晶 片206之底面上之高熱傳導性之金屬散熱片21〇直接逸散至 外界中，可以省去基板2 〇 2之低熱傳導性之防銲層的隔 TW1029F(日月光）.ptd 第9頁 582102 五、發明說明（6) 絕，使得封裝件2 0 0之散熱效果較傳統之封裝件1 Q 〇之散熱 效果更佳。另外，配置晶片20 6於開口 20 3中及配置金屬散 熱片210於晶片206之底面上的設計，在不增加晶片206之 厚度的狀況下，可以縮小封裝件2 〇 〇之厚度，並減少生產 成本。 然熟悉此技藝者亦可以明瞭本發明之技術並不侷限於 此，例如，金屬散熱片2 1 〇之材質為銀、銅或其他高熱傳 導性之物貝。其中，開口 2 〇 3係可以機械鑽孔、雷射鑽孔 或其他鑽孔方式完成。此外，金屬散熱片21〇的面積係可 大於晶片2 0 6的面積，以增加散熱效果。 本發明上述實施例所揭 定晶片及金屬散熱片於基板 晶片之底面上的設計，一方 由晶片之底面上之高熱傳導 中，可以省去基板之低熱傳 封裝件之散熱效果。另一方 減少生產成本。 露之封裝件及製造方法，其固 之開口中且固定金屬散熱片於 面使得晶片所產生之熱量將經 性的金屬散熱片逸散至外界 導性之防銲層的隔絕，並提高 面可以縮小封裝件的厚度，並TW1029F (sun and moonlight) .ptd page 8 582102 V. Description of the invention (5) The adhesive 204a is fixed on the bottom surface of the wafer 206. Since the bottom area of the chip 2 06 and the bottom area of the metal heat sink 21 1 are smaller than the size of the opening 2 0 3, the chip 2 0 6 and the metal heat sink 2 1 0 and the opening 2 0 located in the opening 2 03 There is a gap between the mouth walls of No. 3. This gap can be filled with the adhesive agent 20 4b, so that the wafer 2 06 and the metal heat sink 210 can be fixed in the opening 20 3 by the adhesive agent 204 b. Then, a wire bonding operation and an encapsulating operation are sequentially performed to form a plurality of bonding wires 20 8 and an encapsulation 212, as shown in FIG. 2C. In Fig. 2C, the bonding wire 2 0 8 is formed between the front surface of the wafer 2 06 and the front surface of the substrate 2 0 2, so that the wafer 2 6 is electrically connected to the substrate 2 0 2 through the bonding wire 2 0 8. . In addition, the sealant 212 covers the front surface of the wafer 206, the bonding wire 208, and a part of the substrate 202. If the gap between the chip 206 and the metal heat sink 210 and the mouth wall of the opening 203 is not filled with the adhesive 20b first, the gap will be filled with the sealant 21 2. Next, the film 205 is removed to expose the bonding pads 214 and the metal heat sink 210, so that the metal heat sink 210 is directly exposed to the outside air and serves as a heat dissipation medium for the chip 206, as shown in FIG. 2D. In FIG. 2D, after the thin film 205 is removed, the wafer 206 and the metal heat sink 2 10 can still be fixed in the opening 203 by the adhesive 204b and the sealant 212. Then, ball mounting is performed to form a plurality of solder balls 216 on the bonding pads 214, so that the package 200 is finally completed, as shown in FIG. 2E. ^ When the package 2000 is in operation, the heat generated by the chip 206 will be directly dissipated to the outside through the high thermal conductivity metal heat sink 21 on the bottom surface of the chip 206, which can save the substrate 002 as low as possible. TW1029F (sun moonlight) .ptd p. 9 582102 of the thermal conductive solder mask. V. INTRODUCTION (6) The heat dissipation effect of the package 2000 is better than that of the conventional package 1 Q 〇. In addition, the design of disposing the wafer 20 6 in the opening 20 3 and disposing the metal heat sink 210 on the bottom surface of the wafer 206 can reduce the thickness of the package 2000 and reduce production without increasing the thickness of the wafer 206. cost. However, those skilled in the art can also understand that the technology of the present invention is not limited to this. For example, the material of the metal heat sink 21 is silver, copper, or other highly thermally conductive materials. Among them, the opening 203 can be completed by mechanical drilling, laser drilling or other drilling methods. In addition, the area of the metal heat sink 21 may be larger than the area of the chip 206 to increase the heat dissipation effect. The design of the chip and the metal heat sink on the bottom surface of the substrate wafer disclosed in the above embodiments of the present invention can eliminate the heat dissipation effect of the substrate's low heat transfer package by high heat conduction on the bottom surface of the wafer. The other party reduces production costs. The exposed package and its manufacturing method have a fixed opening and a metal heat sink fixed on the surface so that the heat generated by the chip will dissipate the metallic heat sink to the external conductive solder mask and improve the surface. Reduce the thickness of the package, and

系；f；上所述，雖然本發明已以一 i —System; f; as described above, although the present invention has

然其並非用以限定本發明，任和> ^佳實施例揭露如上， 本發明之精神和範圍内，當可^热習此技藝者，在不脫離 本發明之保護範圍當視後附之 $種之更動與潤飾，因此 準。 甲請專利範圍所界定者為However, it is not intended to limit the present invention. Any and > preferred embodiments are disclosed above. Within the spirit and scope of the present invention, those skilled in the art can attach to it without departing from the scope of the present invention. $ Kind of change and retouch, so accurate. A Please define the scope of the patent as

582102 圖式簡單說明 第1圖繪示乃傳統之具有金屬散熱片之球格陣列封裝 件的剖面圖。 第2 A〜2 E圖繪示乃依照本發明之較佳實施例之封裝件 之製造方法的流程剖面圖。 圖式標號說明 1 0 0、2 0 0 :封裝件 1 0 2、2 0 2 :基板 104a 、 104b 、 204a 2 0 4b :黏著劑 106 108 110 112 114 116 203 205 206 208 210 212 214 216 開口 薄膜 晶片 銲線 金屬散熱片 封膠 鲜塾 錫球582102 Brief Description of Drawings Figure 1 shows a sectional view of a conventional ball grid array package with a metal heat sink. Figures 2A to 2E are cross-sectional views showing the flow of a method for manufacturing a package according to a preferred embodiment of the present invention. Description of figure numbers: 1 0 0, 2 0 0: package 1 0 2, 2 0 2: substrates 104a, 104b, 204a 2 0 4b: adhesive 106 108 110 112 114 116 203 205 206 208 210 212 214 216 opening film Chip bonding wire metal heat sink sealing glue fresh tin ball

TW1029F(曰月光）.ptd 第11頁TW1029F (Yueguang) .ptd Page 11

Claims (1)

582102 六、申請專利範圍 1. 一種封裝件之製造方法，至少包括： 提供一基板，該基板具有一開口； 黏貼一薄膜於該基板之底面上，該薄膜係封住該開口 之下口端； 置放一晶片及一金屬散熱片於該開口中之該薄膜上， 該晶片係位於該金屬散熱片上； 形成複數條銲線於該晶片之正面及該基板之正面之 間，以電性連接該晶片及該基板； 形成一封膠以覆蓋該晶片、該些銲線及部分之該基板 的正面；以及 去除該薄膜，以暴露該金屬散熱片。 2. 如申請專利範圍第1項所述之方法，其中該方法於 該置放一晶片及一金屬散熱片之步驟中更包括： 使用一黏著劑固定一金屬散熱片於一晶片之底面上； 以及 將該晶片及該金屬散熱片以該金屬散熱片之底面朝向 該薄膜之方式置放於該開口中之該薄膜上。 3. 如申請專利範圍第1項所述之方法，其中該方法於 該置放一晶片及一金屬散熱片之步驟中更包括： 置放一金屬散熱片於該開口中之該薄膜上；以及 將一晶片以該晶片之底面朝向該金屬散熱片之方式固 定於該開口中之該金屬散熱片上。 4. 如申請專利範圍第1項所述之方法，其中該方法於 該置放一晶片及一金屬散熱片之步驟與該形成複數條銲線582102 VI. Application for patent scope 1. A method for manufacturing a package, at least comprising: providing a substrate, the substrate having an opening; adhering a film on the bottom surface of the substrate, the film sealing the mouth end under the opening; A wafer and a metal heat sink are placed on the film in the opening, the wafer is located on the metal heat sink; a plurality of bonding wires are formed between the front side of the wafer and the front side of the substrate to electrically connect the A wafer and the substrate; forming an adhesive to cover the wafer, the bonding wires, and a portion of the front surface of the substrate; and removing the film to expose the metal heat sink. 2. The method as described in item 1 of the scope of patent application, wherein the method further comprises: placing a wafer and a metal heat sink on the bottom surface of a wafer using an adhesive; And the wafer and the metal heat sink are placed on the film in the opening with the bottom surface of the metal heat sink facing the film. 3. The method according to item 1 of the scope of patent application, wherein the method further comprises: placing a wafer and a metal heat sink on the film: placing a metal heat sink on the film in the opening; and A wafer is fixed on the metal heat sink in the opening with the bottom surface of the wafer facing the metal heat sink. 4. The method as described in item 1 of the scope of patent application, wherein the method includes a step of placing a wafer and a metal heat sink and forming a plurality of bonding wires. TW1029F(日月光）.ptd 第12頁 582102 六、申請專利範圍 之步驟之間更包括： 使用一黏著劑填滿該晶片及該金屬散熱片和該開口之 口壁之間的空隙。 5. 如申請專利範圍第1項所述之方法，其中該方法於 該形成一封膠之步驟中更包括： 形成一封膠以覆蓋該晶片、該些銲線及部分之該基板 的正面，並填滿該晶片及該金屬散熱片和該開口之口壁之 間的空隙。 6. 如申請專利範圍第1項所述之方法，其中該薄膜之 頂面積係大於該開口之大小，且該薄膜係覆蓋該基板之底 面的複數個銲墊。 7. 如申請專利範圍第6項所述之方法，其中該方法於 該去除該薄膜之步驟後又包括： 形成複數個錫球於該些銲墊上。 8. 如申請專利範圍第1項所述之方法，其中該金屬散 熱片之材質為銅。 9. 一種封裝件，至少包括： 一基板，具有一開口； 一晶片，係固定於該開口中；以及 一金屬散熱片，係固定於該晶片之底面上並位於該開 口中，用以將該晶片所產生之熱量逸散至外界中。 10. 如申請專利範圍第9項所述之封裝件，其中該封 裝件更包括： 複數條銲線，係形成於該晶片之正面及該基板之正面TW1029F (Sun Moonlight) .ptd Page 12 582102 6. The scope of the patent application step further includes: using an adhesive to fill the gap between the chip and the metal heat sink and the wall of the opening. 5. The method according to item 1 of the scope of patent application, wherein the method further comprises: forming an adhesive to cover the wafer, the bonding wires and a part of the front surface of the substrate, And fill the gap between the chip and the metal heat sink and the opening wall of the opening. 6. The method according to item 1 of the scope of patent application, wherein the top area of the film is larger than the size of the opening, and the film is a plurality of pads covering the bottom surface of the substrate. 7. The method according to item 6 of the patent application scope, wherein after the step of removing the film, the method further comprises: forming a plurality of solder balls on the pads. 8. The method according to item 1 of the scope of patent application, wherein the material of the metal heat sink is copper. 9. A package comprising at least: a substrate having an opening; a wafer fixed in the opening; and a metal heat sink fixed on a bottom surface of the wafer and located in the opening, for The heat generated by the chip is dissipated to the outside world. 10. The package according to item 9 of the scope of patent application, wherein the package further includes: a plurality of bonding wires formed on the front surface of the wafer and the front surface of the substrate TW1029F(日月光）.ptd 第13頁 582102 六、申請專利範圍 之間，用以電性連接該晶片及該基板； 一封膠，係覆蓋該晶片、該些銲線及部分之該基板的 正面；以及 複數個錫球，係形成於該基板之底面之複數個銲墊 上。 11. 如申請專利範圍第9項所述之封裝件，其中該金 屬散熱片係藉由一黏著劑固定於該晶片之底面上。 12. 如申請專利範圍第9項所述之封裝件，其中該晶 片及該金屬散熱片和該開口之口壁之間的空隙係以一黏著 劑填滿，使得該晶片及該金屬散熱片固定於該開口中。 13. 如申請專利範圍第9項所述之封裝件，其中該金 屬散熱片之材質為銅。TW1029F (Sun Moonlight) .ptd Page 13 582102 6. Between the scope of the patent application, it is used to electrically connect the chip and the substrate; a glue covering the front of the chip, the bonding wires and parts of the substrate; And a plurality of solder balls are formed on a plurality of pads on the bottom surface of the substrate. 11. The package according to item 9 of the scope of patent application, wherein the metal heat sink is fixed on the bottom surface of the chip by an adhesive. 12. The package according to item 9 of the scope of the patent application, wherein the gap between the chip and the metal heat sink and the opening wall is filled with an adhesive, so that the chip and the metal heat sink are fixed. In the opening. 13. The package according to item 9 of the scope of patent application, wherein the material of the metal heat sink is copper. TW1029F(日月光）.ptd 第14頁TW1029F (Sun and Moonlight) .ptd Page 14
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