JPH0955917A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display the wide video signal of a PAL system in a state horiozntally and vertically balanced on the display panel of a standard screen for an NTSC-system. SOLUTION: A video input terminal 10 inputting the video signal of the PAL system, a wide detection circuit 12 detecting whether the video signal from the input terminal 10 is a wide video signal whose aspect ratio is 9:16 or not, an RGB decoder 11 separating primary color signals and a synchronizing signal from the video signals from the input terminal 10, the liquid crystal display panel 15 of the NTSC system, which has the standard display screen whose aspect ratio is 3: 4 and a controller 13 controlling a signal-side driver 16 and a scanning-side driver 17 so that the primary color signals are thinned about 1/3 so as to display them on the liquid crystal panel 15 in a scanning line unit from the display time of a standard video signal based on the synchronizing signal obtained by the RGB decoder 11 in the case of detecting the input of the wide video signal by the wide detection circuit 12 are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dot matrix type display panel such as a liquid crystal display panel for displaying a video signal having a television system and an aspect ratio different from that of the display panel.

[0002]

2. Description of the Related Art Conventionally, the NTSC system has been adopted as a television system in Japan and the United States, but the PAL system has been adopted in many countries in Europe and Oceania. However, in the case of a liquid crystal display panel that displays a standard screen with an aspect ratio of 3: 4 in the NTSC system and a display device that displays a video signal in the PAL system with the same aspect ratio, the number of scanning lines is 262.5 in the NTSC system / Field, P
312.5 lines / field in the AL system, of which the number of effective scanning lines for image display is 241.5 in the NTSC system.
Since there are more lines / field and the PAL system with 287.5 lines / field, the PAL system usually has thinned and displayed 1/6 or 1/7 of the video signal as an approximate value.

[0003]

A case will be considered in which a wide video signal having an aspect ratio of 9:16 according to the PAL system is displayed on the above display device. As shown in FIG. 5A, the PAL wide video signal has the same P
The number of scanning lines is 312.5 like the standard video signal of AL system.
Lines / field, the number of effective scanning lines is 287.5 lines / field, and as shown in FIG. 5 (2), 1H (the time from the beginning of one scanning line to the beginning of the next scanning line) ) Display data of 4/3 (= 16/12) times is compressed and included in the period.

Therefore, if the PAL wide video signal is displayed as it is on the display device, a horizontal compressed video signal is displayed as shown in FIG. 6, and the vertical and horizontal balance is lost. Specifically, a vertically long image is unnaturally displayed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to convert a wide video signal with an aspect ratio of 9:16 according to the PAL system into a standard with an aspect ratio of 3: 4 for the NTSC system. An object of the present invention is to provide a display device capable of displaying in a vertically and horizontally balanced state on a dot matrix type display panel having a screen.

[0006]

Means for Solving the Problems That is, the present invention is as follows: (1) When a wide video signal having an aspect ratio of 9:16 is input according to the PAL system, this video signal is displayed in units of scanning lines from the display of the standard video signal to approximately 3 is thinned out and displayed on an NTSC type dot matrix type display panel having a standard display screen with an aspect ratio of 3: 4.

(2) Input means for inputting a PAL video signal, detection means for detecting a video signal input by the input means when the video signal is a wide video signal having an aspect ratio of 9:16, and NTS having a decoding means for separating a primary color signal and a synchronizing signal from a video signal input from the input means, and a standard display screen having an aspect ratio of 3: 4
C type dot matrix type display panel and display of standard video signal in scanning line units of the primary color signals based on the synchronizing signal obtained by the decoding means when the input of the wide video signal is detected by the detecting means. Display control means for thinning out approximately 1/3 from the time and displaying on the display panel is provided.

In either of the configurations of (1) and (2) above, the NTS is used to convert a wide video signal having an aspect ratio of 9:16 by the PAL system without using a complicated signal processing circuit.
It is possible to display in a vertically and horizontally balanced state on a dot matrix type display panel having a standard screen with an aspect ratio of 3: 4 for the C system.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which the present invention is applied to a display driving device for a liquid crystal panel will be described below with reference to the drawings. FIG. 1 exemplifies the circuit configuration, and a PAL-system composite video signal input from a video input terminal 10 is sent to an RGB decoder 11 and a wide detection circuit 12.

The RGB decoder 11 receives the input PAL
By performing processing such as sync separation detection and chroma processing on the composite video signal of the system, R, G, B primary color signals and a sync signal composed of a horizontal sync signal H and a vertical sync signal V are decoded and output. , And outputs the obtained synchronization signals H, V to the controller 13 and the primary color signals R, G, B to the inverting amplifier 14, respectively.

The wide detection circuit 12 receives the input P
By detecting the presence or absence of the identification signal superimposed on the specific scanning line position in the AL type composite video signal,
The PAL system composite video signal is a wide video signal for determining whether it is a wide video signal with an aspect ratio of 9:16 or a standard video signal with an aspect ratio of 3: 4. When the identification signal is detected, the thinning mode signal is sent to the controller 13.

The controller 13, whose detailed structure will be described later, is a display target based on the synchronization signals H and V sent from the RGB decoder 11 and the thinning-out mode signal sent from the wide detection circuit 12. An NTSC type liquid crystal display panel (LCD) 15 having a standard display screen with an aspect ratio of 3: 4 is provided with a horizontal control signal for a signal side driver 16 for driving a signal electrode and a vertical direction for a scanning side driver 17 for driving the same scanning electrode. The control signal and the inverted signal FRP are output to the inverting amplifier 14 and the amplifier 18, respectively.

The inversion amplifier 14 appropriately inverts the polarities of the primary color signals R, G, B received from the RGB decoder 11 in scanning line units and field units in accordance with the inversion signal FRP from the controller 13, and then the signal side driver. Serve to 16.

The amplifier 18 generates a voltage VCOM whose polarity is appropriately inverted in scanning line units and field units in response to an inversion signal FRP from the controller 13 and supplies it to the scanning electrodes of the liquid crystal display panel 15.

The scanning side driver 17 sequentially scans and drives the scanning electrodes of the liquid crystal display panel 15 by a vertical control pulse,
The signal side driver 16 drives the signal electrodes of the liquid crystal display panel 15 by gradation in accordance with the inversion primary color signals R, G, B from the inversion amplifier 14 in accordance with the scanning electrode voltage VCOM.
Images are displayed on the liquid crystal display panel 15.

As described above, the liquid crystal display panel 15, the signal side driver 16 for driving the signal electrodes of the liquid crystal display panel 15 and the scanning side driver 17 for driving the scanning electrodes are N.
Video input terminal 10 for TSC system
The video signal input from is a PAL system. Therefore, the controller 13 absorbs the difference due to these methods, including the difference in the number of scanning lines, and displays the liquid crystal in accordance with the input wide image signal with the aspect ratio of 9:16 and the standard image signal with the same aspect ratio of 3: 4. A display control operation such as timing is performed to display an image on the panel 15.

FIG. 2 exemplifies a detailed circuit configuration of the controller 13. The horizontal synchronizing signal H from the RGB decoder 11 is fed to the PLL circuit 21, the vertical synchronizing signal V is fed to the synchronizing control circuit 22, and the wide detecting circuit is provided. The thinning-out mode signal from 12 is input to the thinning-out control circuit 23 and the thinning-out decoder 24, respectively.

The PLL circuit 21 is a VC as an oscillation circuit.
It forms a loop with O25 and outputs a signal corresponding to the phase difference between the scanning pulse PH sent from the horizontal decoder 26 and the horizontal synchronizing signal H to the VCO 25. VCO25
Generates a basic clock (CK) in the controller 13 based on the signal voltage from the PLL circuit 21, and the horizontal counter 27 and the dot clock generation circuit 28.
Send to.

The horizontal decoder 26 uses the start signal SRT, the output enable signal OE, and the clear signal CL based on the count value of the horizontal counter 27 that counts the dot positions of the input video signal within one horizontal scanning period.
The Rs are collectively sent as a horizontal control signal directly to the signal side driver 16, while the gate output enable signal GOE is output.
And a gate pulse clock GPCK as a vertical control signal to the thinning-out control circuit 23, and an internal horizontal synchronizing signal (internal H) as a scanning line clock as a vertical counter 29, a thinning-out counter 30, an FRP generating circuit 31, and a reset signal. It outputs to each horizontal counter 27.

The dot clock generation circuit 28 has a VC
The dot clock DCK is generated by appropriately dividing the basic clock sent from O25, and is directly sent to the signal side driver 16 as a part of the horizontal control signal.

The sync control circuit 22 generates an internal vertical sync signal (internal V) according to the vertical sync signal V separated from the video signal input from the RGB decoder 11 and the control signal from the vertical decoder 32. As a reset signal, the vertical counter 29 and the thinning counter 30
To the FRP generation circuit 31.

The vertical decoder 32 is the horizontal decoder 2
On the basis of the count value of the vertical counter 29 which counts the scanning line position in one field in the video signal by the internal horizontal synchronizing signal outputted from the control signal 6, the control signal is sent to the synchronizing control circuit 22 while the gate start signal GSRT is outputted.
Is directly sent to the scanning side driver 17 as a part of the vertical control signal.

The thinning-out decoder 24, based on the count value of the thinning-out counter 30 which counts the scanning line position in one field in the video signal by the internal horizontal synchronizing signal output from the horizontal decoder 26 like the vertical counter 29, based on the count value. In response to the thinning-out mode signal input from the wide detection circuit 12, a thinning-out control signal indicating the timing of the scanning line position to be thinned out is sent to the thinning-out control circuit 23 and the FRP generation circuit 31.

The FRP generation circuit 31 includes a horizontal decoder 26.
In order to invert the polarity of the voltage applied to the electrodes in the scanning line unit and the field unit of the liquid crystal display panel 15 by the internal horizontal synchronization signal from the LCD, the thinning control signal from the thinning decoder 24 and the internal vertical synchronization signal from the synchronization control circuit 22. The inverted signal FRP is generated and output to the inverting amplifier 14 and the amplifier 18 as described above.

The thinning control circuit 23 is provided with a gate output enable signal GOE as a vertical control signal sent from the horizontal decoder 26 and a gate pulse clock GPC.
The output of K to the scanning side driver 17 is supplied to the thinning control signal from the thinning decoder 24 and the wide detection circuit 12 described above.
The stop control is appropriately performed by the thinning mode signal from

In the circuit configuration as described above, when a composite video signal based on a standard video with an aspect ratio of 3: 4 of the PAL system is input to the video input terminal 10 and a wide video with the same aspect ratio of 9:16. The operation when a composite video signal of a signal is input will be described.

First, a case will be described in which a composite video signal based on a standard video with an aspect ratio of 3: 4 of the PAL system is input. When the composite video signal of the standard video is input from the video input terminal 10, the identification signal for the wide video is not superimposed on the specific scanning line position in the composite video signal, and the wide detection circuit 12 performs the identification. Since the code cannot be detected, the thinning mode signal is not sent to the controller 13.

The RGB decoder 11 has a video input terminal 10
The primary color signals of R, G, B and the synchronization signal composed of the horizontal synchronization signal H and the vertical synchronization signal V are separated from the composite video signal input from, and each synchronization signal H, V is sent to the controller 13 and the primary color signals R, G and B are output to the inverting amplifier 14, respectively.

The controller 13 mainly absorbs the difference in the number of scanning lines between the PAL system which is the television system of the input video signal and the NTSC system which is the television system of the liquid crystal display panel 15 and its drivers 16 and 17. In addition, the horizontal control signal and the vertical control signal are sent to the signal side driver 16 and the scanning side driver 17 in consideration of the number of signal electrodes and the number of scanning electrodes of the liquid crystal display panel 15.

For example, it is assumed that the liquid crystal display panel 15 has 320 signal electrodes and 240 scanning electrodes. PAL
The number of scanning lines of the standard video signal of the system is 312.5 lines / field, the number of scanning lines of the NTSC system is 262.5 lines / field, and the effective number of scanning lines for image display is 287. 5 lines / field, 241.5 lines / field in the NTSC system, which is almost the same number as the number of scanning electrodes of the liquid crystal display panel 15;
If 87.5 is approximated to be 5/6, that is, if one scanning line is thinned out to six scanning lines of the input video signal, PA
Standard image of L system is displayed on the liquid crystal display panel 15 of NTSC system.
Can be displayed with.

Accordingly, in the controller 13, the thinning-out decoder 24 counts the scanning line position in one field in the video signal by the internal horizontal synchronizing signal output from the horizontal decoder 26, based on the count value of the thinning-out counter 30. Corresponding to the absence of the thinning-out mode signal from the wide detection circuit 12, the thinning-out control circuit 23 outputs the thinning-out control signal at a timing such that one out of every six effective scanning lines becomes the “H” level. And to the FRP generation circuit 31.

On the other hand, the thinning-out control circuit 23 outputs the gate output enable signal GOE and the gate pulse clock GPCK as the vertical control signals sent from the horizontal decoder 26 to the scanning side driver 17, to the thinning-out decoder 24. Due to the thinning control signal from No. and the thinning mode signal not input from the wide detection circuit 12, the stop control is appropriately performed so as to drive 240 scanning lines in one field.

Next, a case will be described in which a composite video signal of a wide video having a PAL aspect ratio of 9:16 is input. When the composite video signal of the wide video is input from the video input terminal 10, the identification signal for the wide video is superimposed on the specific scanning line position in the composite video signal, and therefore the wide detection circuit 12 performs the identification. The code is detected and a thinning mode signal is sent to the controller 13.

The RGB decoder 11 has a video input terminal 10
The primary color signals of R, G, B and the synchronization signal composed of the horizontal synchronization signal H and the vertical synchronization signal V are separated from the composite video signal input from, and each synchronization signal H, V is sent to the controller 13 and the primary color signals R, G and B are output to the inverting amplifier 14, respectively.

The controller 13 mainly absorbs the difference in the number of scanning lines between the PAL system which is a television system of the input video signal and the NTSC system which is a television system of the liquid crystal display panel 15 and its drivers 16 and 17. , And that the input PAL composite video signal is a wide video whose signal amount is temporally compressed within one scanning period, and the liquid crystal display panel 15
The horizontal control signal and the vertical control signal are sent to the signal side driver 16 and the scanning side driver 17 in consideration of the number of signal electrodes and the number of scanning electrodes.

That is, the wide video signal of the PAL system has the same number of scanning lines as the standard video signal of 312.5 lines / field, and the effective number of scanning lines of them is also 287.5 lines / field. In order to display the image on a screen with an aspect ratio of 3: 4 without breaking the balance, at least one of the upper end portion and the lower end portion of the screen as shown in FIG.
3/12) is masked with the same color, for example black, and the remaining 3
/ 4 (= 9/12) will be used. FIG. 3 exemplifies a case in which both the upper end portion and the lower end portion of the screen are masked and the central portion of the screen is used for display.

Here, considering the thinning ratio of the video signal,
Since the approximate value for the standard image is 5/6, and the number of scanning lines used on the screen is reduced to 3/4 for wide image display, “(5/6) × (3/4) = 5 / 8 ”, which is further approximated to 1/3 for simplification of the signal processing system.
And That is, one in three scanning lines of the input video signal
If you decimate by the ratio of books, PAL wide video will be recorded by NTS.
It can be displayed on the standard C type liquid crystal display panel 15.

Therefore, in the controller 13, the thinning-out decoder 24 counts the scanning line position in one field in the video signal by the internal horizontal synchronizing signal output from the horizontal decoder 26, based on the count value of the thinning-out counter 30. Corresponding to the input of the thinning-out mode signal from the wide detection circuit 12, in the PAL wide video signal shown in FIG. 4 (1), one out of every three effective scanning lines “◯” and “x” is shown. The thinning-out control signal is supplied to the thinning-out control circuit 23 and FR at a timing such that the ratio becomes "H" level.
It is sent to the P generation circuit 31.

On the other hand, the thinning control circuit 23 has the gate output enable signal GOE shown in FIG. 4C as the vertical control signal sent from the horizontal decoder 26 and the gate pulse clock GPCK shown in FIG. 4B. The output to the scanning-side driver 17 is 180 in one field as a result of the thinning control signal from the thinning decoder 24 and the thinning mode signal from the wide detection circuit 12.
(= 240 × (3/4)) scanning lines are appropriately stopped and controlled so as to be driven.

In this case, as described above, the number of effective scanning lines in the PAL wide video signal is 287.5 lines / field, and since this is used for displaying only about 2/3, "287.5" is used. × (2/3) = 191.7 ”, and since the number of scanning lines of the liquid crystal display panel 15 actually used for display is 180,“ 180 / 191.7 = 9 ”
3.9 (%) ", the horizontal signal amount of each scanning line used for display is set to about 94%, and the horizontal decoder 26 is arranged so that about 6% of the image, including the left and right ends, is not used for display. By designing the peripheral circuit including the horizontal counter 27 and the dot clock generation circuit 28, it is possible to display a balanced wide image in vertical and horizontal directions with almost no flatness.

In the above embodiment, the case where the liquid crystal display panel 15 is used as a display target has been described, but the present invention is not limited to this, and a plasma display or the like can be used.
It goes without saying that other dot matrix type display panels can be applied.

[0042]

As described above, according to the present invention, the PA
A display device capable of displaying a wide video signal with an aspect ratio of 9:16 according to the L system on a dot matrix type display panel having a standard screen with an aspect ratio of 3: 4 for the NTSC system in a vertically and horizontally balanced state. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed circuit configuration in the controller of FIG.

FIG. 3 is a diagram for explaining an operation according to the same embodiment.

FIG. 4 is a waveform diagram for explaining an operation according to the same embodiment.

FIG. 5 is a diagram illustrating a PAL wide video signal.

FIG. 6 is a diagram exemplifying screen configurations of wide video and standard video.

[Explanation of symbols]

 10 ... Video input terminal 11 ... RGB decoder 12 ... Wide detection circuit 13 ... Controller 14 ... Inversion amplifier 15 ... Liquid crystal display panel 16 ... Signal side driver 17 ... Scanning side driver 18 ... Amplifier 21 ... PLL circuit 22 ... Synchronization control circuit 23 ... Thinning control circuit 24 ... Thinning decoder 25 ... VCO 26 ... Horizontal decoder 27 ... Horizontal counter 28 ... Dot clock generating circuit 29 ... Vertical counter 30 ... Thinning counter 31 ... FRP generating circuit 32 ... Vertical decoder

Claims (2)

[Claims] 1. An aspect ratio of 9:16 according to the PAL method.
When a wide video signal is input, this video signal is thinned out by approximately 1/3 from the standard video signal display in scanning line units and displayed on an NTSC dot matrix type display panel having a standard display screen with an aspect ratio of 3: 4. A display device characterized by: 2. An input means for inputting a PAL video signal, and a video signal input by this input means has an aspect ratio of 9:
A detection means for detecting 16 wide video signals, a decoding means for separating the primary color signal and the sync signal from the video signal input from the input means, and a standard display screen with an aspect ratio of 3: 4 are provided. An NTSC type dot matrix type display panel and a primary video signal of a standard video signal for each scanning line based on a synchronization signal obtained by the decoding means when an input of a wide video signal is detected by the detection means. A display device, comprising: display control means for thinning out approximately 1/3 from a display time to display on the display panel.