JP2733664B2 - Matrix display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] Regarding a matrix display device such as a liquid crystal display, for the purpose of shaping the waveform of a synchronization signal and enabling normal display even during special playback of a video, the edge of a pulse is detected. An edge detection unit, a pulse addition unit that generates a pulse when the next pulse is not input even after a predetermined time has elapsed from the edge detection by the edge detection unit, and a predetermined time from the edge detection by the edge detection unit A synchronous signal correction unit comprising: a noise removal unit that removes a next pulse when a next pulse is input before the time elapses; and a pulse width correction unit that corrects a pulse other than a predetermined pulse width to a predetermined pulse width. It is configured to provide a circuit.

[Industrial applications]

The present invention relates to a matrix display device such as a liquid crystal display, and more particularly, to a matrix display device including a synchronization signal correction circuit.

[Conventional technology]

Liquid crystal element, EL (electroluminescent), PDP (plasma d
Matrix display devices based on isplay, etc., are being put to practical use in word processors and the like because of their advantages of being thinner and lighter than CRTs. In particular, various pocket TVs have been commercialized for liquid crystal displays. Although pocket televisions were initially accepted simply as reception-only, it is clear that, as with ordinary televisions, they need to be equipped with the capability to handle video equipment.

On the other hand, in a matrix display device, a method is generally used in which a selection pulse is shifted line by line by a horizontal synchronizing signal and each row is written. That is, as shown in FIG.
When the matrix display panel 81 is scanned from the upper side to the lower side in the figure, the scanning waveform for each row is written with a shift of one pulse cycle (63.5 μs) of the horizontal synchronization signal. Also, as shown in FIG. 8 (b), no DC voltage is applied to the display element.
The AC voltage is inverted by inverting the data voltage every time the vertical synchronization signal is input.

[Problems to be solved by the invention]

Currently, VTR devices used for consumer use can perform still images and fast-forwarding in addition to normal playback, but during these special playbacks, the output waveform is disturbed, and the sync signal has noise or chipping .

FIG. 9 is a sample diagram showing each example of such a disturbance of the synchronization signal. FIG. 7A shows a waveform of normal reproduction, wherein the upper part in the figure is a comb-shaped composite synchronizing signal and the lower part in the figure is a square vertical synchronizing signal, both of which are negative pulses. FIG. 9B shows an example in which the composite synchronization signal is disturbed, and includes a portion 9a having a broken waveform, a missing portion 9b, and two portions 9c. FIG. 9C shows an example of a case where the vertical synchronizing signal is disturbed, and a waveform which normally needs to be performed once appears twice. For example, when the composite synchronizing signal is lacking, the driving is stopped, and when the number is two, the driving is excessive. For this reason, the vertical scanning is not performed normally, and a DC voltage is applied to the display element, which causes a deterioration in life. In the case of a CRT display device, vertical scanning is performed by a vertical synchronization signal and is independent of the horizontal synchronization signal, so that it only has a partial or instantaneous effect on the screen, but in a matrix display device, it has an overall effect. . Further, in the liquid crystal, it is necessary to perform the AC driving, and there is a possibility that the display becomes impossible when a DC voltage is applied.

The present invention has been made in view of such a problem, and an object of the present invention is to provide a matrix-type display device that performs waveform shaping of a synchronization signal and can perform normal display even during special video playback.

[Means for solving the problem]

In the present invention, means for solving the above-mentioned problem is provided in a matrix display device controlled in a matrix by a horizontal synchronizing signal and a vertical synchronizing signal as shown in FIG. An edge detection unit that detects an edge of a pulse, a pulse addition unit that generates a pulse when a next pulse is not input even after a predetermined time has elapsed from the edge detection by the edge detection unit, and an edge that is generated by the edge detection unit. A noise removing unit that removes the next pulse when a next pulse is input before a predetermined time has elapsed from the detection, and a pulse width correction unit that corrects a pulse other than the predetermined pulse width to a predetermined pulse width. Is provided.

[Action]

As shown in FIG. 2, the TV signal has a period, a pulse width, and an allowable error range of the synchronization signal determined by the NTSC standard. Frequency of the horizontal period signal (f _H) is 15.734
26KHz (~1 / 63.5μs), a vertical synchronizing signal frequency (f _V)
Is 59.94 Hz (up to 1 / 16.6 ms). In other cases, the input synchronization signal is corrected.

Horizontal sync and vertical sync are only frequency differences, so
The following describes only the horizontal synchronization signal.

FIG. 3 is a waveform chart showing the principle of the present invention. Since the period of the horizontal synchronizing signal is about 63.5 μs, as shown in FIG. 5A, when the interval from one synchronization pulse to the next synchronization pulse is 63.5 μs or less (actually 60 to 63.5 μs or less). Removes the second pulse, as shown in FIG.
On the other hand, if the next sync pulse is not input within 63.5 μs or more after the input of a certain sync pulse as shown in FIG. 3C, the sync pulse is artificially inserted as shown in FIG. I do.

In the above processing, normal display is performed by removing noise on the synchronization pulse and correcting missing pulses.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the embodiment will also be described using a horizontal synchronization signal as an example.

FIG. 1 is a basic block diagram showing a synchronous signal correction circuit according to an embodiment of the present invention. In FIG. 1, a synchronization signal correction circuit includes an edge detection unit 1 that detects an edge at which a pulse rises, and a pulse that generates a pulse when the next pulse is not detected even after a predetermined time has elapsed from the detected edge. An adding unit 2, a noise removing unit 3 for masking the next pulse when a predetermined pulse is detected before a predetermined time has elapsed from the detected edge, and a pulse width for outputting only a pulse of a predetermined width And a correction unit 4.

The edge detection unit 1 performs the operation when no pulse is input (always
(5V or 0V) The input of the next stage is provided so as to be "H" to prevent the vertical synchronization signal from being mixed.

The pulse adding section 2 at the next stage is basically an oscillator that oscillates at a slightly lower frequency than the horizontal synchronization frequency, and has a built-in multivibrator 2a that can be retriggered at predetermined time constants. FIG. 4 is a waveform diagram showing an example of the operation, and FIG. 4A shows the input signal S1 of FIG. 1, in which a part of the synchronization signal set at a period of 63.5 μs is missing. In such a case, if the first pulse is used as a trigger and the trigger is retriggered every 64 μs as in the signal S2 shown in FIG. Is not input, the output Q falls by the multivibrator 2a and a pulse is added, as shown by a signal S3 in FIG. This waveform is fed back to the input of the NAND gate 2b again, and when a pulse is continuously missing, the operation is repeated by using its own output Q as a trigger and oscillates. 6
If pulses having a period of 3.5 μs are sequentially input, Q always becomes “H”, and the output signal S4 of FIG. 1 shown in FIG.
Is the inverse of the input.

The noise elimination unit 3 performs the operation after the first pulse is input.
The pulse input within μs is masked, and the next pulse after 63 μs is passed. FIG. 5 is a waveform diagram showing an example of the operation of the NAND gate 2b of the pulse adding unit 2 in FIG.
If the signal S4 output from the device includes noise as shown in FIG. 5 (a), the noise is 63 μs
As shown in FIG. 5B, the signal S6 outputted from the NAND gate 3b is noise-removed as shown in FIG. 5B, since the signal S6 is masked by the mask signal S5 outputted from the multivibrator 3a. Will be done.

In the above circuit, the period is corrected by extracting the edge of the synchronization pulse.
The pulse of 6 μs is passed as it is, and the pulse of 4 μs or less is expanded to 4 μs, and the pulse of 6 μs or more is reduced to 6 μs.

6A and 6B are sample diagrams of the waveform processing according to the present invention. FIG. 6A shows a case where the input is normal, FIG. 6B shows a case where the input pulse is missing, and FIG. This shows a case where noise is mixed. In the case of FIG. 5A, the input is output as it is, in the case of FIG. 5B, a pulse is added, and in the case of FIG. In addition, it is possible to stabilize scanning and drive the liquid crystal by alternating current, and obtain a good display. Further, the above circuit has an advantage that a malfunction can be prevented since a synchronization signal is generated even when there is no signal.

FIG. 7 shows a TFT (thin fi) using the correction circuit of the present invention.
FIG. 2 is a configuration diagram illustrating an example of a liquid crystal display device driven by an lm transistor. As shown in the figure, the composite video signal is separated into a luminance signal and a composite synchronization signal (CSYNC) by a synchronization separation circuit 71, and the composite synchronization signal is separated from a horizontal synchronization signal (HSYNC) and a vertical synchronization signal by a horizontal / vertical separation circuit 72. It is separated into a synchronization signal (VSYNC). Each of the synchronization signals is shaped by the correction circuit (A and B) 73 of the present invention, and then input to the control circuit 74 to synchronize the control signals of the data driver 75a and the scanning driver 75b. Note that the horizontal synchronizing signal is also used as a clock of the scanning driver 75b, and the vertical synchronizing signal is also used for switching the inversion data and the non-inversion data of the video signal.

In a display device not using the present invention, the horizontal and vertical scanning signals are kept separated by the horizontal / vertical separation circuit 72, and the horizontal and vertical scanning timing signals are generated by the control circuit 74. In order to apply a positive-negative symmetric voltage to the panel 76, the polarity of the data voltage is inverted for each field for driving, and the polarity is inverted by a vertical synchronization signal.
Since the positive / negative data voltage is switched by the analog switch 78 etc. according to the signal by toggling the type flip-flop 77, if noise is mixed in the vertical synchronizing signal, the polarity cannot be switched, and the display cannot be performed. However, by interposing the synchronization signal correction circuit 73 of the present invention, these can be prevented. Also, if noise is mixed in the horizontal synchronization signal, the vertical scanning clock will increase or decrease, causing abnormalities in the vertical scanning timing, causing the screen to expand or contract.
This can also be stabilized by providing the synchronization signal correction circuit 73 of the present invention.

As described above, according to the matrix type display device using the synchronization signal correction circuit of the present invention, it is possible to substantially eliminate display failure and flicker due to disturbance of the synchronization signal of video equipment and the like, and to destroy the display device due to malfunction. Can be prevented.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a matrix-type display device that performs waveform shaping of a synchronization signal or generates a synchronization signal when there is no signal, and can perform normal display even during special playback of video. it can.

[Brief description of the drawings]

 FIG. 1 is a block diagram of a basic embodiment of the present invention, FIG. 2 is a block diagram of NTSC, FIG. 3 is a waveform diagram of the principle of the present invention, and FIG. 4 is a waveform of a pulse adding process of the present invention. FIG. 5, FIG. 5 is a waveform diagram of the noise removal processing of the present invention, FIG. 6 is a sample diagram of the waveform processing of the present invention, FIG. 7 is a configuration diagram of an application example of the present invention, and FIG. FIG. 9 is a waveform diagram of the synchronization signal during reproduction. 1; edge detection section; 2; pulse addition section; 3; noise removal section; 4; pulse width correction section.

Continuation of front page (72) Inventor Kazuhiro Takahara 1015 Ueodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-55-107388 (JP, A)

Claims (1)

(57) [Claims] 1. A matrix display device controlled in a matrix by a horizontal synchronizing signal and a vertical synchronizing signal, an edge detecting section (1) for detecting an edge of a pulse, and a predetermined time from the edge detection by the edge detecting section. A pulse adding unit (2) for generating a pulse when the next pulse is not input even after the lapse of time, and when a next pulse is input before a predetermined time has passed since the edge detection by the edge detection unit. A synchronizing signal correction circuit comprising: a noise removal unit (3) for removing the pulse; and a pulse width correction unit (4) for correcting a pulse other than the predetermined pulse width to a predetermined pulse width. Matrix display device.