JP2002278493A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a vertical scanning part is overloaded to stop operation when an abnormal data enable signal is inputted thereto. SOLUTION: This image display device is provided with a line count circuit 11 which counts the number of times of an effective image signal presented by the data enable signal specifying at least an effective timing of the image signal during a single vertical scanning period, and judges whether or not the number of times is a specified number or more, a controller 12 which detects vertical synchronization by using the data enable signal and outputs a vertical synchronous signal when the result of the judgment presents the specified number or more, and does not output the vertical synchronous signal when the number of times is less than the specified number, and a scanning circuit 14 which line-sequentially and vertically scans the picture display part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, an information processing device, and a program used for a display for displaying an image signal of a personal computer or the like.

[0002]

2. Description of the Related Art FIG. 3 is a schematic view of a conventional image display device, in which 31 is an image display unit, and 32 is an image display unit 31.
Is a controller that detects vertical synchronization based on the input data enable signal and controls the vertical scanning circuit 32, and 34 generates various voltages required for vertical scanning. Is a scanning voltage generation circuit.

FIG. 4 is a waveform diagram showing the operation of the conventional image display device. Reference numeral 42 denotes a data enable signal.
1 is an image signal, 43 is a data enable signal 42
Is a vertical synchronizing signal generated based on. 44 is an irregular data enable signal, and 45 is a vertical synchronization signal erroneously generated based on the irregular data enable signal 44.

[0004] The controller 33 has a vertical blanking time in which data becomes invalid for a predetermined period between a screen and a screen of the next frame.
2 is not input for a predetermined time, and
3 is detected. The scanning line drive circuit 32 to which the vertical synchronizing signal has been input enables the first-stage selection signal for driving the uppermost line of the image display section, and causes the uppermost section of the image display section to be selected. Thereafter, the selection signal is sequentially shifted to select the image display section line-sequentially and perform vertical scanning.

[0005]

However, in such a configuration, a normal data enable signal is not input at an unintended timing or at an unstable timing that occurs at the time of starting the system, and a data enable signal having an extremely long period is not provided. When a signal is input, an erroneous vertical synchronization is detected. When this erroneous vertical synchronizing signal is input to the vertical scanning circuit, the first stage is set to the selected state when scanning of one frame is not completed.

That is, a plurality of lines are selected for an image display unit where only one line is normally selected, and an overload is applied to a vertical scanning voltage generating circuit for supplying a vertical scanning voltage to the vertical scanning circuit. In such a case, the operation of the image display device is stopped in the worst case.

The present invention has been made in consideration of the above problems, and has an image display apparatus that does not overload a vertical scanning voltage generation circuit even when an irregular data enable signal is input, and thus does not cause an operation stop. It is an object to realize an information processing device and a program.

[0008]

According to a first aspect of the present invention (corresponding to claim 1), a data enable signal for defining at least the effective timing of an image signal during one vertical period is provided. A line count circuit that counts the number of times that the image signal indicates that it is valid, and determines whether the number is equal to or greater than a predetermined number, and when the determination result indicates that the number is equal to or greater than the predetermined number, A controller that does not output the vertical synchronization signal when the number of times is less than the predetermined number, and outputs a vertical synchronization signal by detecting vertical synchronization using the data enable signal; and And a scanning circuit that vertically scans the image display unit line-sequentially based on the above.

Further, the second invention (corresponding to claim 2)
Comprises a processing means for processing data, and a display means for displaying a result processed by the processing means, wherein the display means uses the image display device according to the first aspect of the present invention. Device.

Further, the third invention (corresponding to claim 3)
In the image display device according to the first aspect of the present invention, the number of times that the data enable signal defining at least the valid timing of the image signal indicates that the image signal is valid during one vertical period is counted. A line count circuit that determines whether or not is greater than or equal to a predetermined number, and, if the determination result indicates that the number is greater than or equal to the predetermined number, detects vertical synchronization using the data enable signal and outputs a vertical synchronization signal. A controller that does not output the vertical synchronization signal when the number of times is less than the predetermined number, and a scanning circuit that vertically scans the image display unit line-sequentially based on the vertical synchronization signal. It is a program for causing a computer to function as a whole or a part.

The present invention is, as an example, an image display device that receives at least an image signal, a clock, and a data enable signal that defines the effective timing of the image signal, detects vertical synchronization based on the data enable signal, and displays an image. A line count circuit that counts the number of data enable signals input during one vertical period to determine whether or not a predetermined number or more of data enable signals have been input; A controller for detecting a vertical synchronization signal based on an input data enable signal and controlling vertical scanning, and a vertical scanning circuit for vertically scanning an image display section line-sequentially based on the vertical synchronization signal are provided. Image display device.

As described above, according to the present invention, the vertical synchronizing signal is not input to the vertical scanning circuit and a plurality of lines of the image display section are simultaneously scanned unless a predetermined number or more of data enable signals are input. Never be.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to an image display apparatus which receives at least an image signal, a clock, and a data enable signal for defining the effective timing of the image signal, detects vertical synchronization based on the data enable signal, and displays an image. A line count circuit that counts the number of data enable signals input during one vertical period to determine whether or not a predetermined number or more of data enable signals are input, and a determination condition from the line count circuit. A controller that detects a vertical synchronization signal based on a data enable signal input thereto and controls vertical scanning, and a vertical scanning circuit that vertically scans an image display unit line-sequentially based on the vertical synchronization signal. It is an image display device characterized by the following.

According to the present invention, the above configuration has an effect of preventing a plurality of lines from being scanned at the same time even if an irregular data enable signal is input.

FIG. 1 shows an embodiment of the present invention.
This will be described with reference to FIG.

(Embodiment 1) FIG. 1 is a schematic diagram of an image display device according to Embodiment 1 of the present invention.

FIG. 2 is a waveform chart showing the operation of the image display device of the present invention.

In FIG. 1, reference numeral 11 denotes a line count circuit for counting an input data enable signal.
Reference numeral 2 denotes a controller that detects vertical synchronization and controls vertical scanning. Reference numeral 13 denotes an image display unit. Reference numeral 14 denotes a vertical scanning circuit that scans the image display unit. Reference numeral 15 denotes a scan that generates a voltage required for vertical scanning. It is a voltage generation circuit.

In FIG. 2, reference numeral 21 denotes an image signal;
2 is a normal data enable signal, 23 is a vertical synchronization signal detected based on the data enable signal, 24 is a judgment output of the line count circuit, and 25
Is an irregular data enable signal.

The operation of the liquid crystal display device of the present embodiment configured as described above will be described below.

The controller 12 observes the input data enable signal 22, and outputs a vertical synchronizing signal 23 if the data enable signal is not input for a predetermined time. Based on the vertical synchronizing signal 23, the vertical scanning circuit 14
Displays the image by vertically scanning the image display unit 13 line-sequentially.

When an irregular data enable signal as shown at 24 in FIG. 2 is input, the line count circuit 11 continues to operate until a predetermined number of data enable signals are input, for example, the normal line number. The determination output 24 is invalidated until the value becomes 1/2. When the determination output 24 is invalid, the controller 12 does not output the vertical synchronization signal 23 to the vertical scanning circuit 14, and the vertical scanning circuit does not start vertical scanning. Therefore, a plurality of lines are not simultaneously scanned on the image display unit, that is, the scanning voltage generation circuit 15
No excessive load is applied to the

As described above, according to the present embodiment, even when a data enable signal at an irregular timing is input, a plurality of lines are not scanned at the same time, and an image which does not cause an operation error is generated. A display device can be realized.

Note that the vertical scanning circuit 14 of the present embodiment is an example of the scanning circuit of the present invention.

The image processing apparatus further comprises a processing means for processing data, and a display means for displaying a result of the processing performed by the processing means, wherein the display means uses the image display apparatus of the present invention. Also belong to the present invention.

Further, the present invention is a program for causing a computer to execute the functions of all or a part of the above-described image display device of the present invention (or a device, an element, a circuit, a unit, etc.), A program that operates in cooperation with a computer.

It should be noted that some means (or devices, elements, circuits, units, etc.) of the present invention means some of the plurality of means, or one of the means. Means some functions or some operations.

The present invention also includes a computer-readable recording medium on which the program of the present invention is recorded.

[0029] One embodiment of the program of the present invention may be a mode in which the program is recorded on a computer-readable recording medium and operates in cooperation with the computer.

[0030] One embodiment of the program of the present invention may be a mode in which the program is transmitted through a transmission medium, read by a computer, and operates in cooperation with the computer.

The recording medium includes a ROM and the like, and the transmission medium includes a transmission medium such as the Internet,
Light, radio waves, sound waves, etc. are included.

Further, the computer of the present invention described above has
It is not limited to pure hardware such as a CPU, but may include firmware, an OS, and peripheral devices.

As described above, the configuration of the present invention may be realized by software or hardware.

[0034]

As is apparent from the above description, the present invention provides an image display device in which an image displayed on the image display device is not disturbed even when an irregular data enable signal is input. An information processing device and a program can be provided.

Further, the present invention provides an image display apparatus, an information processing apparatus, and a program which have a simple configuration and prevent a serious trouble such as an operation stop even when an irregular data enable signal is input. I can do it.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an image display device according to an embodiment of the present invention.

FIG. 2 is a waveform chart of the embodiment.

FIG. 3 is a schematic diagram of a conventional image display device.

FIG. 4 is a waveform diagram of a conventional image display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Line count circuit 12 Gate line 13 Common electrode line 23 Driving waveform of normal part at inspection 24 Driving waveform of abnormal part at inspection

Claims (3)

[Claims] A data enable signal defining at least a valid timing of an image signal during one vertical period counts the number of times that the image signal is valid, and determines whether the number is equal to or more than a predetermined number. A line count circuit for determining, when the determination result indicates that the number is equal to or more than the predetermined number, a vertical synchronization signal is detected by using the data enable signal, and a vertical synchronization signal is output; An image display device comprising: a controller that does not output the vertical synchronization signal when the number is less than the number; 2. An information processing apparatus comprising: a processing unit for processing data; and a display unit for displaying a result processed by the processing unit, wherein the display unit uses the image display device according to claim 1. apparatus. 3. The image display device according to claim 1, wherein the number of times that the data enable signal for defining at least the valid timing of the image signal indicates that the image signal is valid during one vertical period is counted. A line count circuit that determines whether or not is greater than or equal to a predetermined number, and, if the determination result indicates that the number is greater than or equal to the predetermined number, detects vertical synchronization using the data enable signal and detects a vertical synchronization signal. A controller that does not output the vertical synchronization signal when the number of times is less than the predetermined number, and a scanning circuit that vertically scans the image display unit line-sequentially based on the vertical synchronization signal. A program that causes a computer to function in whole or in part.