JPH113070A - Controller for liquid crystal display panel, control method, and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to display surely picture data from the leading of a liquid crystal display panel by detecting a data-enable signal being made active while picture data is supplied to a panel, and controlling display timing. SOLUTION: A D flip-flop 20 is synchronized with a clock signal from a picture data supplying source, latches a data-enable signal ENAB, and detects it. When an output of the D flip-flop 20 is made to be a H level, that is, a data-enable signal ENAB is supplied from the picture data supplying source, a timing making circuit 32 outputs a clock D-CLK for data driver, a start pulse D-SP for data driver, a latch pulse LP, picture data DATD, a clock G-CLK for gate driver, and a start pulse G-SP for gate driver so that display timing of picture data in a liquid crystal display panel can be controlled with display timing based on the data-enable signal ENAB outputted from an AND circuit 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a timing controller for a liquid crystal display device which controls a driver for driving a liquid crystal display panel to control a display timing of image data on the liquid crystal display panel.

[0002]

2. Description of the Related Art FIG. 1 is a circuit diagram showing a main part of an example of a conventional liquid crystal display device of the XGA (1024.times.768 dots) type. In FIG. 1, reference numeral 10 denotes an active matrix type liquid crystal display panel; A data driver that drives a data bus (signal line) formed on the liquid crystal display panel 10, and a gate driver 12 that drives a gate bus (scan line) formed on the liquid crystal display panel 10.

[0003] A vertical synchronizing signal VSYNC, a horizontal synchronizing signal HSYNC, a clock CLK, a data enable signal ENAB, and image data DATA supplied from an image data supply source (not shown) are input to a vertical synchronizing signal VSYNC. This is a timing controller for a liquid crystal display device that controls the display timing of image data DATA on the liquid crystal display panel 10 based on the display timing based on the horizontal synchronization signal HSYNC.

In this example, the timing controller 13 for the liquid crystal display device sends a clock D-CLK for data driver, a start pulse DSP for data driver, and a latch pulse LP to the data driver 11.
And image data DATA, and the gate driver 1
2 is configured to supply a gate driver clock G-CLK and a gate driver start pulse G-SP.

FIG. 2 is a timing chart showing horizontal driving timings of the conventional liquid crystal display device shown in FIG. 1. FIG. 2A shows a horizontal synchronizing signal HSYNC, FIG. 2B shows a clock CLK, FIG. 2C shows image data DATA, and FIG. 11D indicates a data enable signal ENAB. In addition, Th
Is a horizontal cycle period, Thp is a horizontal flyback period, Thd is a display effective period, Thb is a back porch of the display effective period Thd, and Thf is a front porch of the display effective period Thd.

FIG. 3 is a timing chart showing the vertical drive timing of the conventional liquid crystal display device shown in FIG. 1. FIG. 3A shows a vertical synchronization signal VSYNC, FIG. 3B shows a horizontal synchronization signal HSYNC, and FIG. 3C shows image data DATA. , FIG.
D indicates a data enable signal ENAB. Here, Tv is a vertical cycle period, Tvp is a vertical flyback period, Tv
d is a display effective period, Tvb is a back porch of the display effective period Tvd, and Tvf is a front porch of the display effective period Tvd.

FIG. 4 shows one of the conventional liquid crystal display devices shown in FIG.
FIG. 5 is a diagram showing a relationship between a data display area and a blank area in a vertical cycle period. In FIG. 4, reference numeral 15 denotes a data display area, and 16 denotes a blank area. The data display area 15 corresponds to the pixel area of the panel, and the size of the data is equal to the number of pixels. Also, the sum of the data display area 15 and the blank area 16 is (the size of) the data actually sent to the liquid crystal display device, and in addition to the image data, data not involved in the display (invalid data: for example, “ L
OW "signal, which can be regarded as a state where no image data is supplied).

[0008]

The conventional timing controller 13 for a liquid crystal display device comprises a back porch Thb, Tvb and a front porch Th in the horizontal and vertical directions.
The set values of f and Tvf are fixed, and these back pouches Thb, Tvb and front pouches Thf, Tv
The data driver 11 and the gate driver 12 are configured to display an image on the liquid crystal display panel 10 at a display timing determined by f.

Therefore, the conventional timing controller 13 for a liquid crystal display device can be used only for a personal computer or the like which performs image display at a specific display timing, and is used for a personal computer or the like having a different display timing. In such a case, a display defect or a display position shift occurs. As shown in FIG. 4, when the fixed values of the back porches Thb and Tvb are on the first line and accurately indicate the starting pixel of the data display area 15 scanned by the first clock of 1024 clocks, Image data is correctly displayed in the data display area 15 during the data valid periods Thd and Tvd in synchronization with the data enable signal ENAB.

The fixed values of the back porches Thb and Tvb and the fixed values of the front porches Thf and Tvf depend on the timing specifications of the electronic device on which the liquid crystal display device is mounted.
For example, the timing specification of the electronic device is determined first, and the back porch Thb, Tv
The fixed value of b and the fixed values of the front porches Thf and Tvf are determined. Alternatively, the timing specifications of the electronic device are determined so as to match the fixed values of the back porch Thb and Tvb and the fixed values of the front porch Thf and Tvf.

If the fixed values of the back porches Thb and Tvb and the fixed values of the front porches Thf and Tvf do not match the timing specifications of the electronic device, the image data cannot be accurately displayed on the data display area 15. For example, the image data is displayed in the data display area 15 with a shift in the horizontal and / or vertical directions, and a part of the image is lost.

Therefore, the timing controller 13
The present invention is not applicable to various timing specifications of an electronic device on which a liquid crystal display device is mounted, but can be applied only to specific timing specifications. In fact, the timing controllers 13 need to be individually designed to meet different timing specifications of the electronic devices mounted. Usually, the design of the timing controller 13 takes a considerable amount of time (for example,
It takes about one month), and it takes a long time (for example, about two months) to ship mass-produced products. For this reason, there has been a problem that it is not possible to rapidly develop a product that requires a timing controller for a liquid crystal display device, such as a personal computer having a liquid crystal display device.

The present invention solves the above-mentioned problems of the prior art,
An object of the present invention is to provide a controller for a liquid crystal display panel that can be applied to various timing specifications of an electronic device on which the liquid crystal display device is mounted.

[0014]

According to a first aspect of the present invention, a timing controller for a liquid crystal display panel includes a data enable signal detection circuit (corresponding to a circuit 20 in an embodiment described later) for detecting a data enable signal supplied to the timing controller. ) And a timing creation circuit (32) for controlling display timing of image data to be displayed on the liquid crystal display panel based on the detected data enable signal.

The data enable signal is a signal that becomes active while image data is being supplied to the panel. The timing at which the data enable signal becomes active is arbitrary, but is always synchronized with the image data. Therefore, if the display timing is controlled by detecting the data enable signal, the display timing of the image data can be controlled. That is, if the display is started by detecting the data enable signal, the image data can be surely displayed from the top of the liquid crystal display panel at any time when the data enable signal becomes active. become able to. Therefore, the display timing can be freely controlled irrespective of the back porch and the front porch of the horizontal and vertical synchronizing signals as in the related art, and it is possible to correspond to all display timing specifications of the electronic device.

According to a second aspect of the present invention, there is provided the timing controller according to the first aspect, wherein the first controller starts driving each line of the liquid crystal display panel from the data enable signal.
First circuit for generating start pulse (FIG. 15C)
And a second circuit (FIG. 15F) for generating a second start pulse for starting driving of a scan line of the liquid crystal display panel from the data enable signal.

According to the above configuration, the start timing of panel driving can be determined based on the detected data enable signal, so that no matter when the data enable signal becomes active, the image is reliably started from the top of the liquid crystal display panel. Data can be displayed. In the timing controller according to the third aspect, the timing generation circuit according to the first aspect includes a circuit portion (15F) that detects the start of each frame based on the data enable signal.

Conventionally, a synchronization signal (vertical synchronization signal) has been used for discrimination between frames. However, discrimination between frames is performed based on a data enable signal. This is because the control of the display timing according to the first aspect of the invention is performed based on the data enable signal, not based on the synchronization signal. According to the fourth aspect of the present invention, the timing controller of the first aspect further includes a synchronization signal detection circuit (22, 23, 24) for detecting a horizontal and vertical synchronization signal, and a data enable signal detection circuit for detecting the data enable signal. A pseudo data enable signal generating circuit (25) for generating a pseudo data enable signal when the horizontal and vertical synchronizing signals are detected in a state in which the image data is not synchronized with the image data based on the pseudo data enable signal. The display timing of is controlled.

Even if the supply of the data enable signal from the outside is stopped for some reason, the display can be continued by simulating the data enable signal. Further, since the horizontal and vertical synchronizing signals are detected, the same display timing control as that in the related art can be performed, so that it is possible to flexibly respond to a user's request. According to the fifth aspect of the present invention, the timing controller according to the first aspect further includes a synchronization signal detection circuit (22, 23, 24) for detecting a horizontal and vertical synchronization signal, and the horizontal and vertical synchronization signals are not detected. A protection circuit (27) for generating a pseudo data enable signal, and the timing creation circuit controls the display timing of the image data based on the pseudo data enable signal.

According to this configuration, even when the horizontal and vertical synchronizing signals and the data enable signal are not supplied (not detected) due to a failure or the like, the pseudo data enable signal is generated. It is possible to display predetermined image data such as black or white, and to prevent the DC voltage from being continuously applied to the liquid crystal of each pixel of the liquid crystal display panel.

According to a sixth aspect of the present invention, in the method for controlling display timing of a liquid crystal display panel, a data enable signal applied to a timing controller is detected, and a display on the liquid crystal display panel is performed based on the detected data enable signal. This is a method characterized by controlling the display timing of image data to be displayed. The same operation and effect as those of the first aspect are obtained.

According to a seventh aspect of the present invention, there is provided a liquid crystal display panel having signal lines and scanning lines, a data driver for driving the signal lines, a gate driver for driving the scanning lines, and image data to be displayed on the liquid crystal display panel. A timing controller for controlling the display timing of the liquid crystal display panel, based on the detected data enable signal, and a data enable signal detection circuit for detecting a data enable signal supplied to the timing controller. A liquid crystal display device having a timing creation circuit for controlling display timing of image data to be displayed. A liquid crystal display device having the effects of the first aspect is obtained.

According to an eighth aspect of the present invention, the timing controller is the timing controller according to any one of the second to fifth aspects. A liquid crystal display device having the above-described effects of claims 2 to 5 can be obtained.

[0024]

FIG. 5 is a diagram showing a configuration of a timing controller according to one embodiment of the present invention. The illustrated timing controller replaces the timing controller 13 of FIG. That is, the liquid crystal display device of the present invention includes the timing controller, the data driver 11, the gate driver 12, and the liquid crystal display panel 10 shown in FIG.

The timing controller shown in FIG. 5 has three display timing control modes different from display timing control using fixed values of the back porch Thb and Tvb and fixed values of the front porch Thf and Tvf as in the prior art. . The first display timing control mode directly replaces the conventional display timing control, and the second and third display timing control modes are backups or additions of the first mode. That is, the second and third display timing modes are optional modes,
It may not be necessary.

The timing controller shown in FIG.
Flip-flops 20, 22, and 23, AND circuit 2
1, 24, pseudo data enable signal generation circuit 25, N
OR circuit 26, protection circuit 27, and timing creation circuit 3
And 2. The first display timing control mode is generally realized by the D flip-flop 20, the AND circuit 21, and the timing creation circuit 32. The second display timing control mode generally includes D flip-flops 23, 2
3, an AND circuit 24, a pseudo data enable signal creation circuit 25, and a timing creation circuit 32. The third display timing control mode generally includes a NOR circuit 26, a protection circuit 27, and a timing creation circuit 32.

The D flip-flop latches the data enable signal ENAB in synchronization with a clock signal from an external image data supply source (not shown), and functions as a data enable signal detector. Similarly, the data enable signal ENAB is generated by an external image data supply source (not shown). Data enable signal E
When NAB becomes active, the supply of image data generated by the image data source begins. As described later in detail, the first display timing control mode controls the display timing using the data enable signal ENAB.

The AND circuit 21 outputs the data enable signal ENAB and the output signal DET1 of the D flip-flop 20.
AND operation is performed. Data enable signal ENAB
Is supplied from the image data supply source, the output signal DET1 of the D flip-flop 20 becomes high potential (H level). Therefore, the data enable signal ENAB is output from the AND circuit 21. When the data enable signal is not supplied, the output signal D of the D flip-flop 20
ET1 is at a low potential (L level), and the output of the AND circuit 21 is at L level.

The D flip-flop 22 receives the clock CLK
The horizontal synchronization signal HSYNC is latched in synchronization with the horizontal synchronization signal, and functions as a horizontal synchronization signal detector. The D flip-flop 23 latches the vertical synchronization signal VSYNC in synchronization with the clock signal CLK, and functions as a vertical synchronization signal detector. The AND circuit 24 performs an AND operation on the output signals of the D flip-flops 22 and 23. The D flip-flops 22 and 23 and the AND circuit 24 constitute a horizontal / vertical synchronization signal detection circuit.

The horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC are supplied from an image data supply source. Then, the output signals of the D flip-flops 22 and 23 become H level, and the output signal DET2 of the AND circuit 24 becomes H level. The output signal DET2 of the AND circuit 24 is provided to the timing creation circuit 32. If the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are not supplied from the image data supply source, the D flip-flop 2
2 and 23 are at the L level, and the AND circuit 24
Is at L level.

Pseudo data enable signal creation circuit 25
Receives the clock CLK from the image data supply source and the output signal DET2 of the AND circuit 24, and generates the pseudo data enable signal ENAB-D1 at a predetermined timing after the output signal DET2 of the AND circuit 24 becomes H level. I do. The pseudo data enable signal ENAB-D1 is output to the timing creation circuit 32.

The NOR circuit 26 is connected to the D flip-flop 20
Output signal DET1 and the output signal DET of the AND circuit 24
2 and a NOR operation is performed. When the output signal DET1 of the D flip-flop 20 goes high, that is, when the data enable signal ENAB is supplied from the image data supply source, or when the output signal DET2 of the AND circuit 24 goes high, That is, when the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are supplied from the image data supply source, the output signal of the NOR circuit 26 becomes L level.

On the other hand, the output signal of the D flip-flop 20 is at the L level, and the output signal DET of the AND circuit 24 is
2 is L level, that is, when the data enable signal ENAB, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC are not supplied from the image data supply source,
The output of the OR circuit 26 becomes H level. 27 is a clock CLK and NO supplied from the image data supply source.
When the output of the R circuit 26 is input and the output of the NOR circuit 26 is set to the H level, that is, the data enable signal ENAB and the horizontal synchronization signal HSYNC from the image data supply source
And when the vertical synchronization signal VSYNC is not supplied,
This is a protection circuit that outputs a pseudo data enable signal ENAB-D2.

FIG. 6 is a circuit diagram showing the structure of the protection circuit 27. In FIG. 6, reference numeral 29 denotes a pseudo-horizontal synchronization signal HSYNC-D generated and output when the output of the NOR circuit 26 is at the H level. This is a pseudo horizontal synchronizing signal generation circuit. Reference numeral 30 denotes a pseudo data enable signal generation circuit that generates and outputs a pseudo data enable signal ENAB-D2 when the pseudo horizontal synchronization signal generation circuit 29 outputs the pseudo horizontal synchronization signal HSYNC-D.

In FIG. 5, reference numeral 32 denotes a timing generation circuit for controlling the display timing of the image data DATA on the liquid crystal display panel.
2 includes image data D supplied from an image data supply source.
ATA, clock CLK, output of AND circuit 21, output of pseudo data enable signal generation circuit 25,
The output of the D flip-flop 20, the output of the AND circuit 24, and the output of the protection circuit 27 are supplied.

In response, the timing generation circuit 32
Is a data driver clock D-CLK for a data driver driving a data bus of a liquid crystal display panel.
, A data driver start pulse D-SP, a latch pulse LP and image data DATA, and a gate driver clock G-CLK and a gate driver for driving a gate bus of the liquid crystal display panel. It is configured to supply a driver start pulse G-SP.

FIG. 7 shows the output of the D flip-flop 20 = H
FIG. 7A is a timing chart showing the operation of the timing generation circuit 32 when the level becomes the level. FIG. 7A shows a vertical synchronization signal VSYNC supplied from the image data supply source, a horizontal synchronization signal HSYNC, and a data enable signal ENAB.
, A clock CLK, and image data DATA.

FIG. 7B shows a data driver clock D-CLK supplied to the data driver, a data driver start pulse D-SP, and a latch pulse LP.
FIG. 7C shows a gate driver clock G- supplied to the gate driver.
CLK and a gate driver start pulse G-SP.

As described above, the timing creation circuit 32
When the output of the D flip-flop 20 becomes H level, that is, when the data enable signal ENAB is supplied from the image data supply source, the liquid crystal is displayed at a display timing based on the data enable signal ENAB output from the AND circuit 21. The data driver clock D-CLK and the data driver start pulse D-CLK are used to control the display timing of image data on the display panel.
-SP, latch pulse LP, image data DATA, gate driver clock G-CLK, and gate driver start pulse G-SP.

As shown in FIG. 7, the D flip-flop 2
When the 0 output signal DET1 goes to H level, that is, when the data enable signal ENAB is supplied from the image data supply source, the timing creation circuit 32 outputs the synchronization signal VSYN.
Even if C and HSYNC are at L level, the AND circuit 21
The display timing is controlled based on the data enable signal ENAB supplied from the CPU. This timing control
This is completely different from the conventional display timing control shown in FIG.

More specifically, the data enable signal E
While NAB is at the H level, the image data DATA is supplied. 7, a rising edge * 1 of the data enable signal ENAB corresponds to the first line of the display panel 10. The data enable signal ENAB is kept at the H level while each line constituting one frame (screen) is supplied from the image data supply source.

In response to the rising edge * 1 of the data enable signal, the data driver start pulse D-
The SP is generated by the timing creation circuit 32 and output to the data driver 11. Further, in response to the rising edge * 1 of the data enable signal ENAB, a start pulse G-SP for a gate driver is created by the timing creation circuit 32 and output to the gate driver 12. The gate driver start pulse G-SP is
It is kept at the H level during the first line. Therefore, the start pulse D-SP for the gate driver is generated by the rising edge * of the data enable signal ENAB indicating the second line.
In response to 2, the level becomes L level.

Further, as described later, referring to the data enable signal ENAB, the latch pulse LP and the gate driver clock G-CLK are generated by the timing generation circuit 3.
2 is created. Further, as will be described later, the data generation clock D-CLK is generated from the clock CLK by the timing generation circuit 32. As described above, by detecting only the data enable signal ENAB, it is possible to reliably display the image data DATA from the first pixel of the display panel 10 that is scanned first. The above control corresponds to a first display timing control mode.

FIG. 8 shows a vertical synchronization signal VSYNC supplied from the image data supply source and a horizontal synchronization signal HSY.
NC, data enable signal ENAB, and clock C
LK and image data DATA are shown. FIG. 9A shows the horizontal synchronization signal H supplied from the image data supply source.
9B shows a SYNC, a clock CLK, and image data DATA. FIG. 9B shows a pseudo data enable signal EN output from the pseudo data enable signal creation circuit 25.
AB-D1 is shown.

FIG. 9C shows a data driver clock D-CLK supplied to the data driver, a data driver start pulse D-SP, and a latch pulse LP.
FIG. 9D shows a gate driver clock G- supplied to the gate driver.
CLK and a gate driver start pulse G-SP.

As described above, the timing creation circuit 32
The output of the D flip-flop 20 is kept at L level,
When the output of the AND circuit 24 becomes H level, that is,
When the data enable signal ENAB is not supplied from the image data supply source and the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are supplied, the image data on the liquid crystal display panel is displayed at the display timing based on the pseudo data enable signal ENAB-D1. In order to control the display timing, the data driver clock D-CL
K, a data driver start pulse D-SP, a latch pulse LP, image data DATA, a gate driver clock G-CLK, and a gate driver start pulse G-SP.

For example, if a failure occurs in the image data supply source,
If image data DATA is supplied but supply of data enable signal ENAB stops,
In the first display timing control mode, the image data D
ATA cannot be displayed. In such a case, the pseudo data enable signal ENAB-D1 is used. This pseudo data enable signal ENAB-D1 is
It is created at a predetermined timing after the output signal DET2 of the AND circuit 24 goes high. Therefore, the pseudo data enable signal ENAB-D1 is the image data DATA
Therefore, the image data DATA may be shifted on the liquid crystal display panel 10. However,
The second display timing control mode functions as a backup mode when the supply of the data enable signal ENAB stops due to a failure.

Also, the pseudo data enable signal ENAB
If the above-described back porch Thb, Tvb, Thf, Tvf is determined so that -D1 is synchronized with the image data DATA, the second display timing control mode conforms to a specific timing specification as in the related art. Furthermore, the second
The display timing control mode of the horizontal synchronization signal HSYN
The present invention can be applied to a timing specification in which C and the vertical synchronization signal VSYNC are supplied but the data enable signal ENAB is not supplied.

FIGS. 10 and 11 show the output of the D flip-flop 20 at the L level and the output of the AND circuit 24 at the L level.
13 is a timing chart illustrating an operation of the timing generation circuit 32 (third display timing control) when the L level is maintained. FIG. 10 shows the vertical synchronization signal VSYNC supplied from the image data supply source and the horizontal synchronization signal H
SYNC, a data enable signal ENAB, a clock CLK, and image data DATA are shown.

FIG. 11A shows a pseudo-horizontal synchronization signal HSYNC-D output from the pseudo-horizontal synchronization signal generation circuit 29.
And a pseudo data enable signal ENAB-D2 output from the pseudo data enable signal creation circuit 30 and a clock CLK supplied from an image data supply source. FIG. 11B shows a data driver clock D-CLK supplied to the data driver, a data driver start pulse DSP, a latch pulse LP, and image data DATA. FIG. 11C shows a gate driver. Gate driver clock G-CL to be supplied
K and the start pulse G-SP for the gate driver are shown.

As described above, the timing creation circuit 32
When the output of the D flip-flop 20 is maintained at the L level and the output of the AND circuit 24 is maintained at the L level, that is, when the data enable signal ENAB, the horizontal synchronization signal HSYNC, and the vertical synchronization signal VSYNC are not supplied from the image data supply source Is a pseudo data enable signal ENAB-
The data driver clock D-CLK, the data driver start pulse D-SP, and the latch pulse L are controlled so that the display timing of the image data DATA on the liquid crystal display panel can be controlled by the display timing based on D2.
P, image data DATA, clock G for gate driver
-CLK and start pulse G-SP for gate driver
Is output.

However, in this case, since the image data DATA is not supplied from the image data supply source, the image data DATA generated by the timing generation circuit 32 is supplied to the data driver. FIG. 12 is a flowchart showing the operation of one embodiment of the present invention. In one embodiment of the present invention, every time one frame period starts (step ST1), a synchronization signal supplied from an image data supply source is supplied. , The data enable signal ENAB (step ST2), the horizontal synchronizing signal HSYN
C and the vertical synchronization signal VSYNC are detected (step ST4).

Here, when the data enable signal ENAB is supplied from the image data supply source, the output of the D flip-flop 20 becomes H level, and the AND circuit 21
Output data enable signal ENAB. As a result, in the timing creation circuit 32, based on the fact that the output of the D flip-flop 20 has become H level,
Data enable signal E output from AND circuit 21
The data driver and the gate driver are controlled so that the display timing of the image data DATA on the liquid crystal display panel can be controlled by the display timing based on the NAB (step ST3).

On the other hand, when the data enable signal ENAB is not supplied from the image data supply source and the horizontal synchronization signal HSYNC and the vertical synchronization signal VSYNC are supplied, the output of the D flip-flop 20 is maintained at the L level. At the same time, the output of the AND circuit 24 becomes H level, and the pseudo data enable signal generation circuit 25 outputs the pseudo data enable signal ENAB-D1.

As a result, in the timing creation circuit 32, based on the fact that the output of the D flip-flop 20 is kept at L level and the output of the AND circuit 24 is at H level, the pseudo data enable signal ENAB-
The display timing of the image data on the liquid crystal display panel can be controlled by the display timing based on D1.
Control for the data driver and the gate driver is performed (step ST5).

When the data enable signal ENAB, the horizontal synchronizing signal HSYNC, and the vertical synchronizing signal VSYNC are not supplied from the image data supply source, the output level of the D flip-flop 20 becomes L level and the AND circuit 24
Is maintained at the L level, and the output of the NOR circuit 26 attains the H level. As a result, the protection circuit 27 outputs the pseudo data enable signal ENAB-D2, and the timing generation circuit 32 outputs the display timing of the image data DATA on the liquid crystal display panel according to the display timing based on the pseudo data enable signal ENAB-D2. Is controlled for the data driver and the gate driver (step ST6).

Next, the timing creation circuit 32 shown in FIG.
Will be described. FIGS. 13, 14 and 15 are block diagrams showing the internal configuration of the timing creation circuit 32. First, referring to FIG. 13, the timing creation circuit 32 has a 3-1 selector 41. The selector 41 detects the detection signals DET1 and DET shown in FIG.
2, one signal is selected from the three input signals ENAB, ENAB-D1 and ENAB-D2. Table 1 is a truth table of the selector 41.

[0058]

[Table 1]

The selected data enable signal is used as an internal data enable signal ENAB-INT in FIG.
Are output to the circuit portion shown in FIG.

FIG. 14 shows two flip-flops 43 and 44, an inverter 45, and OR circuits 46 and 1.
It has a 2-bit binary counter 42. The selected data enable signal ENAB-INT is supplied to the flip-flop 4
3 given. The flip-flops 43 and 44, the inverter 45, and the OR circuit 46 detect a leading portion of the internal data enable signal ENAB-INT that changes from L level to H level. The output signal of the OR circuit 46 is given to the counter 42 as a reset signal. In response to the reset signal, the counter 42 starts counting the clock CLK. The count value represented by the 12 bits 2 ^{0 to} 2 ¹¹ includes a gate driver clock G-CLK, a latch pulse LP, a data driver start pulse D-SP, and a gate driver start pulse G, as described below. Used to create the SP.

FIG. 15A shows a clock G for a gate driver.
The corresponding circuit portion of the timing generation circuit 32 for generating -CLK is shown. This circuit part includes a decoder (# 1) 4
7, a decoder (# 2) 48 and a JK flip-flop 49. The decoders 47 and 48 separately decode the 12-bit count value, generate an output signal when the count value reaches a predetermined value, and output the output signal to the JK flip-flop 49. Then, the gate driver clock G-CLK is output from the JK flip-flop 49 to which the clock CLK is supplied.

FIG. 15B shows a corresponding circuit portion of the timing generation circuit 32 for generating the latch pulse LP. This circuit part includes a decoder (# 3) 50 and a decoder (#
4) It has 51 and a JK flip-flop 52. The decoders 50 and 51 separately decode the 12-bit count value, generate an output signal when the count value reaches a predetermined value, and output the output signal to the JK flip-flop 52. Then, the latch pulse LP is output from the JK flip-flop 52 to which the clock CLK is supplied.

FIG. 15C shows a corresponding circuit portion of the timing generating circuit 32 for generating the gate driver start pulse DSP. The illustrated circuit portion includes a decoder (# 5) 53 and a flip-flop 54. Decoder 53 outputs an output signal to flip-flop 54 when a predetermined count value is decoded. Clock C
The flip-flop 54 to which LK is supplied outputs a gate driver start pulse D-SP.

FIG. 15D shows a data driver clock generation circuit 55 that generates a data driver clock D-CLK from the clock CLK. FIG. 15E shows a corresponding circuit portion of the timing generation circuit 32 that outputs the image data DATA. The illustrated circuit portion includes a flip-flop 56, a selector 57, and a flip-flop 58. The flip-flop 56 latches image data from an external image data source. The latched image data is supplied to the selector 57. The selector 57 is also provided with display color data outside the display area (white or black). This color data is used in a third display timing control mode that can be selected when no image data is supplied. The selector 57 selects either image data DATA from outside or display color data outside the display area according to the data selection signal. The data selection signal corresponds to the output signal of the NOR circuit 26 shown in FIG. The selected image data is latched by the flip-flop 58 and the liquid crystal display panel 1
Output to 0.

FIG. 15F shows a corresponding circuit portion of the timing generation circuit 32 that outputs the gate driver start pulse G-SP. FIG. 16 is a timing chart showing the operation of this circuit portion. The circuit part shown is
The head of each frame is detected, and during a period corresponding to the first line, the internal data enable signal ENAB-IN
A start pulse G-SP for a gate driver is created from T.

The circuit portion shown in FIG. 15F includes a decoder (#
6) It has a holding circuit 60, a tip detection circuit 61, and a flip-flop 62 having a data valid terminal. The tip detection circuit 61 includes flip-flops 43, 4
4, an inverter 45 and an OR circuit 46 shown in FIG. Internal data enable signal ENAB-IN
When T is held at the L level during the predetermined period, the decoder 59 outputs an H level pulse. This H-level pulse is held in the holding circuit 60. Then, the H-level pulse held in the holding circuit 60 is output to the data terminal of the flip-flop 62 as HLD.
The circuit 61 includes an internal data enable signal ENAB-IN
A pulse is output each time T is detected. The pulse output from the circuit 61 is supplied to the holding circuit 60 as a reset signal, and is supplied to the data valid terminal of the flip-flop 62 as a data valid signal.

While one line is being scanned, the internal data enable signal ENAB-INT switches from L level to H level before a predetermined time elapses. During a blanking period between adjacent lines, the internal data enable signal ENAB-INT is held at the L level. At this time, the decoder 59 outputs a pulse. This pulse is held in the holding circuit 60. After a lapse of a predetermined period, internal data enable signal ENAB-I
NT switches to H level. This indicates the beginning of the next line. A pulse indicated by * in FIG. 16 is applied to the data valid terminal of the flip-flop 62. Flip-flop 62 receives an H level signal via a data terminal. Therefore, the output signal of the flip-flop 62 is held at the H level until the next rising edge of the internal enable signal ENAB-INT is detected.

As described above, according to the embodiment of the present invention, when the data enable signal ENAB is supplied from the image data supply source, the image on the liquid crystal display panel is displayed at the display timing based on the data enable signal ENAB. The display timing of the data DATA can be controlled. Therefore, the display timing of the image data DATA on the liquid crystal display panel does not depend on the back porch and the front porch in the horizontal and vertical directions,
Since it can be performed at any timing and there is no need to design a timing controller for a liquid crystal display device for each device with a different display timing, a timing controller for a liquid crystal display device such as a personal computer equipped with a liquid crystal display device is required. Product development can be accelerated.

According to the embodiment of the present invention, the data enable signal ENAB is not supplied from the image data supply source, and the horizontal synchronization signal HSYNC and the vertical synchronization signal VS are not supplied.
When YNC is supplied, the horizontal synchronization signal HSYNC is output.
The display timing of the image data DATA on the liquid crystal display panel can be controlled by the display timing based on the vertical synchronization signal VSYNC.

Therefore, image data can be displayed even if the data enable signal ENAB is not supplied due to a failure or the like, and the back porch and the front porch in the horizontal direction and the vertical direction can be displayed in the same manner as the conventional timing controller for a liquid crystal display. It is possible to meet the demand of the user who wants to control the image display timing only at the specific display timing that depends on it.

Further, according to the embodiment of the present invention, even when the data enable signal ENAB, the horizontal synchronizing signal HSYNC and the vertical synchronizing signal VSYNC are not supplied from the image data supply source, the liquid crystal display panel is AC-driven and the liquid crystal display panel is driven. Since it is possible to prevent the DC voltage from being continuously applied to the liquid crystal of each pixel of the display panel, it is possible to suppress the deterioration of the liquid crystal and improve the reliability.

Further, according to one embodiment of the present invention, the timing generation circuit 32 controls the data enable signal ENAB.
Alternatively, the display timing is created based on the pseudo data enable signal ENAB-D1 or the pseudo data enable signal ENAB-D2. Therefore, as shown in FIG. 17, the horizontal blank area is provided on both sides of the horizontal data display area for several clocks, for example, two clocks, and the vertical blank area is provided above and below the vertical data display area. For several clocks, for example,
The liquid crystal display panel can be driven for two clocks and in a shorter horizontal period and shorter vertical period than in the conventional example.

[0073]

According to the timing controller for a liquid crystal display panel according to the first aspect, the method according to the sixth aspect, and the liquid crystal display device according to the seventh aspect, while the image data is supplied to the panel. Since the display timing is controlled by detecting the data enable signal that becomes active, the display can be started by detecting the data enable signal, and even when the data enable signal becomes active at any time, Image data can be reliably displayed from the top of the liquid crystal display panel. Therefore, the display timing can be freely controlled irrespective of the back porch and the front porch of the horizontal and vertical synchronization signals as in the related art, and it is possible to correspond to all display timing specifications of the electronic device.

According to the timing controller of the second aspect, the start timing of panel driving can be determined based on the detected data enable signal. Therefore, even if the data enable signal becomes active at any timing, it is ensured. Image data can be displayed from the top of the liquid crystal display panel. According to the timing controller of the third aspect, it is possible to distinguish between frames based on a data enable signal without using a synchronization signal (vertical synchronization signal) as in the related art.

According to the timing controller of the present invention, even if the supply of the data enable signal from the outside is stopped for some reason, the display is continuously performed by creating the pseudo data enable signal. It is possible. Further, since the horizontal and vertical synchronizing signals are detected, the same display timing control as that of the related art can be performed, so that it is possible to flexibly respond to a user's request.

According to the timing controller of the fifth aspect, the pseudo data enable signal is generated even when the horizontal and vertical synchronization signals and the data enable signal are not supplied (not detected) due to a failure or the like.
It is possible to display predetermined image data such as black or white by driving the liquid crystal display panel with an alternating current, and to prevent a DC voltage from being continuously applied to the liquid crystal of each pixel of the liquid crystal display panel.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a conventional liquid crystal display device.

FIG. 2 is a timing chart showing horizontal driving timings of the conventional liquid crystal display device shown in FIG.

FIG. 3 is a timing chart showing vertical drive timings of the conventional liquid crystal display device shown in FIG.

FIG. 4 is a diagram showing a relationship between a data display area and a blank area in one vertical cycle period of the conventional liquid crystal display device shown in FIG.

FIG. 5 is a block diagram illustrating a timing controller according to an embodiment of the present invention.

6 is a block diagram showing a configuration of a protection circuit 27 shown in FIG.

7 is a timing chart showing the operation of the timing generation circuit 32 shown in FIG. 5 (when the output of the D flip-flop 20 is at a high level).

8 is a timing chart showing the operation of the timing generation circuit 32 shown in FIG. 5 (when the output of the D flip-flop 20 is at a low level and the output of the AND circuit 24 is at a high level).

9 is a timing chart showing the operation of the timing generation circuit 32 shown in FIG. 5 (when the output of the D flip-flop 20 is maintained at a low level and the output of the AND circuit 24 is at a high level).

10 is a timing chart showing the operation of the timing creation circuit 32 shown in FIG. 5 (when the output of the D flip-flop 20 is at a low level and the output of the AND circuit 24 is maintained at a low level).

11 is a timing chart showing the operation of the timing generation circuit 32 shown in FIG. 5 (when the output of the D flip-flop 20 is at a low level and the output of the AND circuit 24 is maintained at a low level).

12 is a flowchart showing the operation of the timing controller shown in FIG.

FIG. 13 is a block diagram (part 1) illustrating an internal configuration of the timing generation circuit 32 illustrated in FIG. 5;

FIG. 14 is a block diagram (part 2) illustrating an internal configuration of the timing creation circuit 32 illustrated in FIG. 5;

FIG. 15 is a block diagram (part 3) illustrating an internal configuration of the timing generation circuit 32 illustrated in FIG. 5;

FIG. 16 is a timing chart showing the operation of FIG. 15F.

FIG. 17 is a diagram showing a relationship between a data display area and a blank area in one vertical cycle period according to one embodiment of the present invention.

[Explanation of symbols]

 VSYNC Vertical synchronization signal HSYNC Horizontal synchronization signal ENAB Data enable signal CLK Clock DATA Image data ENAB-D1 Pseudo data enable signal ENAB-D2 Pseudo data enable signal D-CLK Data driver clock D-SP Data driver start pulse LP Latch pulse G −CLK Gate driver clock G-SP Gate driver start pulse

Claims (8)

[Claims] 1. A timing controller for a liquid crystal display panel, comprising: a data enable signal detection circuit for detecting a data enable signal supplied to the timing controller; and a data controller for detecting image data to be displayed on the liquid crystal display panel based on the detected data enable signal. A timing controller comprising: a timing creation circuit that controls display timing. 2. A first circuit for generating a first start pulse for starting driving of each line of a liquid crystal display panel from a data enable signal, and driving a scan line of the liquid crystal display panel from a data enable signal. 2. A timing controller according to claim 1, further comprising: a second circuit that generates a second start pulse for starting the operation. 3. The timing controller according to claim 1, wherein the timing generation circuit has a circuit portion for detecting the start of each frame based on the data enable signal. 4. The timing controller according to claim 1, further comprising: a synchronization signal detection circuit for detecting a horizontal and vertical synchronization signal; 2. The timing according to claim 1, further comprising a pseudo data enable signal generation circuit for generating a pseudo data enable signal, wherein the timing generation circuit controls display timing of image data based on the pseudo data enable signal. controller. 5. The timing controller further comprises: a synchronization signal detection circuit for detecting a horizontal and vertical synchronization signal; and a protection circuit for generating a pseudo data enable signal when the horizontal and vertical synchronization signals are not detected. 2. The timing controller according to claim 1, wherein the generation circuit controls the display timing of the image data based on the pseudo data enable signal. 6. A method for controlling display timing of a liquid crystal display panel, comprising: detecting a data enable signal provided to a timing controller; and determining a display timing of image data to be displayed on the liquid crystal display panel based on the detected data enable signal. A method characterized by controlling. 7. A liquid crystal display panel having a signal line and a scanning line, a data driver for driving the signal line, a gate driver for driving the scanning line, and controlling a display timing of image data to be displayed on the liquid crystal display panel. A timing controller, wherein the timing controller detects a data enable signal supplied to the timing controller, and a display timing of image data to be displayed on the liquid crystal display panel based on the detected data enable signal. A liquid crystal display device comprising: a timing creation circuit for controlling the timing. 8. A liquid crystal display device according to claim 2, wherein said timing controller is the timing controller according to claim 2.