KR100759971B1 - Liquid crystal display device adapt to an aspect mode of graphic input signal - Google Patents

Abstract

The present invention is a liquid crystal display that adapts to the aspect mode of an input image.

According to the present invention, the timing controller receives a graphic signal applied from the outside, outputs a graphic data signal and a control signal, detects an aspect mode of the graphic signal using a built-in synchronization detector, and detects the aspect mode of the detected aspect mode. A plurality of interlocking scan enable signals are output.

The data driver receives a graphic data signal and outputs a plurality of data signals, and the gate driver outputs at least one of a plurality of gate on signals or a plurality of gate off signals based on a control signal and a plurality of scan enable signals. The liquid crystal display panel is not driven when the gate off signal is received from the gate driver, and receives and displays the data signal when the gate on signal is received from the gate driver.

As a result, by disabling the driving element of the blanking portion of the screen that does not actually need to be driven, it is possible to prevent the black level lifting caused by the driving of the black screen and to reduce power consumption.

LCD, 4: 3, 16: 9, Aspect, Adaptive

Description

Liquid crystal display adapted to the aspect mode of the input image {LIQUID CRYSTAL DISPLAY DEVICE ADAPT TO AN ASPECT MODE OF GRAPHIC INPUT SIGNAL}

1 is a view for explaining a liquid crystal display device adapted to an aspect mode of an input image according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining the above-described gate driver of FIG. 1 in more detail.

3 is a view for explaining a liquid crystal display device adapted to an aspect mode of an input image according to a second embodiment of the present invention.

4 is a diagram for describing a liquid crystal display device adapted to an aspect mode of an input image according to a third exemplary embodiment of the present invention.

FIG. 5 is a diagram for describing a liquid crystal display device adapted to an aspect mode of an input image according to a fourth embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100, 600: timing control unit 200, 700: data driver

300, 800: gate driver 400, 900: LCD panel

310, 320, 330: sub gate module 710, 720, 730: sub data module

150, 650: switching unit

The present invention relates to a liquid crystal display device that adapts to an aspect mode of an input image, and more particularly, to a liquid crystal display device that adapts to an aspect mode of an input image for controlling partial display of the liquid crystal display device. .

In general, when displaying an image in 16: 9 aspect mode on a screen having an aspect ratio of 4: 3 and vice versa, the part to be blanked on the screen is to be processed. Appears.

In this case, when the aspect ratio of the display screen and the aspect mode of the input screen are different, the display screen irrelevant to the input screen among the display screens is monochromatic, preferably black. The black processing of the screen has a problem of causing the screen to be lifted.

In addition, when the aspect ratio of the display screen and the aspect mode of the input screen are different, it is not necessary to drive the driving elements irrelevant to the input screen among the display screens. Occurs.

Accordingly, the technical and problem of the present invention are to solve such a conventional problem, and an object of the present invention is to disable a driving element for driving a blanking portion of a screen that does not need to be driven in a liquid crystal display device. The present invention provides a liquid crystal display device adapted to an aspect mode of an input image for preventing the black level floating due to driving and reducing power consumption.

According to an aspect of the present invention, there is provided a liquid crystal display device adapted to an aspect mode of an input image.

Receives a graphic signal from the outside and outputs a graphic data signal and a control signal, detects the aspect mode of the graphic signal using a built-in synchronization detector, and generates an aspect control signal linked to the detected aspect mode An output timing controller;

A data driver unit receiving the graphic data signal and outputting a plurality of data signals;

A gate driver unit driven full or partial based on the control signal and the aspect control signal to output a gate signal; And

4: 3 or 16: 9 aspect ratio, and in response to the gate signal, a full or partial drive at an aspect ratio of either 4: 3 or 16: 9 to display a data signal provided from the data driver unit The LCD panel is made.

Here, the gate driver unit,

When a high level scan enable signal is input from the timing controller, a plurality of on-type gate signals are provided to the LCD panel to control driving of the LCD panel, and a low level scan enable signal is input. It is preferable to include a plurality of sub-gate modules for providing a plurality of off-type gate signals to the LCD panel to block the drive of the LCD panel.

On the other hand, the liquid crystal display device according to the present invention,

When the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the graphic signal is 4: 3, an aspect control signal is provided to output a scan enable signal through the first path,

When the aspect ratio of the LCD panel is 4: 3, the aspect mode of the graphic signal is 16: 9 further includes a switching unit for receiving an aspect control signal and outputting a scan enable signal through a second path can do.

In addition, the liquid crystal display device adapted to the aspect mode of the input image according to another feature for realizing the above object of the present invention,

Receives a graphic signal from the outside and outputs a graphic data signal and a control signal, detects the aspect mode of the graphic signal using a built-in synchronization detector, and generates an aspect control signal linked to the detected aspect mode An output timing controller;

A data driver unit driven full or partial on the basis of the control signal and the aspect control signal to output a plurality of data signals;

A gate driver unit receiving the control signal and outputting a plurality of gate signals; And

An LCD panel configured to have a 4: 3 or 16: 9 aspect ratio, and displaying a data signal provided from the data driver unit at an aspect ratio of either 4: 3 or 16: 9 in response to the gate signal. It is done by

Here, the data driver unit,

When a high level data enable signal is input from the timing controller, a plurality of on-type data signals are provided to the LCD panel to control driving of the LCD panel, and when a low level data enable signal is input. It is preferable to include a plurality of sub data modules for providing a plurality of off-type data signals to the LCD panel to block the driving of the LCD panel.

On the other hand, the liquid crystal display device according to the present invention,

When the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the graphic signal is 4: 3, an aspect control signal is received to output a data enable signal through a first path, and the LCD panel When the aspect ratio of 4: 3 and the aspect mode of the graphic signal is 16: 9 may further include a switching unit for receiving an aspect control signal and outputting a data enable signal through a second path. .

According to the liquid crystal display device adapted to the aspect mode of the input image, by disabling the drive element of the blanking portion of the screen that does not actually need to drive, it is possible to prevent the black level floating due to the black screen driving Power consumption can be reduced.                     

Then, embodiments will be described so that those skilled in the art can easily implement the present invention.

1 is a view for explaining a liquid crystal display device adapted to an aspect mode of an input image according to a first embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display device adapted to an aspect mode of an input image according to a first embodiment of the present invention includes a timing controller 100, a data driver 200, a gate driver 300, and an LCD panel 400. ).

The timing controller 100 receives a graphic signal applied from an external graphic controller (not shown), a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a main clock MCLK, and receives a graphic data signal composed of RGB ( DATA is output to the data driver 200, and a control signal consisting of the gate clock signal CPV and the vertical start signal STV and a plurality of scan enable signals SEN1 and SEN2 are output to the gate driver 300. .

Here, when the first scan enable signal SEN1 is at a high level, the signal is for driving the display of the LCD panel 400, and when it is at a low level, it is a signal for blocking driving of the LCD panel 400. In addition, the second scan enable signal SEN2 is a signal for driving the display of the LCD panel 400.

In more detail, a sync detector (not shown) of the timing controller 100 detects a mode of an input image input from the outside, that is, whether the input image is a 4: 3 image or a 16: 9 image. The first scan enable signal SEN1 is output to the gate driver 700.                     

For example, when the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the input image is 4: 3, the first scan enable signal SEN1 and the second scan enable signal SEN2 are set to high. When the LCD panel is normally driven to output the level, and the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the input image is 16: 9, the first scan enable signal SEN1 and the second are enabled. The scan enable signal SEN2 is output at a low level and a high level, respectively, to control driving of the LCD panel to adapt to the aspect ratio.

The data driver 200 receives the graphic data signal from the timing controller 100 and outputs a plurality of data signals D1, D2,..., D _m-1 , D _m , which are image signals, to the LCD panel 400. .

The gate driver 300 includes a first sub gate module 310, a second sub gate module 320, and a third sub gate module 330, and includes a gate clock signal CPV provided from the timing controller 100. And a plurality of scan signals (or scan signals) for controlling the display on / off based on the first and second scan enable signals SEN1 and SEN2.

In more detail, when the first sub gate module 310 receives the first scan enable signal SEN1 from the timing controller 100, the first to p-th gate signals G1,..., G _p . Is provided to the LCD panel 400 to control driving of the LCD panel. If the first scan enable signal is a low level (or scan disable signal), the LCD panel 400 may be applied even if a gate clock signal CPV is applied. The power consumption is reduced by shutting off the driving of 400).

When the second sub gate module 320 receives the second scan enable signal SEN2 from the timing controller 100, the second sub gate module 320 includes the (p + 1) to (np) th gate signals G _{p + 1} ,... , G _np ) is provided to the LCD panel 400 to drive the LCD panel 400.

Similar to the operation of the first sub gate module 310 described above, the third sub gate module 330 receives the first scan enable signal SEN1 from the timing controller 100 (n-p). +1) to _n- th gate signals G _{n -p + 1} ,..., G _n are provided to the LCD panel 400 to control the driving of the LCD panel 400, wherein the first scan enable signal If the low level (scan disable signal), even if the gate clock signal (CPV) is applied, the driving of the LCD panel 400 is cut off to reduce power consumption.

Of course, the first to nth gate-on signals G ₁ , ..., G _n are applied to the LCD panel 400 through a sequential line method.

The LCD panel 400 is a screen having a 4: 3 aspect ratio. When the LCD panel 400 receives the low scan first scan enable signal SEN1 from the gate driver 300, the LCD panel 400 is not driven. When the second scan enable signal SEN2 of the high level is received, the driving is driven to partially display the data signal provided from the data driver 200.

As shown, the screen which does not display the graphic signal of the LCD panel 400 is composed of the upper and lower parts, and the displayed screen is located in the middle part, even if using an LCD panel having a 4: 3 aspect ratio. : 9 A graphic image input in aspect mode can be displayed.

In the first embodiment of the present invention, an example of a screen to be displayed is described as being positioned at the middle of the LCD panel as an example. However, a sub gate module that receives a scan enable signal SEN and outputs a gate signal is appropriate. It is obvious that the 16: 9 screen position can be focused on the upper half or the lower half of the LCD panel.

FIG. 2 is a diagram for explaining the above-described gate driver of FIG. 1 in more detail.

1 and 2, the first sub gate module 310 according to the present invention includes a first AND gate 312, a shift register unit 314 including a plurality of shift registers, and a plurality of level shifters. The level shifter unit 316 and the current buffer unit 318 including a plurality of current buffers receive the gate clock signal CPV and the first scan enable signal SEN1 from the timing controller 100. The p-th gate signals G1, ..., Gp are provided to the LCD panel 400 to control driving of the LCD panel.

More specifically, the first AND gate 312 receives the gate clock signal CPV and the first scan enable signal SEN1 from the timing controller 100, and is corrected through an AND operation. Output the signal CPV 'to the shift register. In this case, when the first scan enable signal SEN1 is at a high level, an output signal having a high or low level (for example, '1' or '0') is combined through an AND gate combination with the gate clock signal CPV. Write to the shift register.

The shift register sequentially shifts the data value of the logic input '1' by one line time interval, and the level shifter converts the output logic level of the shift register to the on / off voltage of the gate line and outputs the current buffer. In consideration of the load of the line, the current is amplified and the first to p-th gate signals are output to the LCD panel 400.

In addition, the second sub gate module 320 may include a second AND gate 322, a shift register unit 324 including a plurality of shift registers, a level shifter unit 326 including a plurality of level shifters, and a plurality of current buffers. The current buffer unit 328 is configured to receive the gate clock signal CPV and the second scan enable signal SEN2 from the timing controller 100 to receive p + 1 to np gate signals G _{p + 1} ,. ..., G _np ) is provided to the LCD panel 400 to drive the LCD panel, and a detailed description thereof will be omitted since it is similar to the operation of the first sub gate module.

In addition, since the operation of the third sub gate module 330 according to the present invention is similar to the operation of the first sub gate module described above, a detailed description thereof will be omitted.

In the above description, when the aspect ratio of the LCD panel is 4: 3 screen and the aspect mode is inputted with a 16: 9 image signal, the gate driver is configured to maintain the gate level by keeping the first scan enable signal SEN1 at the gate level. As an example, the CPV, which is a clock signal, is disabled, and the output is performed so that some screens are driven while the gate driver IC is not operated.                     

3 is a view for explaining a liquid crystal display device adapted to an aspect mode of an input image according to a second embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display device adapted to the aspect mode of the input image according to the second exemplary embodiment of the present invention is compared with FIG. 1 as described above, so that the timing controller 100 and the gate driver 300 may be used. It further comprises a switching unit 150 between and.

When the LCD panel 400 has a 4: 3 aspect ratio and the input image is checked to be a 4: 3 aspect mode, the timing controller 100 uses a built-in sync detector (not shown). The switching signal S / W for driving the gate clock signal for driving is output to the switching unit 150, and the LCD panel has a 4: 3 aspect ratio, but the input image is a 16: 9 aspect mode. If checked, the switching signal S / W outputting the gate clock signal adapted to 16: 9 is output to the switching unit 150.

The switching unit 150 receives the gate clock signal CPV and the switching signal S / W applied from the timing controller 100 and outputs the same to the gate driver 300. In this case, the switching for driving a normal LCD panel is performed. When a signal is applied, the signal is output to the first sub gate module 310 so that the entire first to third sub gate modules 310, 320, and 330 are sequentially driven.

In addition, the switching unit 150 controls the output of the gate clock signal only to the second sub gate module 320 when a switching signal for displaying an input image in a 16: 9 aspect mode is applied.                     

In the second embodiment of the present invention, an example of the screen being displayed is described as being located at the middle of the LCD panel as an example. However, the connection between the output path of the gate signal by the switching unit 150 and the sub gate module is properly performed. It will be apparent to those skilled in the art that the position of the 16: 9 screen may be focused on the upper half or the lower half of the LCD panel.

4 is a diagram for describing a liquid crystal display device adapted to an aspect mode of an input image according to a third exemplary embodiment of the present invention.

Referring to FIG. 4, a liquid crystal display device adapted to an aspect mode of an input image according to a third embodiment of the present invention includes a timing controller 600, a data driver 700, a gate driver 800, and an LCD panel 900. ).

The timing controller 600 receives a graphic signal, a vertical sync signal Vsync, a horizontal sync signal Hsync, and a main clock MCLK from an external graphic controller (not shown), and receives the graphic data signal DATA and a load. A signal LOAD, a horizontal start signal STH, and first and second data enable signals DEN1 and DEN2 to the data driver 700, and control signals STV and CPV to the gate driver 300. Output Here, when the first data enable signal DEN1 is at a high level, the signal is for driving the display of the LCD panel 400. When the first data enable signal is at a low level, the display of the LCD panel 400 is displayed. Signal to block.

In more detail, a sync detector (not shown) of the timing controller 600 detects a mode of an input image input from the outside, that is, whether the input image is a 4: 3 image or a 16: 9 image. The first data enable signal DEN1 is then output to the data driver 700. For example, when the aspect ratio of the LCD panel is 16: 9 and the aspect mode of the input image is 16: 9, the first data enable signal and the second scan enable signal are output at high levels, respectively. When the driving of the LCD panel is controlled, the aspect ratio of the LCD panel is 16: 9, and the aspect mode of the input image is 4: 3, the first data enable signal DEN1 and the second data enable are checked. The signal DEN2 is output at a low level and a high level, respectively, to control the driving of the LCD panel to adapt to the aspect ratio.

The data driver 700 includes a first sub data module 710, a second sub data module 720, and a third sub data module 730 to load the graphic data signal DATA from the timing controller 600. A plurality of data signals D1, D2, ... D _{m which} are supplied with the signal LOAD, the horizontal start signal STH and the plurality of data enable signals DEN1, DEN2 to control the display of the image signal on / off. _-1 , D _m ) is output to the LCD panel 400.

More particularly, the first sub-data module 710 when receiving an enable signal (DEN1) first data from the timing controller 600, the first through the q data signal (D1, ..., D _q) Is provided to the LCD panel 900, in which case the driving of the LCD panel is normally controlled when the first data enable signal is at a high level, and the driving of the LCD panel is cut off when the first data enable signal is at a low level. Reduce power consumption.

When the second sub data module 720 receives the second data enable signal DEN2 from the timing controller 600, the second sub data module 720 receives the (p + 1) to (mq) data signals D _{q + 1} ,. , D _mq ) is provided to the LCD panel 900 to drive the LCD panel.

Similar to the operation of the first sub data module 710, when the third sub data module 730 receives the first data enable signal DEN1 from the timing controller 600, the third sub data module 730 may receive (m-q). +1) to _m-th data signals D _{m-q + 1} , ..., D _{m are} provided to the LCD panel 900. When the first data enable signal is at a high level, the LCD panel is normally driven. If the first data enable signal is at a low level, driving of the LCD panel is cut off to reduce power consumption.

The gate driver 800 receives a control signal from the timing controller 600 and outputs a plurality of scan signals (or scan signals) for controlling the on / off of the TFT switching elements positioned on the LCD panel to the LCD panel 900. .

The LCD panel 900 is a 16: 9 display screen and is non-driven when the first data enable signal DEN1 is received from the data driver 700, and the second data enable is enabled from the data driver 700. If the signal DEN2 is provided, it is displayed.

As shown, the non-displayed screen of the LCD panel 900 is composed of the left part and the right part, and the displayed screen is located at the middle part of the LCD panel 900, even when using an LCD panel having a 16: 9 aspect ratio. The graphic image input in the mode can be displayed.

In the above-described third embodiment of the present invention, the display screen is located at the middle of the LCD panel as an example. However, when the sub data module that receives the data enable signal and outputs the data signal is used properly, the display is performed. Obviously, the position of the 4: 3 screen may be concentrated on the left side or the right side of the LCD panel.

5 is a view for explaining a liquid crystal display device adapted to an aspect mode according to a fourth embodiment of the present invention.

Referring to FIG. 5, the liquid crystal display adapting to the aspect mode according to the fourth exemplary embodiment of the present invention is disposed between the timing controller 600 and the data driver 700 in contrast with FIG. 4. It further comprises a switching unit 650.

When the LCD panel 900 has a 16: 9 aspect ratio and the input image is checked to be a 16: 9 aspect mode, the timing controller 600 uses a built-in synchronization detector (not shown). The switching signal S / W for driving the gate clock signal is applied to the switching unit 650, and the LCD panel has a 16: 9 aspect ratio, but the input image is a 4: 3 aspect mode. If checked, the switching signal S / W is output to the switching unit 650 so that a data enable signal adapted to 4: 3 is applied.

The switching unit 650 receives the data signal DATA and the switching signal S / W made of RGB from the timing controller 600 and outputs them to the data driver 700. In this case, switching for driving a normal LCD panel is performed. When a signal is applied, the signal is output to the first sub data module 310 so that the entire first to third sub data modules 710, 720, and 730 are sequentially driven.

In addition, the switching unit 650 controls the data signal DATA to be applied only to the second sub data module 720 when the switching signal for displaying the 4: 3 aspect mode input image is applied.

In the fourth exemplary embodiment of the present invention, the display screen is located at the middle of the LCD panel as an example. However, when the output path of the data by the switching unit 650 and the connection with the sub data module are properly connected, the 4: 3 display is performed. It is obvious that the position of the screen may be concentrated on the left side or the right side of the LCD panel.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

As described above, according to the present invention, the synchronization detection unit of the timing controller detects whether the aspect mode of the input image is a 4: 3 input image or a 16: 9 input image, and the like and adapts the display to the aspect ratio of the LCD panel. By outputting a predetermined signal to the gate driver or the data driver, the full screen of the input image can be displayed even if the aspect ratio of the display screen and the aspect mode of the input image are different.

In addition, when driven in different aspect ratios and aspect modes, a driving signal that is not actually used for a display does not output a driving signal, thereby preventing the screen from being lifted up, and in conjunction with the power Reduced consumption

Claims (16)

Receives a graphic signal from the outside and outputs a graphic data signal and a control signal, detects the aspect mode of the graphic signal using a built-in synchronization detector, and generates an aspect control signal linked to the detected aspect mode An output timing controller; A data driver unit receiving the graphic data signal and outputting a plurality of data signals; A gate driver unit driven full or partial based on the control signal and the aspect control signal to output a gate signal; And 4: 3 or 16: 9 aspect ratio, and in response to the gate signal, a full or partial drive at an aspect ratio of either 4: 3 or 16: 9 to display a data signal provided from the data driver unit LCD panel And a liquid crystal display adapted to an aspect mode of the input image. The method of claim 1, wherein the aspect control signal, When the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the graphic signal is 4: 3, the LCD panel is a scan enable signal for outputting a gate-on signal, When the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the graphic signal is 16: 9, a scan disable signal for outputting a gate-on signal and a scan disable signal for outputting a gate-off signal are provided. A liquid crystal display adapted to an aspect mode of an input video, characterized in that it is a signal. The method of claim 2, wherein the LCD panel, When the gate-off signal is provided, the liquid crystal display adapts to the aspect mode of the input image, which is driven by either normally black driving or normally white driving. The method of claim 1, wherein the gate driver, When a high level scan enable signal is input from the timing controller, a plurality of on-type gate signals are provided to the LCD panel to control driving of the LCD panel, and a low level scan enable signal is input. And a plurality of sub-gate modules for providing a plurality of off-type gate signals to the LCD panel to block driving of the LCD panel. The method of claim 4, wherein the sub gate module, And at least one of an upper half and a lower half of the LCD panel, adapted to the aspect mode of the input image. 6. The liquid crystal display device according to claim 4 or 5, wherein the driving blocking of the LCD panel by the sub gate module does not apply the gate signal. The liquid crystal display device of claim 1, wherein When the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the graphic signal is 4: 3, an aspect control signal is provided to output a scan enable signal through a first path, When the aspect ratio of the LCD panel is 4: 3, the aspect mode of the graphic signal is 16: 9 further includes a switching unit for receiving an aspect control signal and outputting a scan enable signal through a second path And a liquid crystal display adapted to the aspect mode of the input image. The method of claim 7, wherein the gate driver, When the scan enable signal is received through the first path, the driving signal is fully driven. And a plurality of sub-gate modules that are partially driven when the scan enable signal is received through the second path. Receives a graphic signal from the outside and outputs a graphic data signal and a control signal, detects the aspect mode of the graphic signal using a built-in synchronization detector, and generates an aspect control signal linked to the detected aspect mode An output timing controller; A data driver unit driven full or partial on the basis of the control signal and the aspect control signal to output a plurality of data signals; A gate driver unit receiving the control signal and outputting a plurality of gate signals; And An LCD panel configured to have a 4: 3 or 16: 9 aspect ratio, and displaying a data signal provided from the data driver unit at an aspect ratio of either 4: 3 or 16: 9 in response to the gate signal. A liquid crystal display adapted to the aspect mode of the input image. The method of claim 9, wherein the aspect control signal, When the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the graphic signal is 4: 3, the LCD panel is a data enable signal for outputting a data on signal, When the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the graphic signal is 16: 9, a data enable signal for outputting a data on signal and a data disable signal for outputting a gate off signal A liquid crystal display adapted to the aspect mode of an input video. The method of claim 10, wherein the LCD panel, The liquid crystal display adapts to the aspect mode of the input image, characterized in that when the data off signal is provided is driven by either normally black driving or normally white driving. The method of claim 9, wherein the data driver unit, When a high level data enable signal is input from the timing controller, a plurality of on-type data signals are provided to the LCD panel to control driving of the LCD panel, and when a low level data enable signal is input. And a plurality of sub data modules which provide a plurality of off-type data signals to the LCD panel to block driving of the LCD panel. The method of claim 12, wherein the sub data module, And at least one of a left side and a right side of the LCD panel, adapted to the aspect mode of the input image. The liquid crystal display device according to claim 12 or 13, wherein the driving blocking of the LCD panel by the sub data module does not apply the data signal. The liquid crystal display device of claim 9, wherein When the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the graphic signal is 4: 3, an aspect control signal is provided to output a data enable signal through a first path, When the aspect ratio of the LCD panel is 4: 3 and the aspect mode of the graphic signal is 16: 9 further includes a switching unit for receiving an aspect control signal to output a data enable signal through a second path And a liquid crystal display adapted to the aspect mode of the input image. The method of claim 15, wherein the data driver unit, When the data enable signal is received through the first path, the device is fully driven. And a plurality of sub data modules that are partially driven when the data enable signal is received through the second path.

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