JPH08140021A - Drive circuit for liquid crystal display device - Google Patents

Abstract

PURPOSE: To prevent omission of horizontal lines in the case of displaying characters or the like by changing the thinning timing of horizontal scanning lines between odd number fields and even number fields and changing the thinning timing for the respective fields even in non-interlace in a circuit for simply performing the video images of a PAL system to the display device of an NTSC system. CONSTITUTION: A thinning timing circuit 14 operated by the video signals P/L of PAL/NTSC systems being signals for indicating the PAL system generates first thinning timing and a second thinning timing and selectively outputs the first thinning timing and the second thinning timing by field discrimination signals O/E for indicating the odd number fields and the even number fields. By non-interlace discrimination signals NON/INT, the first thinning timing and the second thinning timing are also outputted alternately for the respective fields.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for a liquid crystal display device for displaying an NTSC video signal, and more particularly to an N drive circuit.
The present invention relates to a drive circuit of a liquid crystal display device capable of displaying a video signal other than the TSC system, for example, a PAL system video signal.

[0002]

2. Description of the Related Art Generally, a liquid crystal display device for TV has a T
The active matrix type using FT is mainly used. In the case of the NTSC system, the number of effective scanning lines is about 480 among the 525 horizontal interlaced scanning lines. Therefore, in a liquid crystal display device for TV,
Eighty gate lines are provided, of which 240 odd lines and 240 even lines are driven in an odd field and an even field, respectively. Further, in the simple liquid crystal display device, 240 gate lines are provided, and the gate lines are commonly driven in the odd field and the even field.

On the other hand, in the case of the PAL system, since the number of scanning lines is 625, it cannot be displayed on the liquid crystal display device of the NTSC system as it is, so that the scanning lines are simply thinned out. ing. For example, it is possible to convert to 536 lines by thinning out one scan line for every 7 scan lines, so that it is possible to display on an NTSC liquid crystal display device.

FIG. 4 is a block diagram of a drive circuit in the case of enabling display in both the NTSC system and the PAL system in the above-mentioned simple liquid crystal display device. The liquid crystal panel 1 has 240 gate lines 2 and 2 gate lines 2.
A large number of drain lines 3 that intersect with are provided, and TFTs and pixel electrodes (not shown) are provided at the intersections of the gate lines 2 and the drain lines 3, respectively. The gate line 2 is connected to the gate line driver 4, and the drain line 3 is
It is connected to the drain line driver 5.

The gate line driver 4 is composed of a 240-bit shift register and starts its operation by a start pulse STV applied at the beginning of each field.
The gate lines are sequentially driven by the line clock CKV synchronized with the horizontal synchronizing signal. The drain line driver 5 includes a horizontal shift register 5-1 having a number of bits corresponding to the number of horizontal dots, and R by the horizontal shift register 5-1.
A sample hold circuit 5-2 for sampling G and B video signal voltages, and an analog latch circuit 5-3 for holding the output voltage of the sample hold circuit 5-2 for one line and outputting it to the drain line 3 . The horizontal shift register 5-1 starts its operation by the start pulse STH synchronized with the horizontal synchronizing signal, and the dot clock DC
K sequentially controls the sampling operation of the sample and hold circuit 5-2. Analog latch circuit 5-3
The latch operation is controlled by the line clock CKV, and the voltage latched by the output enable signal OE is supplied to the drain line 3 at a time.

Further, the sync separation circuit 6 uses the video signal VI.
This is a well-known circuit that extracts the horizontal synchronizing signal H and the vertical synchronizing signal V included in DEO. Based on the horizontal synchronizing signal H and the vertical synchronizing signal V, the horizontal timing circuit 7 starts the start pulse STH of the horizontal shift register 5-1. And a dot clock DCK, and the vertical timing circuit 8
The start pulse STV of the gate line driver 4 and the line clock CKV are generated. In addition, PAL / NTS
The C detection circuit 9 detects that the applied video signal VIDEO is NTSC based on the horizontal synchronizing signal H and the vertical synchronizing signal V.
This is a circuit that determines whether the system is the PAL system or not, and the detection output P
/ N is applied to the thinning-out timing circuit 10.

When the detection output P / N indicates the detection output of the PAL system, the thinning-out timing circuit 10 counts the horizontal cycle signal FH output from the vertical timing circuit 8 and outputs one to every seven horizontal scanning lines. Ratio, for example, the thinning-out timing signal C for thinning out the third horizontal scanning line out of seven
Output HGLINE and CHGOE. This thinning-out timing signal CHGLLINE is supplied to the AND gate 11, and in the AND gate 11, the line clock C
KV output is prohibited, while thinning timing signal CH
GOE is applied as the output enable signal OE of the analog latch circuit 5-3, and inhibits the latch voltage output to the drain line 3. The line clock CKV output from the AND gate 11 is applied to the gate line driver 4 and the analog latch circuit 5-3. Therefore, AND
When the output of the line clock CKV in the gate 11 is cut off by one line, the gate line driver 4 stops driving the next gate line, and the analog output of the sample hold circuit 5-2 in one horizontal period is Since the analog latch circuit 5-3 is not latched and the output of the analog latch circuit 5-3 is disabled for one horizontal period, the video signal for one line is thinned out.

When the detection output P / N is the detection output indicating the NTSC system, the thinning-out timing circuit 10 does not operate,
Both the thinning-out timing signals CHGLINE and CHGOE are fixed to the "H" level. Therefore, in this case A
In the ND gate 11, the line clock CKV is not cut off, and the output of the analog latch 5-3 is not prohibited.

As described above, in the liquid crystal display device for the NTSC video signal, the PAL system display can be performed by thinning out the scanning line of the PAL video signal to every seven lines.

[0010]

However, in the liquid crystal display device shown in FIG. 4, the PAL scanning line thinning timing is fixed to the third of the seven scanning lines, so that in each field. The same line will always be thinned out. In this case, for example, when horizontal lines such as characters are displayed as thinned lines, the horizontal lines of characters disappear, which makes it difficult to recognize them as characters. In particular, when used in a device that generates a non-interlaced drive video signal, for example, a PAL system personal computer terminal monitor, the phenomenon in which the horizontal lines of characters disappear is noticeable.

[0011]

The present invention has been made in view of the above-mentioned points, and is a liquid crystal display device for displaying a liquid crystal display device based on the NTSC system on the basis of another system. In the driving circuit of, it operates by a signal indicating that the video signal of the other system is applied,
A video signal of one horizontal scanning line is thinned out at a predetermined horizontal scanning line interval in an odd field of interlace driving and a first timing signal is thinned out and a video signal of one horizontal scanning line is thinned out in a predetermined horizontal scanning line interval at an even field of interlaced driving. A thinning-out timing generating means for generating a second timing signal and alternately generating the first timing signal and the second timing signal for each field during non-interlace driving, and the first and second timing signals. Based on this, the liquid crystal display device is provided with means for inhibiting horizontal scanning line driving and video signal driving.

Further, according to the present invention, a scanning line driver for driving a scanning line of a liquid crystal display device, a signal line driver for driving a signal line of the liquid crystal display device, a vertical synchronizing signal separated from a video signal and a horizontal synchronizing signal. A timing control circuit for generating a plurality of control signals for controlling the timing of the scanning line driver based on a signal and for controlling the timing of the signal line driver, and a horizontal signal according to a signal indicating that a PAL video signal is supplied. A counter for repeatedly counting a predetermined number of horizontal synchronizing clock signals synchronized with the synchronizing signal, and a second value larger than the first value for generating a first timing signal when the count value of the counter is a first value. A decoding circuit for generating a second timing signal at
When a signal indicating that the video signal is interlaced is applied, the first signal is generated according to a signal indicating an odd field.
Timing signal is selected, the second timing signal is selected in accordance with a signal indicating an even field, and when the signal indicating that the video signal is non-interlaced is applied, the first and second timing signals are selected. Timing selection means for alternately selecting and outputting for each field,
According to the first timing signal and the second timing signal output from the timing selecting means, means for inhibiting the operations of the scanning line driver and the signal line driver for one horizontal period is provided.

As a result, the horizontal scanning lines thinned in each field are alternately changed, so that the horizontal lines are not erased.

[0014]

In the present invention, the PA is used instead of the NTSC system.
When the L system video signal is applied, the clock signal synchronized with the horizontal synchronizing signal is repeatedly counted a predetermined number of times, and when the counted value reaches the first value, the first timing signal is output and the second timing signal is output. When the value is reached, the second timing signal is output. When the PAL system video signal is an interlace drive signal, the first timing signal is selected as the thinning-out timing signal of the scanning line based on the signal indicating the odd field, and the second timing signal is selected based on the signal indicating the even field. Since the timing signal is selectively output as the thinning-out timing signal of the scanning lines, the thinning-out scanning lines are different between the odd field and the even field. Further, when the PAL system video signal is a non-interlaced drive signal, the first timing signal and the second timing signal are alternately selected and output for each field, so that the thinned scanning lines are for each field. Will be changed alternately.

Therefore, the same scanning line is not always thinned out, and the horizontal line can be prevented from disappearing.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as the blocks shown in FIG. The difference from FIG. 4 is that the video signal V
A field discriminating circuit 12 for detecting odd and even fields of IDE, a non-interlace discriminating circuit 13 for detecting interlace or non-interlace according to the output of the field discriminating circuit 12, thinning timings of the first timing and the second timing. That is, the thinning-out timing circuit 14 for generating is generated.

The field discriminating circuit 12 discriminates the field by the vertical synchronizing signal and the horizontal synchronizing signal separated by the synchronizing separating circuit 6, and when the horizontal synchronizing signal shifts from the odd field to the even field, it becomes 0. .5H
Displacement is detected and discrimination is performed. In the case of an odd field, the discrimination output E / O becomes L level, and in the case of an even field, the discrimination output E / O becomes H level.

The non-interlace discrimination circuit 13 discriminates non-interlace based on the discrimination output E / O of the field discrimination circuit 12. That is, in the case of interlace, the discrimination output E / O repeats L level and H level for each field, but in the case of non-interlace, the discrimination output E / O is fixed to either L level or H level. Will be done. Therefore, the non-interlace discriminating circuit 13 discriminates non-interlace by detecting that the discrimination output E / O is fixed over a plurality of fields. The discrimination output NON / INT of the non-interlace discrimination circuit 13 becomes L level in the case of interlace and becomes H level in the case of non-interlace.

The thinning timing circuit 14 is a PAL / N
The detection output of the TSC detection circuit 9 and the field discrimination circuit 1
2 discrimination output E / O and non-interlace discrimination output N
Vertical timing circuit 8 controlled by ON / INT
Based on the start pulse STV of the gate line driver 4 and the horizontal cycle signal FH output from the
It is a circuit that generates a first timing and a second timing for thinning out one horizontal scanning line for each line. Specifically, the first timing is the timing of thinning out the third horizontal scanning line of the seven, and the second timing is the timing of thinning the sixth horizontal scanning line of the seven. Timing signals CHGLINE and CHGOE are output according to the first timing and the second timing.

This thinning-out timing signal CHGLLINE
Is supplied to the AND gate 11, and in the AND gate 11, the output of the line clock CKV is prohibited,
The thinning-out timing signal CHGOE is applied as the output enable signal OE of the analog latch circuit 5-3, and inhibits the latch voltage output to the drain line 3.

FIG. 2 shows a concrete circuit diagram of the thinning-out timing circuit 14. In FIG. 2, a 7-ary counter 15 is a counter that repeatedly counts horizontal scanning lines in units of 7 lines, and is reset by a start pulse STV of the gate line driver 4 output for each field, and PA
Detection output P / N output from the L / NTSC detection circuit 9
The horizontal period signal FH applied through the AND gate 16 controlled by is counted. The decoder 17 is the first
To generate the decimation timing, a 7-ary counter 1
The decoder 18 detects the count value "3" of 5
Detects the count value "6" of the 7-ary counter 15 in order to generate the second thinning timing. The decode output of each decoder 17 and 18 is the switching gate 1
9 is applied. This switching gate 19 is J-KFF
Switching is controlled by the output of 20.

The start pulse STV is applied to the clock input T of the J-KFF 20, and the outputs of the NAND gates 21 and 22 are applied to the J and K inputs, respectively. N
A non-interlace discrimination output NON / INT inversion signal and a field discrimination signal E are input to the AND gate 21.
/ O is applied. On the other hand, to the input of the NAND gate 22, the inverted signal of the non-interlaced discrimination output NON / INT and the inverted signal of the field discrimination signal E / O are applied. The output of the switching gate 19 is the timing signal CH.
It is output as GOE and is applied to the D-FF 23 that uses the horizontal cycle signal FH as a clock. D-FF23
Is output as the timing signal CHGLLINE.

In FIG. 2, when the PAL / NTSC detection signal P / N is L level, that is, when the video signal is NTSC, the output of the AND gate 16 is L level.
The 7-ary counter 15 does not count, and the decoder 17
The outputs of 18 and 18 both become L level. In this case, the output of the switching gate 19, that is, the timing signal CHGOE becomes L level, and the analog latch circuit 5
The analog output of -3 is enabled. Also,
Since an inverted signal of the timing signal is applied to the D-FF 23, its output, that is, the timing signal CHGLIN
Since E becomes H level, the AND gate 11 always outputs the line clock CKV. Therefore, in this case, the thinning of the line clock CKV and the thinning of the output of the analog latch circuit 5-3 are not performed, and the normal display operation is performed.

Next, in FIG. 2, when the PAL / NTSC detection signal P / N is at H level, that is, when the video signal is PAL, the horizontal period signal FH is output from the output of the AND gate 16, so that the 7-ary counter is used. Reference numeral 15 counts the horizontal cycle signal FH. Therefore, the count value of the 7-ary counter 15 is "3".
Then, the output of the decoder 17 becomes H level, and when the count value becomes "6", the output of the decoder 18 becomes H level. The outputs of the decoders 17 and 18 are the switching gate 1
It is switched and output by 9.

This state will be described with reference to the timing chart of FIG. In the period (a) shown in FIG. 3, the video signal is interlaced, and the non-interlaced detection signal NON / INT is at L level. At this time, since an inverted signal of the non-interlace detection signal NON / INT, that is, a signal of H level is applied to one input of each of the NAND gates 21 and 22,
A field discrimination signal E / O is input to the J input of the J-KFF20.
The inverted signal of is applied through the NAND gate 21,
The field discrimination signal E / O is input to the NAND gate 2
2 is applied.

Therefore, in the case of an odd field (indicated by O), the field discrimination signal E / O is at the L level, so the J input is at the H level signal and the K input is at the L level signal. Is applied, the Q output of the J-KFF 20 becomes H level. As a result, the switching gate 19 selects the output of the decoder 17. That is, the first thinning timing is selected in the odd field. On the other hand, in the case of an even field (indicated by E), the field discrimination signal O / E is at H level,
An L level signal is applied to the J input and an H level signal is applied to the K input, and the Q output of the J-KFF 20 becomes the L level. As a result, the switching gate 19 causes the decoder 18 to
Select the output of That is, in the even field,
The second thinning-out timing will be selected.

Therefore, in the odd field, the third horizontal scanning line is thinned out every seven horizontal scanning lines, and in the even field, the sixth horizontal scanning line is thinned out every seven horizontal scanning lines. Become.

Next, during the period shown in FIG. 3B, the video signal is non-interlaced, and the non-interlaced discrimination signal NON / INT is at the H level. At this time, the non-interlace discrimination signal NON / IN is input to one input of each of the NAND gates 21 and 22.
Since an inverted signal of T, that is, an L level signal is applied, an H level signal is applied to both the J input and the K input. In this state, the J-KFF 20 operates to invert every time the start pulse STV is applied, so
The output is H level and L in synchronization with the start pulse STV.
A signal that repeats the level. As a result, the switching gate 19 switches and outputs the outputs of the decoders 17 and 18 for each field. That is, even in the case of non-interlace, the thinning-out timing is switched between the third scanning line and the sixth scanning line among the seven scanning lines for each field.

FIG. 3 shows a thinning operation in an odd field of interlaced driving. In this field, the output of the timing decoder 18 is output as the timing signal CHGOE. The horizontal line clock CKV is generated in synchronization with the rising of the horizontal cycle signal FH. When the 7-ary counter 15 counts the horizontal cycle signal FH and becomes "1", the video signal in the horizontal period of n lines is held by the shift register 5-1 for one line in the sample hold circuit 5-2. It Then, when the count value of the 7-ary counter 15 becomes "2", A
In response to the line clock CKV output from the ND gate 11, the analog latch circuit 5-3 latches the analog signal output from the sample hold circuit 5-2 to L level.
Output to the drain line 3 of the CD panel. Since the gate line driver 4 drives the gate line of the next line by this line clock CKV, the image signal of n lines is supplied to the display pixel of 1 line connected to the gate line and displayed. Further, in the horizontal period of the count value “2”, the sample hold circuit 5-2 holds the video signal of the (n + 1) th line.

Next, the count value of the 7-ary counter 15 is "3".
Then, the video signal of the (n + 1) th line held in the sample hold circuit 5-2 is latched in the analog latch circuit 5-3 by the line clock CKV. However, in this case, the decoder 17 detects the count value "3", its output becomes H level and is output to the timing signal CHGOE, so that the analog latch circuit 5-3 becomes disabled and the video signal of the (n + 1) th line is , No output to the drain line. Therefore, even if the gate line driver 4 drives the next gate line by the line clock CKV, the pixel connected to the gate line has n +
The video signal of 1 is not supplied. In the horizontal period of the count value “3”, the sample hold circuit 5-2 outputs n +
Video signals of two lines are held.

Next, the output of the decoder 17 is the D-FF2.
Since it is output to the timing signal CHGLINE with a delay of 1/2 cycle of the horizontal cycle signal FH by 3, the line clock CKV output when the count value of the 7-ary counter 15 becomes "4" is cut off by the AND gate 11. It Therefore, the analog latch circuit 5-3 does not perform the latch operation, and the video signal of the (n + 1) th line remains held. Further, the gate line driver 4 does not operate, and the gate line selected in the previous horizontal period is in a driven state. Further, since the timing signal CHGOE becomes L level during the period of the count value “4”, the video signal of the (n + 1) th line held in the analog latch 5-3 is supplied to the drain line to the gate line in the driving state. Displayed on connected pixels. During the horizontal period of the count value “4”, the sample hold circuit 5-2 holds the video signal of the n + 3 line.

Next, the count value of the 7-ary counter 15 is "5".
Then, the timing signal CHGLLINE is at the H level, so that the line clock CKV is output via the AND gate 11. This line clock CK
Due to V, the analog latch circuit 5-3 latches the video signal of the n + 3 line held in the sample hold circuit 5-2 and outputs it to the drain line 3. Further, since the gate line driver 4 selects the next gate line by the line clock CKV, the image signal of the n + 3 line is supplied to the pixel connected to the gate line and displayed.

As can be seen from the above operation, the video signal of the horizontal scanning line whose count value of the 7-ary counter 15 is "3" is thinned out.

[0034]

As described above, according to the present invention, the NTSC
In order to display the PAL system image on the system display device,
When thinning horizontal scanning lines at a predetermined interval, changing the timing of thinning horizontal scanning lines in odd and even fields prevents horizontal lines from being lost when displaying characters, etc. It can be performed. Also in the case of non-interlace, it is possible to prevent the video displayed on a specific line from being lost because the thinning timing changes for each field.

[0035]

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram specifically showing a part of the block diagram shown in FIG.

FIG. 3 is a timing diagram showing the operation of FIG.

FIG. 4 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 liquid crystal panel 2 gate line 3 drain line 4 gate line driver 5 drain line driver 6 sync separation circuit 7 horizontal timing circuit 8 vertical timing circuit 9 PAL / NTSC detection circuit 12 field discrimination circuit 13 non-interlace discrimination circuit 14 thinning timing circuit 15 7 Binary counter 17, 18 Decoder 19 Switching gate 20 J-KFF 23 D-FF

Claims (2)

[Claims] 1. A driving circuit of a liquid crystal display device for displaying a liquid crystal display device based on the NTSC system on the basis of a signal indicating that the video signal of the other system is applied. The first timing signal for thinning the video signal of one horizontal scanning line at a predetermined horizontal scanning line interval during odd fields of interlace driving and the video of one horizontal scanning line at a predetermined horizontal scanning line interval during even fields of interlace driving A second timing signal for thinning a signal is generated, and a thinning timing generating means for alternately generating the first timing signal and the second timing signal for each field during non-interlaced driving, and the first and second A means for inhibiting horizontal scanning line driving and video signal driving of the liquid crystal display device based on the timing signal is provided. Driving circuit of the liquid crystal display device according to claim. 2. A scanning line driver for driving a scanning line of a liquid crystal display device, a signal line driver for driving a signal line of the liquid crystal display device, and a vertical synchronizing signal and a horizontal synchronizing signal separated from a video signal. A timing control circuit that generates a plurality of control signals that performs timing control of the scanning line driver and timing control of the signal line driver, and synchronizes with a horizontal synchronization signal in accordance with a signal indicating that a PAL video signal is supplied. A counter for repeatedly counting a predetermined number of horizontal synchronization clock signals, a first timing signal when the count value of the counter is a first value, and a second timing signal when the count value is a second value larger than the first value. And a decoding circuit for generating the timing signal, and a signal indicating an odd field when the signal indicating that the video signal is interlaced is applied. According to the first timing signal, the second timing signal according to a signal indicating an even field, and the first and second signals when a signal indicating that the video signal is non-interlaced is applied. Timing selecting means for alternately selecting and outputting the timing signal for each field, and the operation of the scanning line driver and the signal line driver according to the first timing signal and the second timing signal output from the timing selecting means. A driving circuit for a liquid crystal display device, comprising: means for inhibiting a horizontal period.