JPS6365494A - Memorizing liquid crystal display device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display device of a liquid crystal display panel using a memory liquid crystal.

[Prior Art] Conventionally, liquid crystals having memory properties, such as ferroelectric liquid crystals (specifically, decyloxybenzyritene-p'-amino-2-
Driving a liquid crystal display panel (hereinafter referred to as a ferroelectric liquid crystal display panel) using methylbutyl cinnamate (DOBAMBC), hexyloxybenzylidene-p'-amino-2-chloropropyl cinnamate (HOBACPC), etc. is the first step. This was done using a circuit like the one shown in the figure, as explained below.

In FIG. 3, a vertical synchronizing signal VD and a horizontal synchronizing signal Hf) which are synchronously separated from the video signal are input to the scanning IIJ shift register 3 of the scanning N-pole drive circuit 2 of the ferroelectric liquid crystal display panel 1, and the VD is used as a signal to reset the scanning shift register 3, and HD is used as a shift timing signal to sequentially shift and select scanning electrodes one by one. At this time, the scanning driver 4 inputs a shift clock pulse to the scanning electrodes in synchronization with the HD, thereby selecting each scanning electrode. Further, the signal-side shift register 6 of the signal electrode drive circuit 5 receives video data converted into a digital signal 5 for one horizontal period (IH).
The line memory 7 and the signal side driver 8 input the horizontal synchronizing signal) (horizontal synchronizing signal) (Sequentially shifted one line at a time in synchronization with D and output it. Scan electrode drive circuit 2 and signal electrode drive circuit 5 are controlled in synchronization by a horizontal synchronizing signal HD, and images are displayed by sequentially scanning one line at a time from the top to the bottom of the screen.

[Problem that the invention seeks to solve] However,
Liquid crystals with memory properties, such as ferroelectric liquid crystals, have a limited response to electric fields, so if the number of scanning electrodes is large, for example 400 or more, the response to 30 frames per second, which is the limit for human visual response. More than 1 mu (80 in IH time)
This poses a display problem because it cannot be driven at a speed of less than 30 frames per second (μsec or less), that is, at a speed where the scanning state is easily recognized visually.

[Means and effects for solving the problems] The present invention has been made in view of the above circumstances, and includes a video signal output circuit,
A memory liquid crystal display panel, a common address designating means for designating the address of the scan electrode of the memory liquid crystal display panel, a scan electrode drive circuit for driving the scan electrode designated by the common address designation means, and the video signal. It is composed of a signal electrode drive circuit to which a video signal is supplied from the output circuit, a control means for controlling the scanning electrode drive circuit, the signal electrode drive circuit, and a common address designation means. When the screen changes, it is configured to scan only a portion of the screen, rather than scanning the entire screen for each frame, which increases the apparent response speed of the display and significantly reduces power consumption. be.

[Example] Hereinafter, the present invention will be explained in detail based on the drawings.

In FIG. 1, the video signal output circuit 21 is composed of, for example, a television signal receiving circuit, and includes a horizontal synchronizing signal φh,
Outputs analog video signal VD. The output analog video signal VD is converted into a digital signal by an A-D converter 22 and sent to a CPU (central processing unit) 23 as video data.
Output for. The CPU 23 outputs the video data for each frame to a VRAM (video RAM) 24 having a storage capacity for two frames, and temporarily stores the video data.

Further, the CPU 23 outputs a synchronization signal φ2 created based on the horizontal synchronization signal φh output from the video signal output circuit to the switching circuit 25 of the ferroelectric liquid crystal display device. ROM
26, the designation circuit 27 is a so-called coincidence detection circuit, and V
The video data for one frame temporarily stored in the RAM 24 and the video data for one frame that is next manually inputted to the CPU 23 are sequentially compared in line, and a discrepancy signal P is detected by CPU.
This is output to U23. The switching circuit 25 is C
The serial data SD output from the PU 23 is separated into video data and common address data by a selection switch 28, and each signal electrode drive circuit 29. It is output to the scan electrode drive circuit 30. The signal electrode drive circuit 29 has a signal side shift register 30. line memory 3
1. Consisting of a signal electrode driver 32, the input video data is sequentially shifted one line (IH) at a time. The scan electrode drive circuit 32 includes an address data latch 33.
Decoder 34. Consisting of a scanning electrode driver 35,
The common address data latched in the address data latch 33 is decoded by the decoder 34, and the scan electrode driver 35 drives the scan electrode of that address.

Next, the operation of the embodiment configured as described above will be explained with reference to the time chart of FIG. 2 and the flow chart of FIG. 3.

Video signal output circuit (e.g. television signal receiving circuit)
The video signal output from 21 is converted into a digital signal by the A-D converter 22 and output to the CPU 23 as video data. VRAM with
24 alternately and temporarily stored. The common address designation circuit 26 then compares the temporarily stored video data of the previous frame with the video data of the next input frame line by line according to the flowchart in FIG. Detects the address and outputs a mismatch signal P. The CPU 23 detects how many times the mismatch signal P is issued, reads out address data corresponding to that number from the ROM 26, and reads the serial data SD which is serially added to the video data of the corresponding address among the video data of the next frame stored in the VRAM 24. Output. This serial data S
D indicates that the common address data output during the rising time of the horizontal synchronizing signal φh is added to the front of the video signal and output as shown in the time chart of FIG.

The switching circuit 25 switches the selection switch 28 in synchronization with the rise and fall of the synchronization signal φ2 output from the CPU 23, and distributes and outputs the video data to the signal drive circuit 29 and the common address data to the scan electrode drive circuit 32. By operating in this manner, synchronization between video data and common address data is ensured. The changed address data of the scan electrode is input to the address data latch 33 and then sent to the decoder 34.
The scan electrode of that address is scanned by the driver 35, and only the image of that common address data changes. For example, the video data of the previous frame and the video data of the next frame are common address data n.
(0≦n≦400), the CPU 23 outputs only the video data of the next frame corresponding to the common address data n, and outputs the image of the nth scanning electrode of the ferroelectric liquid crystal display panel 21. It changes the

The ferroelectric liquid crystal panel can retain video data even if the signal line on the drive circuit side is cut due to its memory characteristics. , it is possible to change only a part of the image, so even if the operation is performed as described above, no problem will occur on the display.

In the above embodiment, the video data and common address data are output as serial data SD to synchronize them, but if synchronization can be achieved, the video data and common address data can be directly signaled separately. It can also be output to an electrode drive circuit and a scanning electrode drive circuit. Further, although the above embodiments show the case where a ferroelectric liquid crystal display panel is used, the invention is not limited to this, and any liquid crystal display panel having memory properties may be used.
The present invention is applicable.

[Effects of the Invention] Since the structure is configured as described above, if only a part of the screen changes for each screen of the memory liquid crystal display panel, only that part of the screen is scanned and changed, and then the whole screen is scanned. Since this is not performed, the display response speed can be apparently increased, and power consumption can also be significantly reduced.

[Brief explanation of the drawing]

Fig. 1 is a block circuit diagram for explaining the driving of a ferroelectric liquid crystal display panel according to an embodiment of the present invention, Fig. 2 is a time chart of the embodiment of the present invention, and Fig. 3 is a common address data designation circuit. A flowchart showing the operation, and FIG. 4 is a block circuit diagram for explaining the conventional drive. 20 --- Ferroelectric liquid crystal display panel 21 --- Video signal output circuit 22 --- A-D converter 23 --- CPU 24 --- VRAM 27-
--- Common address designation circuit 29 --- One signal electrode drive circuit 32 --- Scanning electrode drive circuit Patent applicant Canon Co., Ltd. Figure 73

Claims (2)

[Claims] (1) A video signal output circuit that outputs a video signal, a memory liquid crystal display panel, a common address designation means for designating the address of the scanning electrode of the memory liquid crystal display panel, and a memory address designation means designated by the common address designation means. A scan electrode drive circuit that drives a scan electrode, a signal electrode drive circuit to which a video signal from the video signal output circuit is supplied, and a control means that controls the scan electrode drive circuit, the signal electrode drive circuit, and the common address designation means. 1. A storage liquid crystal display device comprising: a memory liquid crystal display device, characterized in that only an image of a scanning electrode portion designated by the common address designation means can be changed. (2) The memory liquid crystal display device according to claim 1, wherein the memory liquid crystal display panel is a ferroelectric liquid crystal display panel.