JPH09219840A - Video display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the degradation of vertical resolution by a simple circuit without using a frame memory and to suppress moire by modulating a vertical deflection current once in two lines after performing double density conversion and shifting the position of a scanning line. SOLUTION: Video signals are inputted to a synchronizing separator circuit 1 and horizontal and vertical synchronizing signals are outputted. The vertical synchronizing signals of the synchronizing separator circuit 1 are inputted to a modulation circuit 10 through a vertical deflection circuit 4. The output signals of a double multiplication circuit 2 are inputted there, a modulation waveform for modulating the vertical deflection current once in two lines after the double density conversion is prepared and the vertical deflection current is modulated by the waveform. Thus, by scanning the position for which the (n+1)-th line of a first field after the double density conversion is shifted upwards from the middle of an (n)-th line and an (n+2)-th line, the (n+1)-th line of the first field is prevented from being overlapped with the (n)-th line of a second field. Thus, the degradation of the vertical resolution is prevented even in the case of performing the double density conversion without using the frame memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video display device such as a television receiver, a monitor receiver and a display receiver.

[0002]

2. Description of the Related Art In recent years, many signal processing techniques have been used in order to improve the image quality of current television signals. One of them is a double-density conversion in which the horizontal frequency of the input signal is doubled and scanning is performed. By performing double-density scanning, the response of the high-voltage stabilizing circuit of the receiver can be speeded up, and the high-voltage dynamic stability can be improved. Further, in the receiver corresponding to several kinds of synchronizing signal frequencies, it is not necessary to switch the deflection circuit, and the circuit scale can be reduced.

An example of the above-mentioned double-density conversion is disclosed in Japanese Patent Laid-Open No. 62-256.
597. An image display device including a conventional double-density conversion device will be described below.

FIG. 4 shows a block diagram of a conventional double-density converter. In FIG. 4, reference numeral 1 is a sync separation circuit that separates a horizontal sync signal and a vertical sync signal from an input video signal, 2 is a doubler circuit that outputs a signal twice the frequency of the horizontal sync signal, and 3 is 2 A horizontal deflection circuit that receives the output of the multiplication output circuit 2 and outputs a horizontal deflection current, 4 is a vertical deflection circuit that outputs a vertical deflection current from the vertical synchronization signal that is the output of the sync separation circuit 1, and 5 is a horizontal synchronization circuit. First from the signal
6 is a PLL circuit for outputting the clock signal, 6 is a frequency dividing circuit for dividing the first clock signal by 2 and outputting a second clock signal, and 7 is an analog-digital circuit for the input video signal with the second clock. A / D conversion circuit for conversion, 8 is A / D
The output of the conversion circuit 7 is written and held at the second clock,
A line memory that reads out the data held by the first clock, and 9 is a D / A conversion circuit that converts a digital signal into an analog signal.

The operation of the double-density converter having the above-described structure will be described below.

First, a video signal is input to the sync separation circuit 1 and a horizontal sync signal and a vertical sync signal are separated from the video signal. Next, the horizontal synchronizing signal is input to the doubling circuit 2 and a signal having a doubled frequency is output. For example, when an NTSC system signal is input, the horizontal sync signal output from the sync separation circuit has a frequency of 15.73 kHz, and the output of the frequency doubler circuit 2 is 31.46 kHz, which is double that frequency. A signal having a period of 31.46 kHz is input to the horizontal deflection circuit 3, and a horizontal deflection current for driving the horizontal deflection coil of the CRT is output by this signal. The vertical deflection signal which is the other output of the sync separation circuit 1 is input to the vertical deflection circuit 4, and a vertical deflection current for driving the vertical deflection coil of the CRT is output. With the above operation, horizontal deflection is performed at a frequency double that of the input signal.

Along with the above operation, it is necessary to output a video signal accordingly. The operation will be described below.

The horizontal sync signal of the sync separation circuit 1 is input to the PLL circuit 5, and the color carrier (hereinafter referred to as fs) of the input video signal is input.
A frequency signal 8fsc that is eight times that of c) is output. In the case of the NTSC system, fsc is 3.58MHz and 8fsc is 28.6MHz. PLL
An example of the circuit 5 is shown in FIG. In FIG. 6, 12 is a phase comparison circuit that compares the phases of two input signals and outputs the comparison result as a + signal and a − signal, 13 is an integration circuit that integrates the output of the phase comparison circuit 12, and 14 is An oscillation circuit that oscillates a high frequency signal when the output signal of the integration circuit 13 is an input signal and a low frequency signal when the input signal is low. Reference numeral 15 counts the output signal of the oscillation circuit 14 and becomes a constant count value. It is a counter that sometimes outputs a signal. The NTSC system will be described as an example. In the NTSC system, 8 fsc is 1820 counts and is synchronized with one horizontal cycle.
Now, it is assumed that the oscillator circuit 13 is oscillating at a frequency slightly higher than 8 fsc. When the counter 15 is operated at 8 fsc with a frequency shift and 1820 is counted, a pulse signal is output and the pulse signal is input to the phase comparison circuit 12. The phase comparison circuit 12 compares the phase of the input pulse signal with the phase of the other input horizontal synchronizing signal, but since the counter 15 is operated at a frequency higher than 8 fsc, the pulse signal becomes a signal with a phase earlier than the horizontal synchronizing signal. The output of the phase comparison circuit 12 outputs a negative signal. The integrating circuit 13 receives a negative signal and the output signal becomes small. Oscillation circuit 1
No.4, the input signal becomes small and the output signal frequency goes down 8f
Approach sc. If it is higher than 8fsc, perform the above operation and
When it is lower than sc, the output of the phase comparison circuit 11 becomes large. The above operation is repeated and the output frequency of the oscillation circuit 14 is
It becomes 8fs.

The above is the operation of the PLL circuit 5 in FIG. 6, whereby the PLL circuit 5 outputs the first clock signal having a frequency of 8 fsc. The first clock signal is input to the frequency dividing circuit 6, and the frequency dividing circuit 6 outputs a second clock signal of 4fsc, which is half the frequency of the input signal.
The input video signal is converted from an analog signal to a digital signal by the A / D conversion circuit 7 with the second clock signal.
The video signal converted into a digital signal is input to the line memory 8. The line memory 8 can hold data of one horizontal period and can write and read data asynchronously. The signal input to the line memory 8 is written in the line memory 8 at the second clock and read at the first clock. As a result, the same data is read twice. The read data is converted into an analog video signal by the D / A conversion circuit 9 and input to the CRT.

The CRT is driven at a horizontal deflection frequency that is twice as high as the input signal described above, and two lines of video signals for one line are output.

FIG. 5 shows the scanning situation after the double-density conversion. The line of the first field before double conversion is m, m +
, M + 2, ... (not shown), and the lines of the first field after the double-density conversion are n, n + 1, n + 2 ,.

By scanning the m, m + 1, m + 2, ... Lines, n, n + 1, n + 2 ,. Nth
The line scans the same position as the m-th line, and the n + 1-th line scans between the m-th line and the m + 1-th line, that is, the same position as the m-th line of the second field before the double-density conversion.

After the double density conversion, the nth line of the first field is scanned, and then the same video signal as the nth line is scanned on the (n + 1) th line between the nth line and the (n + 2) th line after the double density conversion. The nth line of the second field scans the position of the (n + 1) th line of the first field.

[0014]

However, in the conventional configuration, the video signal for scanning the (n + 1) th line of the first field and the video signal for scanning the nth line of the second field after the double-density conversion overlap with each other. There is a problem that the vertical resolution is deteriorated.

In view of the above problems, the present invention provides a video display device equipped with a double-density conversion device capable of preventing deterioration of vertical resolution by adding a simple circuit.

[0016]

In order to solve the above-mentioned problems, the video display device of the present invention modulates the output signal of the vertical deflection circuit in the modulation circuit at a horizontal frequency that is doubled for each line, and the first field is generated. By changing the scanning position of the (n + 1) th line without changing the scanning position of the nth line, it is possible to prevent coincidence with the scanning position of the nth line of the second field and maintain the vertical resolution. Also scan line and C
It is possible to suppress moire caused by interference of the RT shadow mask.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention relates to a video display device having a double-density conversion function for scanning by doubling the horizontal frequency of a video input signal, and the scanning lines of the first field and the second field forming one frame. Is characterized in that the scanning position is shifted so as not to overlap the scanning position, and the present invention is a sync separation circuit for separating a vertical sync signal and a horizontal sync signal from the video signal by inputting the video signal, A doubler circuit that receives the horizontal sync signal output from the sync separation circuit and generates a signal having a frequency twice that of the horizontal sync signal, and a horizontal deflector circuit that receives the output signal of the doubler circuit and outputs a horizontal deflection current. A vertical deflection circuit that receives a vertical synchronization signal output from the sync separation circuit as an input and outputs a vertical deflection current; and outputs the vertical deflection circuit and the output from the sync separation circuit as an input. A modulation circuit that modulates and outputs the output signal of, a PLL circuit that inputs the horizontal synchronization signal that is the output of the synchronization separation circuit, and outputs a first clock signal from the frequency of the horizontal synchronization signal, and the first clock A frequency dividing circuit for dividing the signal by 2 and outputting a second clock signal,
An A / D conversion circuit that performs analog-to-digital conversion with the second clock signal, and a digital video signal output from the A / D conversion circuit as an input, the digital video signal is taken in with the second clock, and the first clock It is composed of a line memory that outputs the digital video signal captured in step S1 and a D / A conversion circuit that converts the digital signal into an analog signal. The output signal of the vertical deflection circuit is modulated line by line. The scanning position of the n-th line of the field is not changed, and the scanning position of the (n + 1) -th line is shifted to obtain the second
The vertical resolution is maintained by preventing coincidence with the scanning position of the nth line of the field.

According to the present invention, a modulation amount variable circuit for changing the modulation amount of the modulation circuit is provided in the above-mentioned structure to suppress the moire generated by the interference between the scanning line and the shadow mask of the CRT. It makes it possible.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (Embodiment 1) FIG. 1 shows a double-density conversion apparatus of a video display apparatus according to the present embodiment.

In FIG. 1, a sync separation circuit 1 separates a horizontal sync signal and a vertical sync signal from an input video signal, and a doubling circuit 2 outputs a signal twice the frequency of the horizontal sync signal. The horizontal deflection circuit 3 has two
The horizontal deflection current is output from the output of the multiplication output circuit 2, the vertical deflection circuit 4 outputs the vertical deflection current from the vertical synchronization signal which is the output of the synchronization separation circuit 1, and the PLL circuit 5 is horizontal. The first clock signal is output from the synchronizing signal, the frequency dividing circuit 6 divides the first clock signal by two to output the second clock signal, and the A / D conversion circuit 7 is input. Is used for analog-to-digital conversion of the video signal of the second clock, and the line memory 8 writes and holds the output of the A / D conversion circuit 7 at the second clock and holds the data at the first clock. The D / A conversion circuit 9 performs digital-analog conversion, and the modulation circuit 10 modulates the output signal of the vertical deflection circuit 4 with the output signal of the frequency doubler circuit 2.

Next, the operation will be described. First, a video signal is input to the sync separation circuit 1, and the sync separation circuit 1 outputs a horizontal sync signal and a vertical sync signal. The horizontal synchronizing signal is input to the doubler circuit 2 and the horizontal deflection current is output from the horizontal deflection circuit 3 as in the conventional example. Further, the horizontal synchronizing signal output from the sync separation circuit 1 is input to the PLL circuit to generate the first clock signal, the frequency dividing circuit 6 generates the second clock signal, and the A / D converter 7, line The operation of outputting a signal from the memory 8 and outputting a signal from the D / A conversion circuit 9 is the same as in the conventional example. The vertical synchronizing signal output from the sync separation circuit 1 is input to the vertical deflection circuit 4. The output of the vertical deflection circuit 4 is input to the modulation circuit 10. The modulation circuit 10 receives the output signal of the frequency doubler circuit 2 and is subjected to double-density conversion to generate a modulation waveform for modulating the vertical deflection current once in two lines, and the waveform is used to modulate the vertical deflection current. The vertical deflection current after modulation has the waveform shown in FIG. By modulating the vertical deflection current, as shown in FIG. 2, the n + 1th line of the first field after the double-density conversion is scanned at a position shifted upward from the middle of the nth line and the n + 2th line. It prevents the (n + 1) th line of one field from overlapping the (n) th line of the second field.

According to the above-described embodiment, the vertical deflection signal is modulated once every two lines to shift the position of the scanning line, so that the double-density conversion can be performed while maintaining the vertical resolution without using the frame memory. Since the horizontal frequency is doubled, the high pressure dynamic stability of the CRT can be improved.

(Embodiment 2) FIG. 3 shows a double-density converter for a video display apparatus according to the present embodiment, which suppresses moire caused by interference between a scanning line and a shadow mask of a CRT.

In FIG. 3, a sync separation circuit 1 separates a horizontal sync signal and a vertical sync signal from an input video signal, and a doubling circuit 2 outputs a signal twice the frequency of the horizontal sync signal. The horizontal deflection circuit 3 has two
A horizontal deflection current is output from the output of the multiplication output circuit 2, and a vertical deflection circuit 4 outputs a vertical deflection current from the vertical synchronization signal which is the output of the synchronization separation circuit 1.
The PLL circuit 5 outputs the first clock signal from the horizontal synchronizing signal, and the frequency dividing circuit 6 divides the first clock signal by 2 and outputs the second clock signal.
The A / D conversion circuit 7 performs analog-digital conversion of the input video signal at the second clock, and the line memory 8 writes and holds the output of the A / D conversion circuit 7 at the second clock, The data held by the clock is read out, the D / A conversion circuit 9 performs digital-analog conversion, and the modulation circuit 10 operates as a doubling circuit 2
Is used to modulate the output signal of the vertical deflection circuit 4, and the modulation amount adjustment circuit 11 sets the modulation amount in the modulation circuit 10 arbitrarily.

Next, the operation will be described. As in the first embodiment, the vertical deflection signal is modulated and the scanning line position is shifted once every two lines after the double-density conversion. First after double-dense conversion
N + th line between the nth line and the n + 2th line of the field
One line is scanned, but the modulation amount adjusting circuit 10
The scanning position of the line is adjusted to an arbitrary position between the nth line and the (n + 2) th line.

According to the present embodiment described above, the modulation amount for modulating the vertical deflection current is set, and the modulation amount is adjusted to suppress the moire due to the shadow mask of the scanning line and the CRT. The scanning position can be determined.

Although the PLL circuit 5 for outputting the first clock and the doubler circuit 2 are separated in the first and second embodiments,
It goes without saying that the frequency doubler circuit 2 can be included in the PLL circuit 5.

[0028]

As described above, according to the present invention, the vertical resolution can be prevented from deteriorating even when the double-density conversion is performed by a simple circuit without using a frame memory. In addition, an advantageous effect that it is possible to suppress moire is obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a double-density conversion device of a video display device according to a first embodiment of the present invention.

FIG. 2 is C after double-density conversion according to the first embodiment of the present invention.
Schematic diagram showing scanning line position when RT is viewed from the side

FIG. 3 is a configuration diagram of a double-density conversion device according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional double-density conversion device.

FIG. 5: CR after double-density conversion in a conventional double-density conversion device
Schematic diagram of scanning lines when T is viewed from the side

FIG. 6 is a configuration diagram showing an example of a PLL circuit.

FIG. 7 is a waveform diagram of modulated vertical deflection current.

[Explanation of symbols]

 1 sync separation circuit 2 2 multiplication circuit 3 horizontal deflection circuit 4 vertical deflection circuit 5 PLL circuit 6 frequency division circuit 7 A / D conversion circuit 8 line memory 9 D / A conversion circuit 10 modulation circuit 11 modulation amount adjustment circuit 12 phase comparison circuit 13 integrating circuit 14 oscillating circuit 15 counter

Claims (3)

[Claims] 1. A video display device having a double-density conversion function for doubling the horizontal frequency of a video input signal for scanning.
A video display device, characterized in that the scanning positions of the scanning lines of the first field and the second field forming a frame are shifted so as not to overlap each other. 2. A sync separation circuit which receives a video signal as an input and separates a vertical sync signal and a horizontal sync signal from the video signal, and a horizontal sync signal which is an output of the sync separation circuit as an input and which has a frequency twice that of the horizontal sync signal. A doubler circuit for generating a signal, a horizontal deflector circuit for inputting an output signal of the doubler circuit and outputting a horizontal deflection current, and a vertical deflector for receiving a vertical sync signal of the output of the sync separation circuit and outputting a vertical deflection current. A deflection circuit, a modulation circuit that receives the output of the vertical deflection circuit and the output of the sync separation circuit as input, modulates the output signal of the vertical deflection circuit, and outputs the horizontal sync signal that is the output of the sync separation circuit. A PLL circuit that outputs a first clock signal from the frequency of the horizontal synchronizing signal; a frequency divider circuit that divides the first clock signal by 2 and outputs a second clock signal;
An A / D conversion circuit that performs analog-to-digital conversion with the second clock signal, and a digital video signal output from the A / D conversion circuit as an input, the digital video signal is taken in with the second clock, and the first clock An image display device characterized by comprising a line memory for outputting the digital image signal captured in (1) and a D / A conversion circuit for performing digital-analog conversion. 3. The image display device according to claim 2, further comprising a modulation amount variable circuit capable of changing the modulation amount of the modulation circuit.