JPS63117582A - Sequential scanning conversion television receiver - Google Patents

Abstract

PURPOSE:To prevent the picture quality subjected to a scanning line conversion from being deteriorated by applying the write/read of a time base conversion memory while using a required clock respectively, thereby preventing jitter between read data and a horizontal deflection driving signal. CONSTITUTION:Line and interpolation signals YR, Y1, CR and C1 via a Y/C separation/interpolation circuit 3 are written in a time base conversion memory 4 by using a 4fsc lock 100 (fsc is a subcarrier frequency) from a burst lock PLU 10. Then they are read by an 8fsc clock 101 synchronously with a horizontal synchronizing signal outputted from a 12HD clock PLU 12 receiving a horizontal synchronizing signal HD, signals Y', C' to which scanning line number is converted are outputted and a clock 101 is given to a frequency devider 13 to be horizontal deflection driving signal. Thus, no jitter exists in the read data and the horizontal deflection driving signal in the composite signal to which a chrominance subcarrier signal and a horizontal synchronizing signal are asynchronous and the deterioration in the picture quality subjected to scanning line conversion due to jitter is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a television receiver that converts the number of scanning lines of an NTSC composite signal to provide sequential scanning, and particularly to conversion of the time axis thereof.

[Conventional technology]

Current ink-lace scanning has ink-lace disturbances such as interline flicker and line crawling.
This causes image quality deterioration. Inblue Butto TV (
IDTV) performs scanning line interpolation as signal processing to convert to sequential scanning and display.

[Problem that the invention seeks to solve]

A progressive scan conversion television receiver inputs an NTSC composite signal and processes it digitally, but the clock of each processing section is a 4fsc signal generated in synchronization with the color burst.
(frequency of fscF color subcarrier) clock or its double 8f, c clock is used. 8f here. The clock is an operating clock for the time axis conversion circuit.

As mentioned above, the clock is based on the color subcarrier generated in synchronization with the color burst, but as in the case of a VTR, an NTSC composite signal is input in which the color burst and horizontal synchronization signal are not synchronized. A problem arises when In the time axis conversion circuit, 4f, c
Write the data sampled by the clock, 8f.

Although reading is performed using a clock, the relationship between the signal processing clock and horizontal synchronization is asynchronous, so there is a fluctuation (sick) in the time axis between the read data and the horizontal deflection drive signal, which degrades the image quality. .

SUMMARY OF THE INVENTION An object of the present invention is to provide a progressive scan conversion television receiver that prevents fluctuations in time axis conversion due to the above-mentioned causes.

[Means for solving problems]

In the progressive scan conversion television receiver of the present invention, the time axis conversion memory writes a line signal and an interpolated signal obtained by performing scanning line interpolation using a clock synchronized with a color subcarrier, and writes the clock synchronized with a horizontal synchronization signal. The data is read using a clock with twice the frequency.

[Effect]

Since reading from the memory is performed using a clock synchronized with the horizontal synchronizing signal and is completely synchronized with the horizontal deflection drive signal of the display device, jitter due to the above-mentioned causes does not occur.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic block diagram of a progressive scan conversion television receiver according to an embodiment, particularly showing the clock generation section in detail.

First, clock generation will be explained. Input NT
SC composite signal is burst lock PLL circuit 1
0 and generates a 4fsc clock signal 100 phase-synchronized with the color burst. Here, f3c is the frequency of the color subcarrier. It is also input to the synchronous separation circuit 11,
Horizontal sync HD signal.

Generates vertical synchronization VD signal. This HD signal is used by an HD lock PLL circuit 12 to generate a clock signal 101 whose phase is synchronized with the HD signal. The HD lock PLL circuit 12 includes a phase comparator 121. Loop filter 122. Voltage controlled oscillator 123. and a frequency divider 124. Voltage controlled oscillator 123 is 8 f sc (28,6 MHz)
The frequency divider 124 divides the output frequency into 1/1820 fH (15,75 KHz).

The above clock signal 100 is a system clock for digital signal processing, and is also a write clock for the time axis conversion memory 4. The clock signal 101 serves as a read clock for the time axis conversion memory 4, and is frequency-divided by a frequency divider 13 to 1/910. This frequency-divided output becomes an HD signal for deflection of the CRT.

Next, the operation of the circuit shown in FIG. 1 will be explained. An NTSC composite signal, which is an input signal, passes through a clamp circuit 1, is A/D converted by an A/D converter 2, and is input to a Y/C separation/interpolation circuit 3. Then, Y/C separation and motion adaptive interpolation are performed, and a Y signal/Y signal/CR multiplied signal C1 signal is output. Here, the suffix R indicates a line signal, and ■ indicates an interpolation signal. The above four signals are written into the time axis conversion memory 4, and the write clock is a 4fsc clock signal 100 synchronized with the color burst.

The read clock is a clock signal 101 whose phase is synchronized with the HD signal, and its clock rate is doubled.

The Y' signal is read out, the number of scanning lines is converted, and the C' signal is separated into RGB signals by the signal matrix circuit 5, and converted into analog signals by the D/A converters 6a, 6b, and 6c, and sent to the CRT.
Enter.

〔Effect of the invention〕

As explained in detail above, in NTSC, the color subcarrier signal and the horizontal synchronization signal are in an asynchronous relationship, such as in a VTR.
Even when a composite signal is input, the line signal/interpolation signal is read out in the time base conversion memory using a clock synchronized with the horizontal synchronizing signal, so that the HD signal for deflection of the CRT and the data are in a synchronous relationship. Therefore, no jitter occurs as in the conventional case.

[Brief explanation of the drawing]

FIG. 1 is a circuit block diagram of an embodiment of the present invention. 1-clamp circuit, 2--A/D converter, 3-Y
/C separation/interpolation circuit, 4--time axis conversion memory, 5--matrix circuit, 6 a, 6 b, 6 c--D/A converter, 10--burst lock PLL circuit, 11- -Synchronization separation circuit, 12.-HD clock LL circuit, 13.Frequency divider.

Claims (1)

[Claims] The time axis conversion memory writes a line signal and an interpolated signal obtained by performing scanning line interpolation using a clock synchronized with a color subcarrier, and reads it using a clock synchronized with a horizontal synchronization signal and having twice the frequency of the clock. A progressive scan conversion television receiver.