JPH0430789B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a television receiver suitable for application to, for example, a television receiver in which display with twice the field frequency is performed.

BACKGROUND TECHNOLOGY AND PROBLEMS The current television system uses a scanning method called interlace. That is, 1
A single image (frame) is transmitted by two vertical scans (fields), and the aim is to increase the number of scanning lines as much as possible without causing flicker to the viewer's eyes in a limited frequency band. It was designed to do so.

However, in the CCIR system mainly used in Europe, the field frequency is 50Hz, and flickering cannot be completely eliminated at this frequency, and flickering can be felt, especially on screens with high brightness.

Therefore, conventionally, it has been proposed to convert the field frequency to twice the frequency and display it. In this case, as a conversion process for color video signals, it is generally considered that three sets of field memories are used to independently process a luminance signal and two color difference signals or three primary color signals. On the other hand, since only one field memory is required and it is economical, it has been considered to process the composite signal as it is. FIG. 1 shows an example of a television receiver.

In the figure, 1 is an antenna, 2 is a tuner,
3 is an intermediate frequency amplifier, and 4 is a video detection circuit.
From the video detection circuit 4, a PAL color video signal Sv of, for example, 625 lines/frame and 50 films/sec is obtained. This video signal Sv is converted into a digital signal by an A/D converter 5 and then supplied to a conversion circuit 6.

The conversion circuit 6 includes field memories (random access memories having a storage capacity for pixels of one field period (1V)) 6a and 6b, and switch circuits 6c and 6d. switch circuit 6
c is switched to the memory 6a and 6b side every 1V,
On the other hand, the switch circuit 66d is switched to the opposite side. Further, a write clock pulse is supplied to the memory selected by the switch circuit 6c, and a read clock pulse of twice the frequency is supplied to the memory selected by the switch circuit 6d.

The video signal Sv converted into a digital signal by the A/D converter 5 is supplied to the memories 6a and 6b for 1 field every 1V via the switch circuit 6c, and is written therein, and is also read from the memories 6b and 6a. The video signal for one field written at the previous 1V is read out twice in succession with a period of 1/2V, and this is obtained via the switch circuit 6d. In other words, a double-speed field video signal Sv' whose field frequency is doubled is obtained from this switch circuit 6d.

This video signal Sv' is converted into an analog signal by a D/A converter 7 and then supplied to a signal processing circuit 8. Then, in this signal processing circuit 8, the luminance signal. Processing such as color signal separation and color demodulation is performed,
Red, green and blue primary color signals R, G and B are obtained.
Then, they are respectively supplied to the picture tube 9.

In addition, a video signal obtained from the video detection circuit 4
Sv is supplied to the synchronization separation circuit 10. The vertical synchronizing signal Pv obtained from this separation circuit 10 is doubled by a multiplier 11 to produce a signal with twice the frequency.
Pv ₂ , and this signal Pv ₂ is supplied to the deflection coil 13 through the vertical deflection circuit 12 .

In addition, the horizontal synchronization signal obtained from the separation circuit 10
P _H is doubled by the multiplier 14 to become a signal P _H2 with twice the frequency, and this signal P _H2 is sent to the horizontal deflection circuit 1.
5 to the deflection coil 13.

The example shown in FIG.
Since G and B are supplied and horizontal and vertical deflection scanning is performed at twice the speed, a color image with twice the field frequency is displayed. Therefore, even in the CCIR method described above, the field frequency is doubled to 100 Hz, and no flicker is perceived.

By the way, in this example in Figure 1, the video signal
As shown in Figure 2B, the color subcarrier signal phase-locked to the burst in Sv maintains continuity, whereas the color subcarrier signal phase-locked to the burst in the converted video signal Sv' is As shown in C in the figure, consecutive identical fields (e.g.
Continuity is no longer maintained between F ₁ and F ₁ ). Here, what is shown in A and D in the figure is a vertical synchronizing signal Pv and a signal Pv ₂ having twice the frequency thereof, respectively. In addition, in FIG. B, F ₁ and F ₂ indicate the first and second fields, and corresponding symbols are also given to C in the same figure. In this way, the video signal after conversion
Since the color subcarrier signal phase synchronized with the burst in Sv' is not continuous, in the example of FIG. 1 described above, it is necessary to switch the phase of the reference subcarrier in synchronization with this during color demodulation. For example, a continuous wave signal locked to a color burst signal extracted from the video signal Sv' is used as the reference subcarrier in this color demodulation, but considering the pull-in response, etc., the color subcarrier of the video signal Sv' mentioned above is Phase change (every 1V)
It is difficult to obtain something that corresponds to this. Therefore, it is difficult to perform sufficient color demodulation in the case where the continuity of the color subcarrier signal phase synchronized with the burst in the converted video signal Sv' cannot be maintained as in the example shown in FIG.

OBJECTS OF THE INVENTION The present invention has been made in view of the above problems, and is intended to facilitate color demodulation.

Summary of the Invention In order to achieve the above object, the present invention includes a circuit for extracting a color burst signal from a video signal and obtaining a continuous wave signal locked to the color burst signal, and a memory control circuit. The phase of the leading data written into and read out from the field memory constituting the field memory is maintained at a constant phase with the continuous wave signal, and the continuity of the color subcarrier in the converted video signal is maintained.

The present invention is configured in this manner, and the continuity of the color subcarrier in the video signal after conversion is maintained.
It is easy to obtain the reference subcarrier during color demodulation,
Color demodulation can be easily performed.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to FIG. In FIG. 3, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

In the same figure, the video signal Sv obtained from the video detection circuit 4 is sent to the A/D converter 5, for example.
One sample is converted into an 8-bit digital signal at a sampling frequency of 3sc (sc is the color subcarrier frequency). Video signal Sv converted to digital signal
is supplied to the conversion circuit 16.

The conversion circuit 16 is composed of field memories 16a and 16b and switch circuits 16c and 16d. The switch circuit 16c is switched to the memory 16a and 16b side approximately every 1 V, while the switch circuit 16d is switched to the opposite side. Further, a write clock pulse is supplied to the memory selected by the switch circuit 16c, and
A read clock pulse having twice the frequency is supplied to the memory selected by the switch circuit 16d.

The video signal Sv converted into a digital signal by the A/D converter 5 is sent to approximately 1V via the switch circuit 16c.
The video signal is supplied to the memories 16a and 16b and written to each time, and the video signal written at approximately 1V immediately before from the memories 16b and 16a is approximately 1/2V.
The data is read out twice in succession with a period of , and is obtained via the switch circuit 16d. In other words,
From this switch circuit 16d, a double-speed field video signal Sv ^* whose field frequency is doubled is obtained.

Writing to and reading from the memories 16a and 16b is controlled by a memory control circuit 17, and the leading data phase for writing to and reading from the memories 16a and 16b is determined by the color burst signal Ssc (frequency sc) extracted from the video signal Sv. ) is kept in constant phase with the continuous wave signal locked to ).

The memory control circuit 17 is locked to the color burst signal Ssc and receives continuous wave signals CW ₁ , CW 3 and CW ₃ having frequencies of 1, 3 and 6 times that of the color burst signal Ssc.
CW ₆ is supplied, as well as a vertical synchronizing signal Pv and a signal Pv ₂ having twice its frequency.

That is, the video signal obtained from the video detection circuit 4
Sv is supplied to the burst gate circuit 18. In addition, a horizontal synchronization signal obtained from the synchronization separation circuit 10
P _H is connected to the burst gate circuit 1 via the delay line 20.
8 as a gate signal. A color burst signal Ssc is obtained from the burst gate circuit 18 and is supplied to the PLL circuit 21. Then, the PLL circuit 21 locks onto the color burst signal Ssc, and obtains continuous wave signals CW ₁ , CW 3 and ₆ with frequencies 1, ₃ and 6 times that of the color burst signal Ssc.
The signals are respectively supplied to the memory control circuit 17.

Further, the vertical synchronization signal Pv obtained from the synchronization separation circuit 10 is supplied to a multiplier 11, whereby a signal Pv ₂ having twice the frequency of the vertical synchronization signal Pv is obtained. The vertical synchronization signal Pv and signal Pv ₂ are supplied to the memory control circuit 17.

The memory control circuit 17 is configured as shown in FIG. 4, for example.

The terminals 22, 23, 24, 25 and 26 include
The signals CW ₁ , CW ₃ , CW ₆ , Pv and
Pv ₂ is supplied. Further, in the figure, 27 and 28 are counters for forming a write address signal W _AD and a read address signal R _AD, respectively. Further, 29 is a switch for switching and supplying a write address signal W _AD to the memory selected by the switch circuit 16c and a read address signal R _AD to the memory selected by the switch circuit 16d. This circuit is switched in conjunction with switch circuits 16c and 16d. Further, 30 and 31 are counters 27 and 28, respectively.
This is a phase adjustment circuit for controlling the supply phase of the clear signal supplied to.

In FIG. 4, a vertical synchronizing signal Pv (shown in FIG. 2A) supplied to a terminal 25 is supplied to a phase adjustment circuit 30. Moreover, this phase adjustment circuit 30
is supplied with a continuous wave signal CW ₁ (shown in FIG. 2F) which is supplied to terminal 22. As shown in FIG. 2E, the phase adjustment circuit 30 generates the signal Pw at the first timing when the phase of the continuous wave signal CW ₁ becomes, for example, 0° after the vertical synchronization signal Pv.
This signal Pw is then supplied to the clear terminal CLR of the counter 27, and this counter 27 receives the signal Pw.
Cleared every time. Further, the signal CW ₃ supplied to the terminal 23 is supplied to the clock terminal CK of the counter 27, and the count value of the counter 27 is sequentially changed. The count value of this counter 27 is supplied to the switch circuit 29 as a write address signal W _AD .

By the way, in the above explanation, it was explained that the switch circuit 16c is switched to the memory 16a and 16b side approximately every 1V, but in reality, this signal
It can be switched at the timing of Pw. Further, the switch circuit 16d is switched to the opposite side.

In this way, the clear terminal CLR of the counter 27
The signal Pw supplied to the continuous wave signal CW ₁ is always generated at a timing when the phase of the continuous wave signal CW 1 is 0°, for example,
Since the write address signal W _AD specifies the first address of the memories 16a and 16b at this timing, the first data of the video signal written to the memories 16a and 16b is always at this timing. By the way, continuous wave signal
Since CW ₁ (shown in FIG. 2F) and the color subcarrier in the video signal Sv (shown in FIG. 2B) are in the same phase, the leading data of the video signal written to the memories 16a and 16b in this example is , video signal Sv
The phase of the color subcarrier at is 0°.

Further, in this FIG. 4, the signal Pv ₂ (shown in FIG. 2D) supplied to the terminal 26 is supplied to the phase adjustment circuit 31. Moreover, this phase adjustment circuit 31
is supplied with a continuous wave signal CW ₁ (shown in FIG. 2F) which is supplied to terminal 22. As shown in FIG. 2H, the phase adjustment circuit 31 generates the signal _PR at the first timing when the phase of the continuous wave signal CW ₁ becomes, for example, 0° after the signal Pv ₂ . and,
This signal _PR is supplied to the clear terminal CLR of the counter 28, and this counter 28 is cleared every signal R _R. In addition, the clock terminal of the counter 28
The signal CW ₆ supplied to the terminal 24 is supplied to CK, and the count value of the counter 28 is sequentially changed. The count value of this counter 28 is supplied to a switch circuit 29 as a read address signal R _AD .

In this way, the clear terminal CLR at count 28
The signal P _R supplied _to
At this timing, the read address signal R _AD designates the first address of the memories 16a and 16b. As mentioned above, the phase of the continuous wave signal CW ₁ of the first data of the video signal written in the memories 16a and 16b is always as follows.
For example, the timing is 0°.

Therefore, the color subcarrier signal phase synchronized with the burst in the converted video signal Sv ^* obtained from the switch circuit 16d maintains continuity as shown in FIG. 2G.

Note that since the writing and reading times to and from the memories 16a and 16b change, some data may be missing in the video signal Sv ^* , but the continuity of color subcarriers in the video signal Sv ^* is as described above. As long as writing and reading are done in a phase relationship, there will be no damage. Moreover, this lack is slight and there is no problem on the screen.

Further, in FIG. 3, the video signal Sv ^* obtained from the switch circuit 16d is converted into an analog signal by the D/A converter 7 and then supplied to the signal processing circuit 8. Then, from this signal processing circuit 8, red,
Green and blue primary color signals R, G and B are obtained and supplied to the picture tube 9, respectively.

Also, the video signal Sv ^* obtained from the D/A converter 7
is supplied to the horizontal synchronization separation circuit 19. A horizontal synchronizing signal P _H2 ' (having twice the normal frequency) obtained from this separation circuit 19 is supplied to the deflection coil 13 through the horizontal deflection circuit 15.

This example is constructed as described above, and the picture tube 9 receives primary color signals R, G, and
B is supplied, and the horizontal and vertical deflection scans are
Since the image is displayed at twice the speed, the picture tube 9 displays a color image at twice the field frequency, as in the example shown in FIG.

According to this example, the continuity of the color subcarrier signal phase-synchronized with the burst in the converted video signal Sv ^* is maintained, so it is easy to obtain the reference subcarrier for color demodulation. Color demodulation can be performed more easily than in the example shown in FIG.

In the above embodiments, the case where the video signal is a PAL video signal has been described, but the present invention can be similarly applied to a case where the video signal is a PAL video signal, for example, a color video signal of the NTSC system. Further, in the above embodiment, two field memories 16a, 16
Although the present invention has been shown as an example using B, the present invention can be similarly applied to, for example, a device in which writing and reading are performed in a single memory in a time-division manner to obtain a video signal with twice the field frequency. can do.

In addition, in the above embodiment, the field frequency is set to 2.
Although the present invention is not limited to this, the present invention can be similarly applied to converting the field frequency by 3 times, 4 times, and so on.

Effects of the Invention According to the present invention described above, the continuity of the color subcarrier signal phase-synchronized with the burst in the converted video signal is maintained, so it is not necessary to switch the phase of the reference subcarrier during color demodulation. Therefore, it is easy to obtain this reference subcarrier, and color demodulation can be easily performed.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional television receiver, Fig. 2 is a diagram for explaining the present invention, Fig. 3 is a block diagram showing an embodiment of the present invention, and Fig. 4 is a memory FIG. 3 is a specific configuration diagram of a control circuit. 16 is a conversion circuit, 17 is a memory control circuit, 18 is a burst gate circuit, and 21 is a PLL circuit.

Claims (1)

[Claims] 1. In a television receiver that receives an interlaced video signal, converts the field frequency of the video signal using a field memory, and then supplies it to a picture tube, extracts a color burst signal from the video signal and locks it. A circuit for obtaining a continuous wave signal and a memory control circuit are provided, and under the control of the memory control circuit, the phase of the leading data for writing to and reading from the field memory is maintained at a constant phase with the continuous wave signal, and A television receiver characterized in that the continuity of a carrier signal phase-synchronized with a burst in a video signal is maintained.