JPH09219450A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce irregularity of contact resistance in a via-hole in a semiconductor device having multilayer wiring. SOLUTION: A BPSG film 2 is formed on an Si substrate 1 on which a semiconductor element is formed, and a lower layer wiring (a Ti film 3, a TiN film 4 and an AlSiCu film 5) is formed in a contact hole thereof. On the upper part of the lower layer wiring, an anti-reflective coating (a Ti film 6 and a TiN film 7) is formed, and an insulating film (a P-SiN film 8, a first TEOS film 9, an SOG film 10 and a second TEOS film 11) is formed thereon. A via-hole is formed in these insulating film and anti-reflective coating (a plurality of via-holes are formed in the wafer though only one is shown in the drawing). Then, an upper layer wiring (a Ti film 12, an AlSiCu film 13 and a TiN film 14) is formed. In forming the via-hole, the upper part of the lower layer wiring on the outermost peripheral portion of the wafer is over-etched at least 80nm or more.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having multi-layer wiring.

[0002]

When manufacturing a semiconductor device having multilayer wiring, a lower layer wiring is formed on a wafer on which semiconductor elements are formed, and the lower layer wiring is patterned by etching using a resist pattern. After forming an interlayer insulating film, a via hole is formed to form an upper layer wiring.

In the formation of the resist pattern described above, when the reflected light from the lower layer wiring interferes with the incident light in the resist when exposing the resist, the resist pattern cannot be formed finely and the resist line width is locally reduced. However, there is a problem that it becomes thinner. JP-A-6-69122 discloses that when a contact hole is formed in an interlayer insulating film,
It is disclosed that an antireflection film is formed on an interlayer insulating film to form a fine resist pattern.

Therefore, even in the case of forming a multi-layer wiring, a resist pattern can be finely formed by forming an antireflection film on the lower wiring. However, as the lower layer wiring, AlSi containing aluminum (Al) as a main component is used.
A Cu film is used, and an antireflection film in which a titanium (Ti) film and a titanium nitride (TiN) film are laminated is formed on the Cu film, and an insulating film including an SOG film is further formed thereon, and the insulating film is formed by dry etching. Then, the antireflection film was removed to form a via hole, and the upper wiring of the Ti film and the AlSiCu film was formed on the via hole. As a result, the contact resistance varied between the central portion and the peripheral portion of the wafer.

An object of the present invention is to reduce such resistance variations.

[0006]

Means for Solving the Problems The inventors of the present invention have made the following examinations regarding the cause of the resistance variation. When the SOG film is formed on the lower layer wiring, it is heat-treated and cured. During the heat treatment, Ti of the antireflection film diffuses into the lower layer wiring and reacts with Al to react Al on the lower layer wiring.
It is considered that an alloy layer of Ti and Ti is formed.

When the via hole is formed by etching, the etching rate is different between the central portion and the outer peripheral portion of the wafer depending on manufacturing conditions. For example, if the etching rate at the outer peripheral portion of the wafer is slow, the depth of the via hole at the outer peripheral portion of the wafer is large. Becomes shallower. Therefore, when the via hole is formed, Al and T formed on the upper portion of the lower layer wiring are formed in the central portion and the outer peripheral portion of the wafer.
It is considered that the depth at which the alloy layer of i was removed was different, which caused variations in contact resistance.

Therefore, the contact resistance was measured by forming the measurement pattern shown in FIG. That is, after forming a lower layer wiring (a laminated film of a Ti film, a TiN film, and an AlSiCu film) on a wafer, forming an insulating film including an SOG film on the lower layer wiring, forming a plurality of via holes, and thereafter forming an upper layer wiring. (Ti film and AlSiCu film laminated film) is formed to form a plurality (for example, 40 places) of measurement patterns, and a voltage is applied from one end to the other end of each measurement pattern to detect a current and detect a contact resistance. It was measured.

Here, as shown in FIG. 5, in the central portion and the outer peripheral portion of the wafer, as shown in enlarged sectional views (enlarged view of a portion surrounded by a circle in FIG. 4), the upper portion of the lower layer wiring is shown. The etching depths d (hereinafter, referred to as over-etching amount) are different. Then, the overetch amount at the outermost peripheral portion having the slowest etching rate is set to 63 nm, 80 n
m and 95 nm, the contact resistance was measured in the above plurality of measurement patterns. FIG. 6 shows the result. When the overetch amount is 63 nm, the resistance variation in each measurement pattern is large, but when the overetch amount is 80 nm or more, the resistance variation is greatly reduced. FIG. 7 shows a graph of the results shown in FIG. 6 with the resistance variation value as the vertical axis. From this figure, it can be seen that when the overetch amount is 80 nm or more, the resistance variation is greatly reduced in a saturated manner.

Therefore, if the over-etch amount is 80 nm or more, the resistance variation can be greatly reduced. FIG. 8 shows a Depth Profile (only Al and Ti are shown and other components are omitted) of the lower layer wiring before the via hole is formed. The sputtering rate is 12 nm / min, the horizontal axis represents the sputtering time from the surface of the lower layer wiring, and the vertical axis represents the waveform intensity. The sputtering time on the horizontal axis corresponds to the depth from the surface of the lower layer wiring.

From this Depth Profile, T in the lower layer wiring
It can be seen that i diffuses and an alloy layer of Al and Ti is formed. A when the overetch amount is 80 nm
Since the ratio of Ti to Ti (Ti / Al) is 18.8%, in the outermost peripheral portion where the etching rate is the slowest,
If the etching is overetched to a depth where the ratio becomes 18.8% or less, the resistance variation can be greatly reduced.

The present invention is based on the above-mentioned investigation,
According to the first aspect of the invention, when forming a plurality of via holes in a wafer, at least 80 upper portions of the lower layer wiring are formed at the via hole formation location having the slowest etching rate.
It is characterized in that over-etching is performed by nm or more. According to the second aspect of the present invention, when forming a plurality of via holes in the wafer, the ratio of Ti to Al is at least 18.8% or less at the upper part of the lower layer wiring at the place where the via hole having the slowest etching rate is formed. It is characterized by over-etching to a certain depth.

According to the invention described in claims 1 and 2, it is possible to greatly reduce the variation in the contact resistance. As the antireflection film, a laminated film of a Ti film and a TiN film formed thereon can be used as in the invention of claim 3.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention shown in the drawings will be described. FIG. 1 shows a partial sectional structure of a semiconductor device according to an embodiment of the present invention. A BPSG film 2 is formed as an interlayer insulating film on a Si substrate 1 on which semiconductor elements such as transistors are formed. Contact holes are formed in the BPSG film 2, and the Si substrate 1
The semiconductor element formed on the substrate and the lower layer wiring are electrically connected. The lower wiring is a Ti film 3 / Ti that forms a barrier metal.
It is composed of an N film 4 and an AlSiCu film 5.

A Ti film 6 / TiN film 7 is formed as an antireflection film on the lower layer wiring, and a P-SiN film 8, a first TEOS film 9 and an SOG film 1 are further formed as insulating films.
0, the second TEOS film 11 is formed. Further, via holes are formed in the insulating film and the antireflection film,
An upper layer wiring including an i film 12, an AlSiCu film 13, and a TiN film 14 is formed. The Ti films 6 and 12 are
It is formed to suppress aluminum voids in the AlSiCu films 5 and 13.

Incidentally, the one shown in FIG. 1 shows a part of the whole wafer, and a plurality of via holes are formed in the wafer to electrically connect the lower layer wiring and the upper layer wiring at a plurality of points. It is like this. Next, a method of manufacturing the above semiconductor device will be described. [Process of FIG. 2A] First, on the Si substrate 1 on which semiconductor elements such as transistors are formed, BPS is used as an interlayer insulating film.
After depositing the G film 2 and performing reflow, a contact hole is formed in the BPSG film 2. This contact hole is formed using a photolithography process and an etching process. [Step of FIG. 2 (b)] In order to form the lower wiring and the antireflection film, a continuous process using a sputtering method is performed.
The Ti film 3, the TiN film 4, and the AlSiCu film 5 are set to 400 to 5
The Ti film 6 is formed to a thickness of 10 to 30 nm and the TiN film 7 is formed to a thickness of 20 to 40 nm. [Process of FIG. 2C] Resist 1 using photolithography process
5 is patterned. In this case, a resist pattern can be finely formed by the antireflection film described above. [Process of FIG. 2D] Using the resist 15 as a mask, the lower wiring and the antireflection film are etched in a microwave dry etching process. [Step of FIG. 2E] As the insulating film between the lower layer wiring and the upper layer wiring, first, the P-SiN film 8 and the first TEOS film 9 are sequentially deposited by using the plasma CVD method. Next, an SOG film is applied to flatten the underlying step, and a cure is performed at 450 ° C. for 30 minutes to remove the solvent. Then, SO
The G film is etched back to form the SOG film 10 only on the step portion. After that, the second TEO is formed by using the plasma CVD method.
The S film 11 is deposited. [Process of FIG. 3A] In order to form a plurality of via holes for electrically connecting the lower layer wiring and the upper layer wiring, the resist 16 is patterned by using a photolithography process. [Step of FIG. 3B] Using the resist 16 as a mask, first, wet etching is performed with a BHF solution for removing the pin angle of the via hole, and then the insulating film and the antireflection film are removed by ion reactive plasma etching. Then, the upper portion of the AlSiCu film 5 is etched.
In this case, the upper part of the AlSiCu film 5 is 80
Etching conditions are set so that etching is performed for m or more. [Process of FIG. 3C] Ti is formed by using a sputtering method.
The film 12 and the AlSiCu film 13 are formed, exposed to the air once, and then the TiN film 14 is formed to 30 nm. These are patterned by using a photolithography process and an etching process to form an upper wiring.

In this way, the semiconductor device shown in FIG. 1 is formed. In the above embodiment, the Ti film 3 / TiN film 4 and the AlS film forming the barrier metal are used as the lower wiring.
Although the iCu film 5 is shown, the lower layer wiring according to the present invention only needs to have a surface whose surface is a wiring layer containing Al as a main component. Therefore, the lower layer wiring should be composed of only the AlSiCu film 5. May be.

Although the insulating film includes the SOG film 10, another insulating film requiring a heat treatment step may be used instead of the SOG film. Further, as the antireflection film, titanium tungsten (TiW) or the like may be used instead of the TiN film 7. Further, the present invention can be applied not only to the two-layer structure of the lower layer wiring and the upper layer wiring but also to the multilayer wiring of three or more layers.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a process drawing showing a process for manufacturing the semiconductor device shown in FIG.

FIG. 3 is a process drawing showing a process that follows FIG.

FIG. 4 is a schematic partial cross-sectional view showing a measurement pattern for measuring the resistance of a lower layer wiring and an upper layer wiring.

FIG. 5 is a diagram showing that, when a plurality of via holes are formed in a wafer, the amount of overetching of the lower layer wiring is different between the central portion and the peripheral portion.

FIG. 6 is a diagram showing an experimental result of measuring a variation in resistance value with respect to an overetch amount.

FIG. 7 is a diagram showing the resistance variation value as the vertical axis in the result shown in FIG. 6;

FIG. 8 Depth Profil of Al and Ti in AlSiCu film
It is a figure which shows e.

[Explanation of symbols]

1 ... Si substrate, 2 ... BPSG film, 3 ... Ti film, 4 ... Ti
N film, 5 ... AlSiCu film, 6 ... Ti film, 7 ... TiN
Film, 8 ... P-SiN film, 9 ... First TEOS film, 10 ... S
OG film, 11 ... Second TEOS film, 12 ... Ti film, 13 ...
AlSiCu film, 14 ... TiN film.

Claims (3)

[Claims] 1. A wafer on which a semiconductor element is formed (1,
In 2), lower layer wiring (3 to 5) whose surface is a wiring layer containing aluminum as a main component is formed, a titanium-based antireflection film (6, 7) is formed thereon, and then an insulating film is formed. (8-1
1) is formed, the insulating film and the antireflection film are etched at a plurality of locations on the wafer to form a plurality of via holes, and an upper layer wiring (12) electrically connected to the lower layer wiring is formed.
To 14) are formed, the step of forming the insulating film includes the step of performing heat treatment, and the etching step of forming the plurality of via holes is the most etching. A method for manufacturing a semiconductor device, characterized in that the upper portion of the lower layer wiring is over-etched by at least 80 nm or more at a formation position of a slow via hole. 2. A wafer (1,
In 2), lower layer wiring (3 to 5) whose surface is a wiring layer containing aluminum as a main component is formed, a titanium-based antireflection film (6, 7) is formed thereon, and then an insulating film is formed. (8-1
1) is formed, the insulating film and the antireflection film are etched at a plurality of locations on the wafer to form a plurality of via holes, and an upper layer wiring (12) electrically connected to the lower layer wiring is formed.
To 14) are formed, the step of forming the insulating film includes the step of performing heat treatment, and the etching step of forming the plurality of via holes is the most etching. A method of manufacturing a semiconductor device, comprising: overetching an upper portion of the lower layer wiring at least at a depth where a ratio of titanium to aluminum is 18.8% or less at a formation position of a slow via hole. 3. The semiconductor device according to claim 1, wherein the antireflection film includes a titanium film formed on the lower wiring and a titanium nitride film formed on the titanium film. Production method.